* [PATCH] i386: Simplify {,v}ph{add,sub{,s}{w,d} insn patterns [PR94460]
@ 2020-04-03 22:41 Jakub Jelinek
2020-04-04 22:03 ` [PATCH] i386: Simplify {, v}ph{add, sub{, s}{w, d} " Uros Bizjak
0 siblings, 1 reply; 2+ messages in thread
From: Jakub Jelinek @ 2020-04-03 22:41 UTC (permalink / raw)
To: Uros Bizjak; +Cc: gcc-patches
Hi!
As mentioned in the previous PR94460 patch, the RTL patterns look too
large/complicated, we can simplify them by just performing two 2 arg
permutations to move the arguments into the right spots and then just
doing the plus/minus (or signed saturation version thereof).
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for stage1?
2020-04-04 Jakub Jelinek <jakub@redhat.com>
PR target/94460
* config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3,
ssse3_ph<plusminus_mnemonic>wv8hi3, ssse3_ph<plusminus_mnemonic>wv4hi3,
avx2_ph<plusminus_mnemonic>dv8si3, ssse3_ph<plusminus_mnemonic>dv4si3,
ssse3_ph<plusminus_mnemonic>dv2si3): Simplify RTL patterns.
--- gcc/config/i386/sse.md.jj 2020-04-03 10:21:51.110564277 +0200
+++ gcc/config/i386/sse.md 2020-04-03 11:55:04.455963720 +0200
@@ -16038,73 +16038,23 @@ (define_code_iterator ssse3_plusminus [p
(define_insn "avx2_ph<plusminus_mnemonic>wv16hi3"
[(set (match_operand:V16HI 0 "register_operand" "=x")
- (vec_concat:V16HI
- (vec_concat:V8HI
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ssse3_plusminus:HI
- (vec_select:HI
- (match_operand:V16HI 1 "register_operand" "x")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ssse3_plusminus:HI
- (vec_select:HI
- (match_operand:V16HI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 7)]))))))
- (vec_concat:V8HI
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 8)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 9)])))
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 10)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 11)]))))
- (vec_concat:V2HI
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 12)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 13)])))
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 14)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 15)])))))
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 8)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 9)])))
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 10)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 11)]))))
- (vec_concat:V2HI
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 12)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 13)])))
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 14)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 15)]))))))))]
+ (ssse3_plusminus:V16HI
+ (vec_select:V16HI
+ (vec_concat:V32HI
+ (match_operand:V16HI 1 "register_operand" "x")
+ (match_operand:V16HI 2 "nonimmediate_operand" "xm"))
+ (parallel
+ [(const_int 0) (const_int 2) (const_int 4) (const_int 6)
+ (const_int 16) (const_int 18) (const_int 20) (const_int 22)
+ (const_int 8) (const_int 10) (const_int 12) (const_int 14)
+ (const_int 24) (const_int 26) (const_int 28) (const_int 30)]))
+ (vec_select:V16HI
+ (vec_concat:V32HI (match_dup 1) (match_dup 2))
+ (parallel
+ [(const_int 1) (const_int 3) (const_int 5) (const_int 7)
+ (const_int 17) (const_int 19) (const_int 21) (const_int 23)
+ (const_int 9) (const_int 11) (const_int 13) (const_int 15)
+ (const_int 25) (const_int 27) (const_int 29) (const_int 31)]))))]
"TARGET_AVX2"
"vph<plusminus_mnemonic>w\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
@@ -16114,41 +16064,19 @@ (define_insn "avx2_ph<plusminus_mnemonic
(define_insn "ssse3_ph<plusminus_mnemonic>wv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x,x")
- (vec_concat:V8HI
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ssse3_plusminus:HI
- (vec_select:HI
- (match_operand:V8HI 1 "register_operand" "0,x")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ssse3_plusminus:HI
- (vec_select:HI
- (match_operand:V8HI 2 "vector_operand" "xBm,xm")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
+ (ssse3_plusminus:V8HI
+ (vec_select:V8HI
+ (vec_concat:V16HI
+ (match_operand:V8HI 1 "register_operand" "0,x")
+ (match_operand:V8HI 2 "vector_operand" "xBm,xm"))
+ (parallel
+ [(const_int 0) (const_int 2) (const_int 4) (const_int 6)
+ (const_int 8) (const_int 10) (const_int 12) (const_int 14)]))
+ (vec_select:V8HI
+ (vec_concat:V16HI (match_dup 1) (match_dup 2))
+ (parallel
+ [(const_int 1) (const_int 3) (const_int 5) (const_int 7)
+ (const_int 9) (const_int 11) (const_int 13) (const_int 15)]))))]
"TARGET_SSSE3"
"@
ph<plusminus_mnemonic>w\t{%2, %0|%0, %2}
@@ -16163,25 +16091,17 @@ (define_insn "ssse3_ph<plusminus_mnemoni
(define_insn_and_split "ssse3_ph<plusminus_mnemonic>wv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv")
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ssse3_plusminus:HI
- (vec_select:HI
- (match_operand:V4HI 1 "register_operand" "0,0,Yv")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2HI
- (ssse3_plusminus:HI
- (vec_select:HI
- (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
+ (ssse3_plusminus:V4HI
+ (vec_select:V4HI
+ (vec_concat:V8HI
+ (match_operand:V4HI 1 "register_operand" "0,0,Yv")
+ (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv"))
+ (parallel
+ [(const_int 0) (const_int 2) (const_int 4) (const_int 6)]))
+ (vec_select:V4HI
+ (vec_concat:V8HI (match_dup 1) (match_dup 2))
+ (parallel
+ [(const_int 1) (const_int 3) (const_int 5) (const_int 7)]))))]
"(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
"@
ph<plusminus_mnemonic>w\t{%2, %0|%0, %2}
@@ -16211,41 +16131,19 @@ (define_insn_and_split "ssse3_ph<plusmin
(define_insn "avx2_ph<plusminus_mnemonic>dv8si3"
[(set (match_operand:V8SI 0 "register_operand" "=x")
- (vec_concat:V8SI
- (vec_concat:V4SI
- (vec_concat:V2SI
- (plusminus:SI
- (vec_select:SI
- (match_operand:V8SI 1 "register_operand" "x")
- (parallel [(const_int 0)]))
- (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
- (plusminus:SI
- (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2SI
- (plusminus:SI
- (vec_select:SI
- (match_operand:V8SI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)]))
- (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
- (plusminus:SI
- (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:SI (match_dup 2) (parallel [(const_int 3)])))))
- (vec_concat:V4SI
- (vec_concat:V2SI
- (plusminus:SI
- (vec_select:SI (match_dup 1) (parallel [(const_int 4)]))
- (vec_select:SI (match_dup 1) (parallel [(const_int 5)])))
- (plusminus:SI
- (vec_select:SI (match_dup 1) (parallel [(const_int 6)]))
- (vec_select:SI (match_dup 1) (parallel [(const_int 7)]))))
- (vec_concat:V2SI
- (plusminus:SI
- (vec_select:SI (match_dup 2) (parallel [(const_int 4)]))
- (vec_select:SI (match_dup 2) (parallel [(const_int 5)])))
- (plusminus:SI
- (vec_select:SI (match_dup 2) (parallel [(const_int 6)]))
- (vec_select:SI (match_dup 2) (parallel [(const_int 7)])))))))]
+ (plusminus:V8SI
+ (vec_select:V8SI
+ (vec_concat:V16SI
+ (match_operand:V8SI 1 "register_operand" "x")
+ (match_operand:V8SI 2 "nonimmediate_operand" "xm"))
+ (parallel
+ [(const_int 0) (const_int 2) (const_int 8) (const_int 10)
+ (const_int 4) (const_int 6) (const_int 12) (const_int 14)]))
+ (vec_select:V8SI
+ (vec_concat:V16SI (match_dup 1) (match_dup 2))
+ (parallel
+ [(const_int 1) (const_int 3) (const_int 9) (const_int 11)
+ (const_int 5) (const_int 7) (const_int 13) (const_int 15)]))))]
"TARGET_AVX2"
"vph<plusminus_mnemonic>d\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
@@ -16255,25 +16153,17 @@ (define_insn "avx2_ph<plusminus_mnemonic
(define_insn "ssse3_ph<plusminus_mnemonic>dv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x,x")
- (vec_concat:V4SI
- (vec_concat:V2SI
- (plusminus:SI
- (vec_select:SI
- (match_operand:V4SI 1 "register_operand" "0,x")
- (parallel [(const_int 0)]))
- (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
- (plusminus:SI
- (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
- (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
- (vec_concat:V2SI
- (plusminus:SI
- (vec_select:SI
- (match_operand:V4SI 2 "vector_operand" "xBm,xm")
- (parallel [(const_int 0)]))
- (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
- (plusminus:SI
- (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
+ (plusminus:V4SI
+ (vec_select:V4SI
+ (vec_concat:V8SI
+ (match_operand:V4SI 1 "register_operand" "0,x")
+ (match_operand:V4SI 2 "vector_operand" "xBm,xm"))
+ (parallel
+ [(const_int 0) (const_int 2) (const_int 4) (const_int 6)]))
+ (vec_select:V4SI
+ (vec_concat:V8SI (match_dup 1) (match_dup 2))
+ (parallel
+ [(const_int 1) (const_int 3) (const_int 5) (const_int 7)]))))]
"TARGET_SSSE3"
"@
ph<plusminus_mnemonic>d\t{%2, %0|%0, %2}
@@ -16288,17 +16178,15 @@ (define_insn "ssse3_ph<plusminus_mnemoni
(define_insn_and_split "ssse3_ph<plusminus_mnemonic>dv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
- (vec_concat:V2SI
- (plusminus:SI
- (vec_select:SI
+ (plusminus:V2SI
+ (vec_select:V2SI
+ (vec_concat:V4SI
(match_operand:V2SI 1 "register_operand" "0,0,Yv")
- (parallel [(const_int 0)]))
- (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
- (plusminus:SI
- (vec_select:SI
- (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv")
- (parallel [(const_int 0)]))
- (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
+ (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv"))
+ (parallel [(const_int 0) (const_int 2)]))
+ (vec_select:V2SI
+ (vec_concat:V4SI (match_dup 1) (match_dup 2))
+ (parallel [(const_int 1) (const_int 3)]))))]
"(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
"@
ph<plusminus_mnemonic>d\t{%2, %0|%0, %2}
Jakub
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] i386: Simplify {, v}ph{add, sub{, s}{w, d} insn patterns [PR94460]
2020-04-03 22:41 [PATCH] i386: Simplify {,v}ph{add,sub{,s}{w,d} insn patterns [PR94460] Jakub Jelinek
@ 2020-04-04 22:03 ` Uros Bizjak
0 siblings, 0 replies; 2+ messages in thread
From: Uros Bizjak @ 2020-04-04 22:03 UTC (permalink / raw)
To: Jakub Jelinek; +Cc: gcc-patches
On Sat, Apr 4, 2020 at 12:41 AM Jakub Jelinek <jakub@redhat.com> wrote:
>
> Hi!
>
> As mentioned in the previous PR94460 patch, the RTL patterns look too
> large/complicated, we can simplify them by just performing two 2 arg
> permutations to move the arguments into the right spots and then just
> doing the plus/minus (or signed saturation version thereof).
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for stage1?
>
> 2020-04-04 Jakub Jelinek <jakub@redhat.com>
>
> PR target/94460
> * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3,
> ssse3_ph<plusminus_mnemonic>wv8hi3, ssse3_ph<plusminus_mnemonic>wv4hi3,
> avx2_ph<plusminus_mnemonic>dv8si3, ssse3_ph<plusminus_mnemonic>dv4si3,
> ssse3_ph<plusminus_mnemonic>dv2si3): Simplify RTL patterns.
OK.
Thanks,
Uros.
> --- gcc/config/i386/sse.md.jj 2020-04-03 10:21:51.110564277 +0200
> +++ gcc/config/i386/sse.md 2020-04-03 11:55:04.455963720 +0200
> @@ -16038,73 +16038,23 @@ (define_code_iterator ssse3_plusminus [p
>
> (define_insn "avx2_ph<plusminus_mnemonic>wv16hi3"
> [(set (match_operand:V16HI 0 "register_operand" "=x")
> - (vec_concat:V16HI
> - (vec_concat:V8HI
> - (vec_concat:V4HI
> - (vec_concat:V2HI
> - (ssse3_plusminus:HI
> - (vec_select:HI
> - (match_operand:V16HI 1 "register_operand" "x")
> - (parallel [(const_int 0)]))
> - (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
> - (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
> - (vec_concat:V2HI
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
> - (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
> - (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
> - (vec_concat:V4HI
> - (vec_concat:V2HI
> - (ssse3_plusminus:HI
> - (vec_select:HI
> - (match_operand:V16HI 2 "nonimmediate_operand" "xm")
> - (parallel [(const_int 0)]))
> - (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
> - (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
> - (vec_concat:V2HI
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
> - (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
> - (vec_select:HI (match_dup 2) (parallel [(const_int 7)]))))))
> - (vec_concat:V8HI
> - (vec_concat:V4HI
> - (vec_concat:V2HI
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 1) (parallel [(const_int 8)]))
> - (vec_select:HI (match_dup 1) (parallel [(const_int 9)])))
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 1) (parallel [(const_int 10)]))
> - (vec_select:HI (match_dup 1) (parallel [(const_int 11)]))))
> - (vec_concat:V2HI
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 1) (parallel [(const_int 12)]))
> - (vec_select:HI (match_dup 1) (parallel [(const_int 13)])))
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 1) (parallel [(const_int 14)]))
> - (vec_select:HI (match_dup 1) (parallel [(const_int 15)])))))
> - (vec_concat:V4HI
> - (vec_concat:V2HI
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 2) (parallel [(const_int 8)]))
> - (vec_select:HI (match_dup 2) (parallel [(const_int 9)])))
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 2) (parallel [(const_int 10)]))
> - (vec_select:HI (match_dup 2) (parallel [(const_int 11)]))))
> - (vec_concat:V2HI
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 2) (parallel [(const_int 12)]))
> - (vec_select:HI (match_dup 2) (parallel [(const_int 13)])))
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 2) (parallel [(const_int 14)]))
> - (vec_select:HI (match_dup 2) (parallel [(const_int 15)]))))))))]
> + (ssse3_plusminus:V16HI
> + (vec_select:V16HI
> + (vec_concat:V32HI
> + (match_operand:V16HI 1 "register_operand" "x")
> + (match_operand:V16HI 2 "nonimmediate_operand" "xm"))
> + (parallel
> + [(const_int 0) (const_int 2) (const_int 4) (const_int 6)
> + (const_int 16) (const_int 18) (const_int 20) (const_int 22)
> + (const_int 8) (const_int 10) (const_int 12) (const_int 14)
> + (const_int 24) (const_int 26) (const_int 28) (const_int 30)]))
> + (vec_select:V16HI
> + (vec_concat:V32HI (match_dup 1) (match_dup 2))
> + (parallel
> + [(const_int 1) (const_int 3) (const_int 5) (const_int 7)
> + (const_int 17) (const_int 19) (const_int 21) (const_int 23)
> + (const_int 9) (const_int 11) (const_int 13) (const_int 15)
> + (const_int 25) (const_int 27) (const_int 29) (const_int 31)]))))]
> "TARGET_AVX2"
> "vph<plusminus_mnemonic>w\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "type" "sseiadd")
> @@ -16114,41 +16064,19 @@ (define_insn "avx2_ph<plusminus_mnemonic
>
> (define_insn "ssse3_ph<plusminus_mnemonic>wv8hi3"
> [(set (match_operand:V8HI 0 "register_operand" "=x,x")
> - (vec_concat:V8HI
> - (vec_concat:V4HI
> - (vec_concat:V2HI
> - (ssse3_plusminus:HI
> - (vec_select:HI
> - (match_operand:V8HI 1 "register_operand" "0,x")
> - (parallel [(const_int 0)]))
> - (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
> - (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
> - (vec_concat:V2HI
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
> - (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
> - (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
> - (vec_concat:V4HI
> - (vec_concat:V2HI
> - (ssse3_plusminus:HI
> - (vec_select:HI
> - (match_operand:V8HI 2 "vector_operand" "xBm,xm")
> - (parallel [(const_int 0)]))
> - (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
> - (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
> - (vec_concat:V2HI
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
> - (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
> - (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
> + (ssse3_plusminus:V8HI
> + (vec_select:V8HI
> + (vec_concat:V16HI
> + (match_operand:V8HI 1 "register_operand" "0,x")
> + (match_operand:V8HI 2 "vector_operand" "xBm,xm"))
> + (parallel
> + [(const_int 0) (const_int 2) (const_int 4) (const_int 6)
> + (const_int 8) (const_int 10) (const_int 12) (const_int 14)]))
> + (vec_select:V8HI
> + (vec_concat:V16HI (match_dup 1) (match_dup 2))
> + (parallel
> + [(const_int 1) (const_int 3) (const_int 5) (const_int 7)
> + (const_int 9) (const_int 11) (const_int 13) (const_int 15)]))))]
> "TARGET_SSSE3"
> "@
> ph<plusminus_mnemonic>w\t{%2, %0|%0, %2}
> @@ -16163,25 +16091,17 @@ (define_insn "ssse3_ph<plusminus_mnemoni
>
> (define_insn_and_split "ssse3_ph<plusminus_mnemonic>wv4hi3"
> [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv")
> - (vec_concat:V4HI
> - (vec_concat:V2HI
> - (ssse3_plusminus:HI
> - (vec_select:HI
> - (match_operand:V4HI 1 "register_operand" "0,0,Yv")
> - (parallel [(const_int 0)]))
> - (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
> - (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
> - (vec_concat:V2HI
> - (ssse3_plusminus:HI
> - (vec_select:HI
> - (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv")
> - (parallel [(const_int 0)]))
> - (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
> - (ssse3_plusminus:HI
> - (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
> - (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
> + (ssse3_plusminus:V4HI
> + (vec_select:V4HI
> + (vec_concat:V8HI
> + (match_operand:V4HI 1 "register_operand" "0,0,Yv")
> + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv"))
> + (parallel
> + [(const_int 0) (const_int 2) (const_int 4) (const_int 6)]))
> + (vec_select:V4HI
> + (vec_concat:V8HI (match_dup 1) (match_dup 2))
> + (parallel
> + [(const_int 1) (const_int 3) (const_int 5) (const_int 7)]))))]
> "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
> "@
> ph<plusminus_mnemonic>w\t{%2, %0|%0, %2}
> @@ -16211,41 +16131,19 @@ (define_insn_and_split "ssse3_ph<plusmin
>
> (define_insn "avx2_ph<plusminus_mnemonic>dv8si3"
> [(set (match_operand:V8SI 0 "register_operand" "=x")
> - (vec_concat:V8SI
> - (vec_concat:V4SI
> - (vec_concat:V2SI
> - (plusminus:SI
> - (vec_select:SI
> - (match_operand:V8SI 1 "register_operand" "x")
> - (parallel [(const_int 0)]))
> - (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
> - (plusminus:SI
> - (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
> - (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
> - (vec_concat:V2SI
> - (plusminus:SI
> - (vec_select:SI
> - (match_operand:V8SI 2 "nonimmediate_operand" "xm")
> - (parallel [(const_int 0)]))
> - (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
> - (plusminus:SI
> - (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
> - (vec_select:SI (match_dup 2) (parallel [(const_int 3)])))))
> - (vec_concat:V4SI
> - (vec_concat:V2SI
> - (plusminus:SI
> - (vec_select:SI (match_dup 1) (parallel [(const_int 4)]))
> - (vec_select:SI (match_dup 1) (parallel [(const_int 5)])))
> - (plusminus:SI
> - (vec_select:SI (match_dup 1) (parallel [(const_int 6)]))
> - (vec_select:SI (match_dup 1) (parallel [(const_int 7)]))))
> - (vec_concat:V2SI
> - (plusminus:SI
> - (vec_select:SI (match_dup 2) (parallel [(const_int 4)]))
> - (vec_select:SI (match_dup 2) (parallel [(const_int 5)])))
> - (plusminus:SI
> - (vec_select:SI (match_dup 2) (parallel [(const_int 6)]))
> - (vec_select:SI (match_dup 2) (parallel [(const_int 7)])))))))]
> + (plusminus:V8SI
> + (vec_select:V8SI
> + (vec_concat:V16SI
> + (match_operand:V8SI 1 "register_operand" "x")
> + (match_operand:V8SI 2 "nonimmediate_operand" "xm"))
> + (parallel
> + [(const_int 0) (const_int 2) (const_int 8) (const_int 10)
> + (const_int 4) (const_int 6) (const_int 12) (const_int 14)]))
> + (vec_select:V8SI
> + (vec_concat:V16SI (match_dup 1) (match_dup 2))
> + (parallel
> + [(const_int 1) (const_int 3) (const_int 9) (const_int 11)
> + (const_int 5) (const_int 7) (const_int 13) (const_int 15)]))))]
> "TARGET_AVX2"
> "vph<plusminus_mnemonic>d\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "type" "sseiadd")
> @@ -16255,25 +16153,17 @@ (define_insn "avx2_ph<plusminus_mnemonic
>
> (define_insn "ssse3_ph<plusminus_mnemonic>dv4si3"
> [(set (match_operand:V4SI 0 "register_operand" "=x,x")
> - (vec_concat:V4SI
> - (vec_concat:V2SI
> - (plusminus:SI
> - (vec_select:SI
> - (match_operand:V4SI 1 "register_operand" "0,x")
> - (parallel [(const_int 0)]))
> - (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
> - (plusminus:SI
> - (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
> - (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
> - (vec_concat:V2SI
> - (plusminus:SI
> - (vec_select:SI
> - (match_operand:V4SI 2 "vector_operand" "xBm,xm")
> - (parallel [(const_int 0)]))
> - (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
> - (plusminus:SI
> - (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
> - (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
> + (plusminus:V4SI
> + (vec_select:V4SI
> + (vec_concat:V8SI
> + (match_operand:V4SI 1 "register_operand" "0,x")
> + (match_operand:V4SI 2 "vector_operand" "xBm,xm"))
> + (parallel
> + [(const_int 0) (const_int 2) (const_int 4) (const_int 6)]))
> + (vec_select:V4SI
> + (vec_concat:V8SI (match_dup 1) (match_dup 2))
> + (parallel
> + [(const_int 1) (const_int 3) (const_int 5) (const_int 7)]))))]
> "TARGET_SSSE3"
> "@
> ph<plusminus_mnemonic>d\t{%2, %0|%0, %2}
> @@ -16288,17 +16178,15 @@ (define_insn "ssse3_ph<plusminus_mnemoni
>
> (define_insn_and_split "ssse3_ph<plusminus_mnemonic>dv2si3"
> [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
> - (vec_concat:V2SI
> - (plusminus:SI
> - (vec_select:SI
> + (plusminus:V2SI
> + (vec_select:V2SI
> + (vec_concat:V4SI
> (match_operand:V2SI 1 "register_operand" "0,0,Yv")
> - (parallel [(const_int 0)]))
> - (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
> - (plusminus:SI
> - (vec_select:SI
> - (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv")
> - (parallel [(const_int 0)]))
> - (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
> + (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv"))
> + (parallel [(const_int 0) (const_int 2)]))
> + (vec_select:V2SI
> + (vec_concat:V4SI (match_dup 1) (match_dup 2))
> + (parallel [(const_int 1) (const_int 3)]))))]
> "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
> "@
> ph<plusminus_mnemonic>d\t{%2, %0|%0, %2}
>
> Jakub
>
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2020-04-04 22:03 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-03 22:41 [PATCH] i386: Simplify {,v}ph{add,sub{,s}{w,d} insn patterns [PR94460] Jakub Jelinek
2020-04-04 22:03 ` [PATCH] i386: Simplify {, v}ph{add, sub{, s}{w, d} " Uros Bizjak
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