[PATCH] PowerPC -mcpu=future tests, Introduction

[PATCH] PowerPC -mcpu=future tests, Introduction

[Michael Meissner]

This patch will allow me to group the 7 patches I have for GCC 10 to test the
various -mcpu=future features.

There are 7 patches in this patch set:

Patch #1: Add target support for -mpcrel and -mprefixed.

Patch #2: Test that PLI/PADDI is generated to load or add large constants.

Patch #3: Add a test to make sure a prefixed load/store is generated in the
case where an offset is invalid for a DS/DQ memory instruction.

Patch #4: Add a test to make sure we do not generate the invalid prefixed
load/store instruction with update.

Patch #5: Add tests to insure prefixed loads or stores are generated when the
offset is a numeric value larger than 16 bits.

Patch #6: Add tests to insure that the PC-relative instructions are generated
to access static data items.

Patch #7: Add a test to check that we generate appropriate code when stack
checking is on and we have a large stack frame.

Versions of all of these patches have been submitted before, but some of them
neeed the -mpcrel support to be enabled before the test would succeed.  All of
these patches run on a little endian power8 computer running Linux.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

Re: [PATCH] PowerPC -mcpu=future Patch 1 of 7, add target supports for -mpcrel and -mprefixed

[Michael Meissner]

This patch adds supports in target-supports.exp for -mpcrel and -mprefixed.

Patch #1 of 7.

2020-04-27  Michael Meissner  <meissner@linux.ibm.com>

	* lib/target-supports.exp (check_effective_target_powerpc_pcrel):
	New target for PowerPC -mcpu=future support.
	(check_effective_target_powerpc_prefixed_addr): New target for
	PowerPC -mcpu=future support.

This patch is needed by some of the following patches.

--- /tmp/ulXyBK_target-supports.exp	2020-04-27 13:45:24.507304508 -0400
+++ gcc/testsuite/lib/target-supports.exp	2020-04-27 13:45:10.164498029 -0400
@@ -2189,6 +2189,23 @@ proc check_p9modulo_hw_available { } {
     }]
 }
 
+# Return 1 if the target generates PC-relative instructions automatically
+proc check_effective_target_powerpc_pcrel { } {
+    return [check_no_messages_and_pattern powerpc_pcrel \
+	{\mpld\M.*[@]pcrel} assembly {
+	    static long s;
+	    long *p = &s;
+	    long foo (void) { return s; }
+	} {-O2 -mcpu=future}]
+}
+
+# Return 1 if the target generates prefixed instructions automatically
+proc check_effective_target_powerpc_prefixed_addr { } {
+    return [check_no_messages_and_pattern powerpc_prefixed_addr \
+	{\mpld\M} assembly {
+	    long foo (long *p) { return p[0x12345]; }
+	} {-O2 -mcpu=future}]
+}
 
 # Return 1 if the target supports executing FUTURE instructions, 0 otherwise.
 # Cache the result.  It is assumed that if a simulator does not support the

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] PowerPC -mcpu=future Patch 2 of 7, Add PLI/PADDI tests

[Michael Meissner]

Add tests for generating PLI/PADDI with -mcpu=future.

This is patch #2 of 7.  This patch was run on a little endian power8 system
running Linux and the patches succeeded.

2020-04-27  Michael Meissner  <meissner@linux.ibm.com>

	* gcc.target/powerpc/prefix-add.c: New test for -mcpu=future
	generating PADDI for large constant adds.
	* gcc.target/powerpc/prefix-di-constant.c: New test for
	-mcpu=future generating PLI to load up large DImode constants.
	* gcc.target/powerpc/prefix-si-constant.c: New test for
	-mcpu=future generating PLI to load up large SImode constants.

--- /tmp/V53gPm_prefix-add.c	2020-04-27 13:51:49.231124761 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-add.c	2020-04-27 13:51:38.392270487 -0400
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Test that PADDI is generated to add a large constant.  */
+unsigned long
+add (unsigned long a)
+{
+  return a + 0x12345678UL;
+}
+
+/* { dg-final { scan-assembler {\mpaddi\M} } } */
--- /tmp/5x1erh_prefix-di-constant.c	2020-04-27 13:51:49.239124653 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-di-constant.c	2020-04-27 13:51:38.396270434 -0400
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Test that PLI (PADDI) is generated to load a large constant.  */
+unsigned long
+large (void)
+{
+  return 0x12345678UL;
+}
+
+/* { dg-final { scan-assembler {\mpli\M} } } */
--- /tmp/NGLE4b_prefix-si-constant.c	2020-04-27 13:51:49.246124559 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-si-constant.c	2020-04-27 13:51:38.400270380 -0400
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Test that PLI (PADDI) is generated to load a large constant for SImode.  */
+void
+large_si (unsigned int *p)
+{
+  *p = 0x12345U;
+}
+
+/* { dg-final { scan-assembler {\mpli\M} } } */

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] PowerPC -mcpu=future Patch 3 of 7, Add test for generating prefixed load/store

[Michael Meissner]

This patch adds a test that verifies that the compiler generates a prefixed
load/store instruction where the compiler cannot generate the instruction
directly because the offset is not a valid DS or DQ offset.  A DS offset must
have the bottom 2 bits clear.  A DQ offset must have the bottom 4 bits clear.
Due to the way PowerPC instructions are encoded, some instructions use the DS
format and some use the DQ format.

This is patch #3 of 7.  The tests in this patch run on a little endian power8
system running Linux.

2020-04-27  Michael Meissner  <meissner@linux.ibm.com>

	* gcc.target/powerpc/prefix-ds-dq.c: New test to verify that we
	generate the prefix load/store instructions for traditional
	instructions with an offset that doesn't match DS/DQ
	requirements.

--- /tmp/dtFbYL_prefix-ds-dq.c	2020-04-27 13:54:38.350850944 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-ds-dq.c	2020-04-27 13:54:15.301160847 -0400
@@ -0,0 +1,156 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests whether we generate a prefixed load/store operation for addresses that
+   don't meet DS/DQ offset constraints.  */
+
+unsigned long
+load_uc_offset1 (unsigned char *p)
+{
+  return p[1];				/* should generate LBZ.  */
+}
+
+long
+load_sc_offset1 (signed char *p)
+{
+  return p[1];				/* should generate LBZ + EXTSB.  */
+}
+
+unsigned long
+load_us_offset1 (unsigned char *p)
+{
+  return *(unsigned short *)(p + 1);	/* should generate LHZ.  */
+}
+
+long
+load_ss_offset1 (unsigned char *p)
+{
+  return *(short *)(p + 1);		/* should generate LHA.  */
+}
+
+unsigned long
+load_ui_offset1 (unsigned char *p)
+{
+  return *(unsigned int *)(p + 1);	/* should generate LWZ.  */
+}
+
+long
+load_si_offset1 (unsigned char *p)
+{
+  return *(int *)(p + 1);		/* should generate PLWA.  */
+}
+
+unsigned long
+load_ul_offset1 (unsigned char *p)
+{
+  return *(unsigned long *)(p + 1);	/* should generate PLD.  */
+}
+
+long
+load_sl_offset1 (unsigned char *p)
+{
+  return *(long *)(p + 1);		/* should generate PLD.  */
+}
+
+float
+load_float_offset1 (unsigned char *p)
+{
+  return *(float *)(p + 1);		/* should generate LFS.  */
+}
+
+double
+load_double_offset1 (unsigned char *p)
+{
+  return *(double *)(p + 1);		/* should generate LFD.  */
+}
+
+__float128
+load_float128_offset1 (unsigned char *p)
+{
+  return *(__float128 *)(p + 1);	/* should generate PLXV.  */
+}
+
+void
+store_uc_offset1 (unsigned char uc, unsigned char *p)
+{
+  p[1] = uc;				/* should generate STB.  */
+}
+
+void
+store_sc_offset1 (signed char sc, signed char *p)
+{
+  p[1] = sc;				/* should generate STB.  */
+}
+
+void
+store_us_offset1 (unsigned short us, unsigned char *p)
+{
+  *(unsigned short *)(p + 1) = us;	/* should generate STH.  */
+}
+
+void
+store_ss_offset1 (signed short ss, unsigned char *p)
+{
+  *(signed short *)(p + 1) = ss;	/* should generate STH.  */
+}
+
+void
+store_ui_offset1 (unsigned int ui, unsigned char *p)
+{
+  *(unsigned int *)(p + 1) = ui;	/* should generate STW.  */
+}
+
+void
+store_si_offset1 (signed int si, unsigned char *p)
+{
+  *(signed int *)(p + 1) = si;		/* should generate STW.  */
+}
+
+void
+store_ul_offset1 (unsigned long ul, unsigned char *p)
+{
+  *(unsigned long *)(p + 1) = ul;	/* should generate PSTD.  */
+}
+
+void
+store_sl_offset1 (signed long sl, unsigned char *p)
+{
+  *(signed long *)(p + 1) = sl;		/* should generate PSTD.  */
+}
+
+void
+store_float_offset1 (float f, unsigned char *p)
+{
+  *(float *)(p + 1) = f;		/* should generate STF.  */
+}
+
+void
+store_double_offset1 (double d, unsigned char *p)
+{
+  *(double *)(p + 1) = d;		/* should generate STD.  */
+}
+
+void
+store_float128_offset1 (__float128 f128, unsigned char *p)
+{
+  *(__float128 *)(p + 1) = f128;	/* should generate PSTXV.  */
+}
+
+/* { dg-final { scan-assembler-times {\mextsb\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlbz\M}   2 } } */
+/* { dg-final { scan-assembler-times {\mlfd\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mlfs\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mlha\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mlhz\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mlwz\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mpld\M}   2 } } */
+/* { dg-final { scan-assembler-times {\mplwa\M}  1 } } */
+/* { dg-final { scan-assembler-times {\mplxv\M}  1 } } */
+/* { dg-final { scan-assembler-times {\mpstd\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstxv\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstb\M}   2 } } */
+/* { dg-final { scan-assembler-times {\mstfd\M}  1 } } */
+/* { dg-final { scan-assembler-times {\mstfs\M}  1 } } */
+/* { dg-final { scan-assembler-times {\msth\M}   2 } } */
+/* { dg-final { scan-assembler-times {\mstw\M}   2 } } */

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] PowerPC -mcpu=future Patch 4 of 7, Make sure an invalid instruction is not generated

[Michael Meissner]

This test validates that the compiler does not generate a prefixed load/store
instruction with an update form.  The prefixed load/store instructions do not
have an update form.

This is patch #4 of 7.  This patch was run on a little endian power8 system
running Linux, and the tests passed.  Can I check this into the trunk?

2020-04-27  Michael Meissner  <meissner@linux.ibm.com>

	* gcc.target/powerpc/prefix-no-premodify.c: Make sure we do not
	generate the non-existent PLWZU instruction if -mcpu=future.

--- /tmp/zijQUT_prefix-no-premodify.c	2020-04-27 14:01:44.465121833 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-no-premodify.c	2020-04-27 14:01:44.288124213 -0400
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Make sure that we don't generate a prefixed form of the load and store with
+   update instructions (i.e. instead of generating LWZU we have to generate
+   PLWZ plus a PADDI).  */
+
+#ifndef SIZE
+#define SIZE 50000
+#endif
+
+struct foo {
+  unsigned int field;
+  char pad[SIZE];
+};
+
+struct foo *inc_load (struct foo *p, unsigned int *q)
+{
+  *q = (++p)->field;	/* PLWZ, PADDI, STW.  */
+  return p;
+}
+
+struct foo *dec_load (struct foo *p, unsigned int *q)
+{
+  *q = (--p)->field;	/* PLWZ, PADDI, STW.  */
+  return p;
+}
+
+struct foo *inc_store (struct foo *p, unsigned int *q)
+{
+  (++p)->field = *q;	/* LWZ, PADDI, PSTW.  */
+  return p;
+}
+
+struct foo *dec_store (struct foo *p, unsigned int *q)
+{
+  (--p)->field = *q;	/* LWZ, PADDI, PSTW.  */
+  return p;
+}
+
+/* { dg-final { scan-assembler-times {\mlwz\M}    2 } } */
+/* { dg-final { scan-assembler-times {\mstw\M}    2 } } */
+/* { dg-final { scan-assembler-times {\mpaddi\M}  4 } } */
+/* { dg-final { scan-assembler-times {\mplwz\M}   2 } } */
+/* { dg-final { scan-assembler-times {\mpstw\M}   2 } } */
+/* { dg-final { scan-assembler-not   {\mplwzu\M}    } } */
+/* { dg-final { scan-assembler-not   {\mpstwu\M}    } } */
+/* { dg-final { scan-assembler-not   {\maddis\M}    } } */
+/* { dg-final { scan-assembler-not   {\maddi\M}     } } */

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] PowerPC -mcpu=future Patch 5 of 7, Add prefixed load/store tests with large numeric offsets

[Michael Meissner]

This patch adds tests for -mcpu=future generating prefixed load/store
instructions with large numeric offsets.

This is patch #5 of 7.  This patch was tested on a little endian power8 system
running Linux, and the tests passed.  Can I check this into GCC 10?

2020-04-27  Michael Meissner  <meissner@linux.ibm.com>

	* gcc.target/powerpc/prefix-large.h: New set of tests to test
	prefixed addressing on 'future' system with large numeric offsets
	for various types.
	* gcc.target/powerpc/prefix-large-dd.c: New test for prefixed
	loads/stores with large offsets for the _Decimal64 type.
	* gcc.target/powerpc/prefix-large-df.c: New test for prefixed
	loads/stores with large offsets for the double type.
	* gcc.target/powerpc/prefix-large-di.c: New test for prefixed
	loads/stores with large offsets for the long type.
	* gcc.target/powerpc/prefix-large-hi.c: New test for prefixed
	loads/stores with large offsets for the short type.
	* gcc.target/powerpc/prefix-large-kf.c: New test for prefixed
	loads/stores with large offsets for the __float128 type.
	* gcc.target/powerpc/prefix-large-qi.c: New test for prefixed
	loads/stores with large offsets for the signed char type.
	* gcc.target/powerpc/prefix-large-sd.c: New test for prefixed
	loads/stores with large offsets for the _Decimal32 type.
	* gcc.target/powerpc/prefix-large-sf.c: New test for prefixed
	loads/stores with large offsets for the float type.
	* gcc.target/powerpc/prefix-large-si.c: New test for prefixed
	loads/stores with large offsets for the int type.
	* gcc.target/powerpc/prefix-large-udi.c: New test for prefixed
	loads/stores with large offsets for the unsigned long type.
	* gcc.target/powerpc/prefix-large-uhi.c: New test for prefixed
	loads/stores with large offsets for the unsigned short type.
	* gcc.target/powerpc/prefix-large-uqi.c: New test for prefixed
	loads/stores with large offsets for the unsigned char type.
	* gcc.target/powerpc/prefix-large-usi.c: New test for prefixed
	loads/stores with large offsets for the unsigned int type.
	* gcc.target/powerpc/prefix-large-v2df.c: New test for prefixed
	loads/stores with large offsets for the vector double type.

--- /tmp/ky2ZAZ_prefix-large-dd.c	2020-04-27 14:05:05.638417056 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-dd.c	2020-04-27 14:05:05.406420175 -0400
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for _Decimal64 objects.  */
+
+#define TYPE _Decimal64
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplfd\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstfd\M} 2 } } */
--- /tmp/HDrUG4_prefix-large-df.c	2020-04-27 14:05:05.647416935 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-df.c	2020-04-27 14:05:05.411420108 -0400
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for double objects.  */
+
+#define TYPE double
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplfd\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstfd\M} 2 } } */
--- /tmp/eqa8N9_prefix-large-di.c	2020-04-27 14:05:05.654416841 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-di.c	2020-04-27 14:05:05.415420054 -0400
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for long objects.  */
+
+#define TYPE long
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mpld\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstd\M} 2 } } */
--- /tmp/jLewWe_prefix-large-hi.c	2020-04-27 14:05:05.660416760 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-hi.c	2020-04-27 14:05:05.419420000 -0400
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for short objects.  */
+
+#define TYPE short
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplh[az]\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpsth\M}     2 } } */
--- /tmp/ea0a6j_prefix-large-kf.c	2020-04-27 14:05:05.666416679 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-kf.c	2020-04-27 14:05:05.423419946 -0400
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for __float128 objects.  */
+
+#define TYPE __float128
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplxv\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstxv\M} 2 } } */
--- /tmp/7Ko4gp_prefix-large-qi.c	2020-04-27 14:05:05.673416585 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-qi.c	2020-04-27 14:05:05.426419906 -0400
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for signed char objects.  */
+
+#define TYPE signed char
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplbz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstb\M}  2 } } */
--- /tmp/Tl8etu_prefix-large-sd.c	2020-04-27 14:05:05.680416491 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-sd.c	2020-04-27 14:05:05.430419852 -0400
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for _Decimal32 objects.  */
+
+#define TYPE _Decimal32
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mpaddi\M|\mpli|\mpla\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mlfiwzx\M}              2 } } */
+/* { dg-final { scan-assembler-times {\mstfiwx\M}              2 } } */
+
+
--- /tmp/KbsIGz_prefix-large-sf.c	2020-04-27 14:05:05.687416397 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-sf.c	2020-04-27 14:05:05.434419799 -0400
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for float objects.  */
+
+#define TYPE float
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplfs\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstfs\M} 2 } } */
--- /tmp/AsuuVE_prefix-large-si.c	2020-04-27 14:05:05.693416315 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-si.c	2020-04-27 14:05:05.438419745 -0400
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for int objects.  */
+
+#define TYPE int
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplw[az]\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstw\M}     2 } } */
--- /tmp/RO8CbK_prefix-large-udi.c	2020-04-27 14:05:05.701416205 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-udi.c	2020-04-27 14:05:05.441419704 -0400
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for unsigned long
+   objects.  */
+
+#define TYPE unsigned long
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mpld\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstd\M} 2 } } */
--- /tmp/2Dy8sP_prefix-large-uhi.c	2020-04-27 14:05:05.708416109 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-uhi.c	2020-04-27 14:05:05.445419651 -0400
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for unsigned short
+   objects.  */
+
+#define TYPE unsigned short
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplhz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpsth\M}  2 } } */
--- /tmp/XKp5LU_prefix-large-uqi.c	2020-04-27 14:05:05.716416000 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-uqi.c	2020-04-27 14:05:05.449419597 -0400
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for unsigned char
+   objects.  */
+
+#define TYPE unsigned char
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplbz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstb\M}  2 } } */
--- /tmp/XSeo6Z_prefix-large-usi.c	2020-04-27 14:05:05.723415904 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-usi.c	2020-04-27 14:05:05.453419543 -0400
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for unsigned int
+   objects.  */
+
+#define TYPE unsigned int
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplwz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstw\M}  2 } } */
--- /tmp/skm5r5_prefix-large-v2df.c	2020-04-27 14:05:05.730415808 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-v2df.c	2020-04-27 14:05:05.457419489 -0400
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for vector objects.  */
+
+#define TYPE vector double
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplxv\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstxv\M} 2 } } */
--- /tmp/1H98Oa_prefix-large.h	2020-04-27 14:05:05.737415712 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-large.h	2020-04-27 14:05:05.461419436 -0400
@@ -0,0 +1,59 @@
+/* Common tests for prefixed instructions testing whether we can generate a
+   34-bit offset using 1 instruction.  */
+
+typedef signed char	schar;
+typedef unsigned char	uchar;
+typedef unsigned short	ushort;
+typedef unsigned int	uint;
+typedef unsigned long	ulong;
+typedef long double	ldouble;
+typedef vector double	v2df;
+typedef vector long	v2di;
+typedef vector float	v4sf;
+typedef vector int	v4si;
+
+#ifndef TYPE
+#define TYPE ulong
+#endif
+
+#ifndef ITYPE
+#define ITYPE TYPE
+#endif
+
+#ifndef OTYPE
+#define OTYPE TYPE
+#endif
+
+#if !defined(DO_ADD) && !defined(DO_VALUE) && !defined(DO_SET)
+#define DO_ADD		1
+#define DO_VALUE	1
+#define DO_SET		1
+#endif
+
+#ifndef CONSTANT
+#define CONSTANT	0x123450UL
+#endif
+
+#if DO_ADD
+void
+add (TYPE *p, TYPE a)
+{
+  p[CONSTANT] += a;
+}
+#endif
+
+#if DO_VALUE
+OTYPE
+value (TYPE *p)
+{
+  return p[CONSTANT];
+}
+#endif
+
+#if DO_SET
+void
+set (TYPE *p, ITYPE a)
+{
+  p[CONSTANT] = a;
+}
+#endif

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] PowerPC -mcpu=future Patch 6 of 7, add PC-relative tests

[Michael Meissner]

This patch adds PC-relative tests for -mcpu=future.

This is patch #6 of 7.  I have checked this on a little endian power8 system
running Linux, and all tests passed.  Can I check this into the GCC 10 trunk?

2020-04-27  Michael Meissner  <meissner@linux.ibm.com>

	* gcc.target/powerpc/prefix-pcrel.h: New set of tests to test
	prefixed addressing on 'future' system with PC-relative addresses
	for various types.
	* gcc.target/powerpc/prefix-pcrel-dd.c: New test for prefixed
	loads/stores with PC-relative addresses for the _Decimal64 type.
	* gcc.target/powerpc/prefix-pcrel-df.c: New test for prefixed
	loads/stores with PC-relative addresses for the double type.
	* gcc.target/powerpc/prefix-pcrel-di.c: New test for prefixed
	loads/stores with PC-relative addresses for the long type.
	* gcc.target/powerpc/prefix-pcrel-hi.c: New test for prefixed
	loads/stores with PC-relative addresses for the short type.
	* gcc.target/powerpc/prefix-pcrel-kf.c: New test for prefixed
	loads/stores with PC-relative addresses for the __float128 type.
	* gcc.target/powerpc/prefix-pcrel-qi.c: New test for prefixed
	loads/stores with PC-relative addresses for the signed char type.
	* gcc.target/powerpc/prefix-pcrel-sd.c: New test for prefixed
	loads/stores with PC-relative addresses for the _Decimal32 type.
	* gcc.target/powerpc/prefix-pcrel-sf.c: New test for prefixed
	loads/stores with PC-relative addresses for the float type.
	* gcc.target/powerpc/prefix-pcrel-si.c: New test for prefixed
	loads/stores with PC-relative addresses for the int type.
	* gcc.target/powerpc/prefix-pcrel-udi.c: New test for prefixed
	loads/stores with PC-relative addresses for the unsigned long
	type.
	* gcc.target/powerpc/prefix-pcrel-uhi.c: New test for prefixed
	loads/stores with PC-relative addresses for the unsigned short
	type.
	* gcc.target/powerpc/prefix-pcrel-uqi.c: New test for prefixed
	loads/stores with PC-relative addresses for the unsigned char
	type.
	* gcc.target/powerpc/prefix-pcrel-usi.c: New test for prefixed
	loads/stores with PC-relative addresses for the unsigned int
	type.
	* gcc.target/powerpc/prefix-pcrel-v2df.c: New test for prefixed
	loads/stores with PC-relative addresses for the vector double
	type.

--- /tmp/61oqzU_prefix-pcrel-dd.c	2020-04-27 14:11:22.981249397 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-dd.c	2020-04-27 14:11:22.751252547 -0400
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the _Decimal64 type.  */
+
+#define TYPE _Decimal64
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  4 } } */
+/* { dg-final { scan-assembler-times {\mplfd\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstfd\M} 2 } } */
--- /tmp/w5tyiy_prefix-pcrel-df.c	2020-04-27 14:11:22.990249274 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-df.c	2020-04-27 14:11:22.755252492 -0400
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the double type.  */
+
+#define TYPE double
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  4 } } */
+/* { dg-final { scan-assembler-times {\mplfd\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstfd\M} 2 } } */
--- /tmp/uE672b_prefix-pcrel-di.c	2020-04-27 14:11:22.998249164 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-di.c	2020-04-27 14:11:22.759252437 -0400
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the long type.  */
+
+#define TYPE long
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel} 4 } } */
+/* { dg-final { scan-assembler-times {\mpld\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstd\M} 2 } } */
--- /tmp/UHt8OP_prefix-pcrel-hi.c	2020-04-27 14:11:23.005249069 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-hi.c	2020-04-27 14:11:22.763252383 -0400
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the short type.  */
+
+#define TYPE short
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}     4 } } */
+/* { dg-final { scan-assembler-times {\mplh[az]\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpsth\M}     2 } } */
--- /tmp/046sCt_prefix-pcrel-kf.c	2020-04-27 14:11:23.012248973 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-kf.c	2020-04-27 14:11:22.767252328 -0400
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the __float128 type.  */
+
+#define TYPE __float128
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  4 } } */
+/* { dg-final { scan-assembler-times {\mplxv\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstxv\M} 2 } } */
--- /tmp/gZkfr7_prefix-pcrel-qi.c	2020-04-27 14:11:23.020248863 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-qi.c	2020-04-27 14:11:22.771252273 -0400
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the signed char type.  */
+
+#define TYPE signed char
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  4 } } */
+/* { dg-final { scan-assembler-times {\mplbz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstb\M}  2 } } */
--- /tmp/KUJshL_prefix-pcrel-sd.c	2020-04-27 14:11:23.028248754 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-sd.c	2020-04-27 14:11:22.774252232 -0400
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the _Decimal32 type.  Note, the _Decimal32
+   type will not generate any prefixed load or stores, because there is no
+   prefixed load/store instruction to load up a vector register as a zero
+   extended 32-bit integer.  So we count the number load addresses that are
+   generated.  */
+
+#define TYPE _Decimal32
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel} 3 } } */
+/* { dg-final { scan-assembler-times {\mpla\M}  3 } } */
--- /tmp/eMi78o_prefix-pcrel-sf.c	2020-04-27 14:11:23.035248658 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-sf.c	2020-04-27 14:11:22.778252177 -0400
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the float type.  */
+
+#define TYPE float
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  4 } } */
+/* { dg-final { scan-assembler-times {\mplfs\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstfs\M} 2 } } */
--- /tmp/jUBb22_prefix-pcrel-si.c	2020-04-27 14:11:23.043248548 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-si.c	2020-04-27 14:11:22.781252136 -0400
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the int type.  */
+
+#define TYPE int
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}     4 } } */
+/* { dg-final { scan-assembler-times {\mplw[az]\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstw\M}     2 } } */
--- /tmp/p0CEWG_prefix-pcrel-udi.c	2020-04-27 14:11:23.050248452 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-udi.c	2020-04-27 14:11:22.784252095 -0400
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for unsigned long type.  */
+
+#define TYPE unsigned long
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel} 4 } } */
+/* { dg-final { scan-assembler-times {\mpld\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstd\M} 2 } } */
--- /tmp/dWjwSk_prefix-pcrel-uhi.c	2020-04-27 14:11:23.058248343 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-uhi.c	2020-04-27 14:11:22.788252040 -0400
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the unsigned short type.  */
+
+#define TYPE unsigned short
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  4 } } */
+/* { dg-final { scan-assembler-times {\mplhz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpsth\M}  2 } } */
--- /tmp/xu5KPY_prefix-pcrel-uqi.c	2020-04-27 14:11:23.065248247 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-uqi.c	2020-04-27 14:11:22.792251985 -0400
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the unsigned char type.  */
+
+#define TYPE unsigned char
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  4 } } */
+/* { dg-final { scan-assembler-times {\mplbz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstb\M}  2 } } */
--- /tmp/PlTpOC_prefix-pcrel-usi.c	2020-04-27 14:11:23.072248151 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-usi.c	2020-04-27 14:11:22.796251931 -0400
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for unsigned int type.  */
+
+#define TYPE unsigned int
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  4 } } */
+/* { dg-final { scan-assembler-times {\mplwz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstw\M}  2 } } */
--- /tmp/2P3sOg_prefix-pcrel-v2df.c	2020-04-27 14:11:23.080248042 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-v2df.c	2020-04-27 14:11:22.800251876 -0400
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the vector double type.  */
+
+#define TYPE vector double
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  4 } } */
+/* { dg-final { scan-assembler-times {\mplxv\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstxv\M} 2 } } */
--- /tmp/mOOQPU_prefix-pcrel.h	2020-04-27 14:11:23.087247946 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel.h	2020-04-27 14:11:22.803251835 -0400
@@ -0,0 +1,58 @@
+/* Common tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for each type.  */
+
+typedef signed char	schar;
+typedef unsigned char	uchar;
+typedef unsigned short	ushort;
+typedef unsigned int	uint;
+typedef unsigned long	ulong;
+typedef long double	ldouble;
+typedef vector double	v2df;
+typedef vector long	v2di;
+typedef vector float	v4sf;
+typedef vector int	v4si;
+
+#ifndef TYPE
+#define TYPE ulong
+#endif
+
+#ifndef ITYPE
+#define ITYPE TYPE
+#endif
+
+#ifndef OTYPE
+#define OTYPE TYPE
+#endif
+
+static TYPE a;
+TYPE *p = &a;
+
+#if !defined(DO_ADD) && !defined(DO_VALUE) && !defined(DO_SET)
+#define DO_ADD		1
+#define DO_VALUE	1
+#define DO_SET		1
+#endif
+
+#if DO_ADD
+void
+add (TYPE b)
+{
+  a += b;
+}
+#endif
+
+#if DO_VALUE
+OTYPE
+value (void)
+{
+  return (OTYPE)a;
+}
+#endif
+
+#if DO_SET
+void
+set (ITYPE b)
+{
+  a = (TYPE)b;
+}
+#endif

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] PowerPC -mcpu=future Patch 7 of 7, Add test for stack checking and large stack frames

[Michael Meissner]

This patch adds a test for the case where we have prefixed load/store
instructions, a large stack frame, and stack checking is enabled.

This is patch #7 of 7.  I have checked this patch on a little endian power8
system running Linux, and the test passed.  Can I check this into the GCC 10
trunk?

2020-04-27  Michael Meissner  <meissner@linux.ibm.com>

	* gcc.target/powerpc/prefix-stack-protect.c: New test to make sure
	-fstack-protect-strong works with prefixed addressing.

--- /tmp/OxuBEg_prefix-stack-protect.c	2020-04-27 14:12:53.883004507 -0400
+++ gcc/testsuite/gcc.target/powerpc/prefix-stack-protect.c	2020-04-27 14:12:53.706006931 -0400
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future -fstack-protector-strong" } */
+
+/* Test that we can handle large stack frames with -fstack-protector-strong and
+   prefixed addressing.  This was originally discovered in trying to build
+   glibc with -mcpu=future, and vfwprintf.c failed because it used
+   -fstack-protector-strong.  */
+
+extern long foo (char *);
+
+long
+bar (void)
+{
+  char buffer[0x20000];
+  return foo (buffer) + 1;
+}
+
+/* { dg-final { scan-assembler {\mpld\M}  } } */
+/* { dg-final { scan-assembler {\mpstd\M} } } */

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

Re: [PATCH] PowerPC -mcpu=future Patch 1 of 7, add target supports for -mpcrel and -mprefixed

[will schmidt]

On Mon, 2020-04-27 at 15:46 -0400, Michael Meissner via Gcc-patches
wrote:
> This patch adds supports in target-supports.exp for -mpcrel and
> -mprefixed.
> 
> Patch #1 of 7.


Hi

Subject: Re: [PATCH] PowerPC -mcpu=future Patch 1 of 7, add target
supports for -mpcrel and -mprefixed

Squish that subject line down a bit if possible. stl

Re: [PATCH 1/7] PowerPC add target supports for -mpcrel and -mprefixed

Can include the "for -mcpu=future" blurb as part of the inline
description if so warranted.

> 
> 2020-04-27  Michael Meissner  <meissner@linux.ibm.com>
> 
> 	* lib/target-supports.exp
> (check_effective_target_powerpc_pcrel):
> 	New target for PowerPC -mcpu=future support.
> 	(check_effective_target_powerpc_prefixed_addr): New target for
> 	PowerPC -mcpu=future support.
> 
> This patch is needed by some of the following patches.
> 
> --- /tmp/ulXyBK_target-supports.exp	2020-04-27 13:45:24.507304508
> -0400
> +++ gcc/testsuite/lib/target-supports.exp	2020-04-27
> 13:45:10.164498029 -0400
> @@ -2189,6 +2189,23 @@ proc check_p9modulo_hw_available { } {
>      }]
>  }
> 
> +# Return 1 if the target generates PC-relative instructions
> automatically
> +proc check_effective_target_powerpc_pcrel { } {
> +    return [check_no_messages_and_pattern powerpc_pcrel \
> +	{\mpld\M.*[@]pcrel} assembly {
> +	    static long s;
> +	    long *p = &s;
> +	    long foo (void) { return s; }
> +	} {-O2 -mcpu=future}]
> +}
> +
> +# Return 1 if the target generates prefixed instructions
> automatically
> +proc check_effective_target_powerpc_prefixed_addr { } {
> +    return [check_no_messages_and_pattern powerpc_prefixed_addr \
> +	{\mpld\M} assembly {
> +	    long foo (long *p) { return p[0x12345]; }
> +	} {-O2 -mcpu=future}]
> +}

The syntax matches existing check_effective_target_powerpc test
stanzas.

lgtm.

thanks,
-Will

>  # Return 1 if the target supports executing FUTURE instructions, 0
> otherwise.
>  # Cache the result.  It is assumed that if a simulator does not
> support the
> 

Re: [PATCH] PowerPC -mcpu=future Patch 2 of 7, Add PLI/PADDI tests

[will schmidt]

On Mon, 2020-04-27 at 15:48 -0400, Michael Meissner via Gcc-patches
wrote:
> Add tests for generating PLI/PADDI with -mcpu=future.
> 
> This is patch #2 of 7.  This patch was run on a little endian power8
> system
> running Linux and the patches succeeded.
> 
> 2020-04-27  Michael Meissner  <meissner@linux.ibm.com>
> 
> 	* gcc.target/powerpc/prefix-add.c: New test for -mcpu=future
> 	generating PADDI for large constant adds.
> 	* gcc.target/powerpc/prefix-di-constant.c: New test for
> 	-mcpu=future generating PLI to load up large DImode constants.
> 	* gcc.target/powerpc/prefix-si-constant.c: New test for
> 	-mcpu=future generating PLI to load up large SImode constants.
> 
> --- /tmp/V53gPm_prefix-add.c	2020-04-27 13:51:49.231124761 -0400
> +++ gcc/testsuite/gcc.target/powerpc/prefix-add.c	2020-04-27 13:51:38.392270487 -0400
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target powerpc_prefixed_addr } */
> +/* { dg-options "-O2 -mdejagnu-cpu=future" } */
> +
> +/* Test that PADDI is generated to add a large constant.  */
> +unsigned long

Just 'long' or should that be 'long long' ? 

otherwise, seems straightforward.

lgtm.

thanks,
-Will



> +add (unsigned long a)
> +{
> +  return a + 0x12345678UL;
> +}
> +
> +/* { dg-final { scan-assembler {\mpaddi\M} } } */
> --- /tmp/5x1erh_prefix-di-constant.c	2020-04-27 13:51:49.239124653 -0400
> +++ gcc/testsuite/gcc.target/powerpc/prefix-di-constant.c	2020-04-27 13:51:38.396270434 -0400
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target powerpc_prefixed_addr } */
> +/* { dg-options "-O2 -mdejagnu-cpu=future" } */
> +
> +/* Test that PLI (PADDI) is generated to load a large constant.  */
> +unsigned long
> +large (void)
> +{
> +  return 0x12345678UL;
> +}
> +
> +/* { dg-final { scan-assembler {\mpli\M} } } */
> --- /tmp/NGLE4b_prefix-si-constant.c	2020-04-27 13:51:49.246124559 -0400
> +++ gcc/testsuite/gcc.target/powerpc/prefix-si-constant.c	2020-04-27 13:51:38.400270380 -0400
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target powerpc_prefixed_addr } */
> +/* { dg-options "-O2 -mdejagnu-cpu=future" } */
> +
> +/* Test that PLI (PADDI) is generated to load a large constant for SImode.  */
> +void
> +large_si (unsigned int *p)
> +{
> +  *p = 0x12345U;
> +}
> +
> +/* { dg-final { scan-assembler {\mpli\M} } } */
> 

Re: [PATCH] PowerPC -mcpu=future Patch 3 of 7, Add test for generating prefixed load/store

[will schmidt]

On Mon, 2020-04-27 at 15:53 -0400, Michael Meissner via Gcc-patches wrote:
> This patch adds a test that verifies that the compiler generates a prefixed
> load/store instruction where the compiler cannot generate the instruction
> directly because the offset is not a valid DS or DQ offset.  A DS offset must
> have the bottom 2 bits clear.  A DQ offset must have the bottom 4 bits clear.
> Due to the way PowerPC instructions are encoded, some instructions use the DS
> format and some use the DQ format.
> 
> This is patch #3 of 7.  The tests in this patch run on a little endian power8
> system running Linux.
> 
> 2020-04-27  Michael Meissner  <meissner@linux.ibm.com>
> 
> 	* gcc.target/powerpc/prefix-ds-dq.c: New test to verify that we
> 	generate the prefix load/store instructions for traditional
> 	instructions with an offset that doesn't match DS/DQ
> 	requirements.

Can probably safely be shortened to end at "... for traditional
instructions."   if not even just "New test".  



> 
> --- /tmp/dtFbYL_prefix-ds-dq.c	2020-04-27 13:54:38.350850944 -0400
> +++ gcc/testsuite/gcc.target/powerpc/prefix-ds-dq.c	2020-04-27 13:54:15.301160847 -0400
> @@ -0,0 +1,156 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target powerpc_prefixed_addr } */
> +/* { dg-options "-O2 -mdejagnu-cpu=future" } */
> +
> +/* Tests whether we generate a prefixed load/store operation for addresses that
> +   don't meet DS/DQ offset constraints.  */
> +
> +unsigned long
> +load_uc_offset1 (unsigned char *p)
> +{
> +  return p[1];				/* should generate LBZ.  */
> +}
> +
> +long
> +load_sc_offset1 (signed char *p)
> +{
> +  return p[1];				/* should generate LBZ + EXTSB.  */
> +}

OCD kicks in and says the above two (and a couple below) have an extra
tab.  nbd. :-)


> +
> +unsigned long
> +load_us_offset1 (unsigned char *p)
> +{
> +  return *(unsigned short *)(p + 1);	/* should generate LHZ.  */
> +}
> +
> +long
> +load_ss_offset1 (unsigned char *p)
> +{
> +  return *(short *)(p + 1);		/* should generate LHA.  */
> +}
> +
> +unsigned long
> +load_ui_offset1 (unsigned char *p)
> +{
> +  return *(unsigned int *)(p + 1);	/* should generate LWZ.  */
> +}
> +
> +long
> +load_si_offset1 (unsigned char *p)
> +{
> +  return *(int *)(p + 1);		/* should generate PLWA.  */
> +}
> +
> +unsigned long
> +load_ul_offset1 (unsigned char *p)
> +{
> +  return *(unsigned long *)(p + 1);	/* should generate PLD.  */
> +}
> +
> +long
> +load_sl_offset1 (unsigned char *p)
> +{
> +  return *(long *)(p + 1);		/* should generate PLD.  */
> +}
> +
> +float
> +load_float_offset1 (unsigned char *p)
> +{
> +  return *(float *)(p + 1);		/* should generate LFS.  */
> +}
> +
> +double
> +load_double_offset1 (unsigned char *p)
> +{
> +  return *(double *)(p + 1);		/* should generate LFD.  */
> +}
> +
> +__float128
> +load_float128_offset1 (unsigned char *p)
> +{
> +  return *(__float128 *)(p + 1);	/* should generate PLXV.  */
> +}
> +
> +void
> +store_uc_offset1 (unsigned char uc, unsigned char *p)
> +{
> +  p[1] = uc;				/* should generate STB.  */
> +}
> +
> +void
> +store_sc_offset1 (signed char sc, signed char *p)
> +{
> +  p[1] = sc;				/* should generate STB.  */
> +}
> +
> +void
> +store_us_offset1 (unsigned short us, unsigned char *p)
> +{
> +  *(unsigned short *)(p + 1) = us;	/* should generate STH.  */
> +}
> +
> +void
> +store_ss_offset1 (signed short ss, unsigned char *p)
> +{
> +  *(signed short *)(p + 1) = ss;	/* should generate STH.  */
> +}
> +
> +void
> +store_ui_offset1 (unsigned int ui, unsigned char *p)
> +{
> +  *(unsigned int *)(p + 1) = ui;	/* should generate STW.  */
> +}
> +
> +void
> +store_si_offset1 (signed int si, unsigned char *p)
> +{
> +  *(signed int *)(p + 1) = si;		/* should generate STW.  */
> +}
> +
> +void
> +store_ul_offset1 (unsigned long ul, unsigned char *p)
> +{
> +  *(unsigned long *)(p + 1) = ul;	/* should generate PSTD.  */
> +}
> +
> +void
> +store_sl_offset1 (signed long sl, unsigned char *p)
> +{
> +  *(signed long *)(p + 1) = sl;		/* should generate PSTD.  */
> +}
> +
> +void
> +store_float_offset1 (float f, unsigned char *p)
> +{
> +  *(float *)(p + 1) = f;		/* should generate STF.  */

Comment should be STFD ?

> +}
> +
> +void
> +store_double_offset1 (double d, unsigned char *p)
> +{
> +  *(double *)(p + 1) = d;		/* should generate STD.  */

Comment should be STFS ? 

> +}
> +
> +void
> +store_float128_offset1 (__float128 f128, unsigned char *p)
> +{
> +  *(__float128 *)(p + 1) = f128;	/* should generate PSTXV.  */
> +}
> +
> +/* { dg-final { scan-assembler-times {\mextsb\M} 1 } } */
> +/* { dg-final { scan-assembler-times {\mlbz\M}   2 } } */
> +/* { dg-final { scan-assembler-times {\mlfd\M}   1 } } */
> +/* { dg-final { scan-assembler-times {\mlfs\M}   1 } } */
> +/* { dg-final { scan-assembler-times {\mlha\M}   1 } } */
> +/* { dg-final { scan-assembler-times {\mlhz\M}   1 } } */
> +/* { dg-final { scan-assembler-times {\mlwz\M}   1 } } */
> +/* { dg-final { scan-assembler-times {\mpld\M}   2 } } */
> +/* { dg-final { scan-assembler-times {\mplwa\M}  1 } } */
> +/* { dg-final { scan-assembler-times {\mplxv\M}  1 } } */
> +/* { dg-final { scan-assembler-times {\mpstd\M}  2 } } */
> +/* { dg-final { scan-assembler-times {\mpstxv\M} 1 } } */
> +/* { dg-final { scan-assembler-times {\mstb\M}   2 } } */

> +/* { dg-final { scan-assembler-times {\mstfd\M}  1 } } */
> +/* { dg-final { scan-assembler-times {\mstfs\M}  1 } } */

I wasn't able to matche these two up with the comments above.
(see above).

beyond those nits, 
lgtm.
thanks, 
-Will


> +/* { dg-final { scan-assembler-times {\msth\M}   2 } } */
> +/* { dg-final { scan-assembler-times {\mstw\M}   2 } } */
> 

Re: [PATCH] PowerPC -mcpu=future Patch 4 of 7, Make sure an invalid instruction is not generated

[will schmidt]

On Mon, 2020-04-27 at 15:57 -0400, Michael Meissner via Gcc-patches
wrote:
> This test validates that the compiler does not generate a prefixed
> load/store
> instruction with an update form.  The prefixed load/store
> instructions do not
> have an update form.
> 
> This is patch #4 of 7.  This patch was run on a little endian power8
> system
> running Linux, and the tests passed.  Can I check this into the
> trunk?

Hi,


> 2020-04-27  Michael Meissner  <meissner@linux.ibm.com>
> 
> 	* gcc.target/powerpc/prefix-no-premodify.c: Make sure we do not
> 	generate the non-existent PLWZU instruction if -mcpu=future.

Should "premodify" instead be "no-update" or "no-update-forms" ?   I
don't immediately see why "modify" is referenced.


> 
> --- /tmp/zijQUT_prefix-no-premodify.c	2020-04-27 14:01:44.465121833
> -0400
> +++ gcc/testsuite/gcc.target/powerpc/prefix-no-premodify.c	2020-
> 04-27 14:01:44.288124213 -0400
> @@ -0,0 +1,50 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target powerpc_prefixed_addr } */
> +/* { dg-options "-O2 -mdejagnu-cpu=future" } */
> +
> +/* Make sure that we don't generate a prefixed form of the load and
> store with
> +   update instructions (i.e. instead of generating LWZU we have to
> generate
> +   PLWZ plus a PADDI).  */
> +
> +#ifndef SIZE
> +#define SIZE 50000
> +#endif
> +
> +struct foo {
> +  unsigned int field;
> +  char pad[SIZE];
> +};
> +
> +struct foo *inc_load (struct foo *p, unsigned int *q)
> +{
> +  *q = (++p)->field;	/* PLWZ, PADDI, STW.  */
> +  return p;
> +}
> +
> +struct foo *dec_load (struct foo *p, unsigned int *q)
> +{
> +  *q = (--p)->field;	/* PLWZ, PADDI, STW.  */
> +  return p;
> +}
> +
> +struct foo *inc_store (struct foo *p, unsigned int *q)
> +{
> +  (++p)->field = *q;	/* LWZ, PADDI, PSTW.  */
> +  return p;
> +}
> +
> +struct foo *dec_store (struct foo *p, unsigned int *q)
> +{
> +  (--p)->field = *q;	/* LWZ, PADDI, PSTW.  */
> +  return p;
> +}
> +
> +/* { dg-final { scan-assembler-times {\mlwz\M}    2 } } */
> +/* { dg-final { scan-assembler-times {\mstw\M}    2 } } */
> +/* { dg-final { scan-assembler-times {\mpaddi\M}  4 } } */
> +/* { dg-final { scan-assembler-times {\mplwz\M}   2 } } */
> +/* { dg-final { scan-assembler-times {\mpstw\M}   2 } } */

Numbers line up with comments above.

> +/* { dg-final { scan-assembler-not   {\mplwzu\M}    } } */
> +/* { dg-final { scan-assembler-not   {\mpstwu\M}    } } */
> +/* { dg-final { scan-assembler-not   {\maddis\M}    } } */
> +/* { dg-final { scan-assembler-not   {\maddi\M}     } } */

Ok.

lgtm.
thanks,
-Will



> 

Re: [PATCH] PowerPC -mcpu=future Patch 5 of 7, Add prefixed load/store tests with large numeric offsets

[will schmidt]

On Mon, 2020-04-27 at 16:00 -0400, Michael Meissner via Gcc-patches
wrote:
> This patch adds tests for -mcpu=future generating prefixed load/store
> instructions with large numeric offsets.
> 
> This is patch #5 of 7.  This patch was tested on a little endian power8 system
> running Linux, and the tests passed.  Can I check this into GCC 10?
> 
> 2020-04-27  Michael Meissner  <meissner@linux.ibm.com>
> 
> 	* gcc.target/powerpc/prefix-large.h: New set of tests to test
> 	prefixed addressing on 'future' system with large numeric offsets
> 	for various types.
> 	* gcc.target/powerpc/prefix-large-dd.c: New test for prefixed
> 	loads/stores with large offsets for the _Decimal64 type.
> 	* gcc.target/powerpc/prefix-large-df.c: New test for prefixed
> 	loads/stores with large offsets for the double type.
> 	* gcc.target/powerpc/prefix-large-di.c: New test for prefixed
> 	loads/stores with large offsets for the long type.
> 	* gcc.target/powerpc/prefix-large-hi.c: New test for prefixed
> 	loads/stores with large offsets for the short type.
> 	* gcc.target/powerpc/prefix-large-kf.c: New test for prefixed
> 	loads/stores with large offsets for the __float128 type.
> 	* gcc.target/powerpc/prefix-large-qi.c: New test for prefixed
> 	loads/stores with large offsets for the signed char type.
> 	* gcc.target/powerpc/prefix-large-sd.c: New test for prefixed
> 	loads/stores with large offsets for the _Decimal32 type.
> 	* gcc.target/powerpc/prefix-large-sf.c: New test for prefixed
> 	loads/stores with large offsets for the float type.
> 	* gcc.target/powerpc/prefix-large-si.c: New test for prefixed
> 	loads/stores with large offsets for the int type.
> 	* gcc.target/powerpc/prefix-large-udi.c: New test for prefixed
> 	loads/stores with large offsets for the unsigned long type.
> 	* gcc.target/powerpc/prefix-large-uhi.c: New test for prefixed
> 	loads/stores with large offsets for the unsigned short type.
> 	* gcc.target/powerpc/prefix-large-uqi.c: New test for prefixed
> 	loads/stores with large offsets for the unsigned char type.
> 	* gcc.target/powerpc/prefix-large-usi.c: New test for prefixed
> 	loads/stores with large offsets for the unsigned int type.
> 	* gcc.target/powerpc/prefix-large-v2df.c: New test for prefixed
> 	loads/stores with large offsets for the vector double type.

I'd probably drop "New" from those.  Aside from that nit, the
descriptions are good.

> 
> --- /tmp/ky2ZAZ_prefix-large-dd.c	2020-04-27 14:05:05.638417056 -0400
> +++ gcc/testsuite/gcc.target/powerpc/prefix-large-dd.c	2020-04-27 14:05:05.406420175 -0400
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target powerpc_prefixed_addr } */
> +/* { dg-options "-O2 -mdejagnu-cpu=future" } */
> +
> +/* Tests for prefixed instructions testing whether we can generate a prefixed
> +   load/store instruction that has a 34-bit offset for _Decimal64 objects.  */
> +
> +#define TYPE _Decimal64
> +
> +#include "prefix-large.h"
> +
> +/* { dg-final { scan-assembler-times {\mplfd\M}  2 } } */
> +/* { dg-final { scan-assembler-times {\mpstfd\M} 2 } } */
> --- /tmp/HDrUG4_prefix-large-df.c	2020-04-27 14:05:05.647416935 -0400
> +++ gcc/testsuite/gcc.target/powerpc/prefix-large-df.c	2020-04-27 14:05:05.411420108 -0400
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target powerpc_prefixed_addr } */
> +/* { dg-options "-O2 -mdejagnu-cpu=future" } */
> +
> +/* Tests for prefixed instructions testing whether we can generate a prefixed
> +   load/store instruction that has a 34-bit offset for double objects.  */
> +
> +#define TYPE double
> +
> +#include "prefix-large.h"
> +
> +/* { dg-final { scan-assembler-times {\mplfd\M}  2 } } */
> +/* { dg-final { scan-assembler-times {\mpstfd\M} 2 } } */
> 
<snip>

> --- /tmp/1H98Oa_prefix-large.h	2020-04-27 14:05:05.737415712 -0400
> +++ gcc/testsuite/gcc.target/powerpc/prefix-large.h	2020-04-27 14:05:05.461419436 -0400
> @@ -0,0 +1,59 @@
> +/* Common tests for prefixed instructions testing whether we can generate a
> +   34-bit offset using 1 instruction.  */
> +
> +typedef signed char	schar;
> +typedef unsigned char	uchar;
> +typedef unsigned short	ushort;
> +typedef unsigned int	uint;
> +typedef unsigned long	ulong;
> +typedef long double	ldouble;
> +typedef vector double	v2df;
> +typedef vector long	v2di;
> +typedef vector float	v4sf;
> +typedef vector int	v4si;
> +
> +#ifndef TYPE
> +#define TYPE ulong
> +#endif
> +
> +#ifndef ITYPE
> +#define ITYPE TYPE
> +#endif
> +
> +#ifndef OTYPE
> +#define OTYPE TYPE
> +#endif
> +

I don't seee any users of ITYPE or OTYPE below.    Those could be
culled.   (if this is likely to be adapted in the future to include
those, probably OK?)


I didn't cross-count the scan-assembler-times stanzas, but being that
the tests are broken up into nice bite-size pieces, this seems
reasonable.

lgtm,
thanks
-Will


> +#if !defined(DO_ADD) && !defined(DO_VALUE) && !defined(DO_SET)
> +#define DO_ADD		1
> +#define DO_VALUE	1
> +#define DO_SET		1
> +#endif
> +
> +#ifndef CONSTANT
> +#define CONSTANT	0x123450UL
> +#endif
> +
> +#if DO_ADD
> +void
> +add (TYPE *p, TYPE a)
> +{
> +  p[CONSTANT] += a;
> +}
> +#endif
> +
> +#if DO_VALUE
> +OTYPE
> +value (TYPE *p)
> +{
> +  return p[CONSTANT];
> +}
> +#endif
> +
> +#if DO_SET
> +void
> +set (TYPE *p, ITYPE a)
> +{
> +  p[CONSTANT] = a;
> +}
> +#endif
> 

Re: [PATCH] PowerPC -mcpu=future Patch 6 of 7, add PC-relative tests

[will schmidt]

On Mon, 2020-04-27 at 16:01 -0400, Michael Meissner via Gcc-patches wrote:
> This patch adds PC-relative tests for -mcpu=future.
> 
> This is patch #6 of 7.  I have checked this on a little endian power8 system
> running Linux, and all tests passed.  Can I check this into the GCC 10 trunk?
> 
> 2020-04-27  Michael Meissner  <meissner@linux.ibm.com>
> 
> 	* gcc.target/powerpc/prefix-pcrel.h: New set of tests to test
> 	prefixed addressing on 'future' system with PC-relative addresses
> 	for various types.
> 	* gcc.target/powerpc/prefix-pcrel-dd.c: New test for prefixed
> 	loads/stores with PC-relative addresses for the _Decimal64 type.
> 	* gcc.target/powerpc/prefix-pcrel-df.c: New test for prefixed
> 	loads/stores with PC-relative addresses for the double type.
> 	* gcc.target/powerpc/prefix-pcrel-di.c: New test for prefixed
> 	loads/stores with PC-relative addresses for the long type.
> 	* gcc.target/powerpc/prefix-pcrel-hi.c: New test for prefixed
> 	loads/stores with PC-relative addresses for the short type.
> 	* gcc.target/powerpc/prefix-pcrel-kf.c: New test for prefixed
> 	loads/stores with PC-relative addresses for the __float128 type.
> 	* gcc.target/powerpc/prefix-pcrel-qi.c: New test for prefixed
> 	loads/stores with PC-relative addresses for the signed char type.
> 	* gcc.target/powerpc/prefix-pcrel-sd.c: New test for prefixed
> 	loads/stores with PC-relative addresses for the _Decimal32 type.
> 	* gcc.target/powerpc/prefix-pcrel-sf.c: New test for prefixed
> 	loads/stores with PC-relative addresses for the float type.
> 	* gcc.target/powerpc/prefix-pcrel-si.c: New test for prefixed
> 	loads/stores with PC-relative addresses for the int type.
> 	* gcc.target/powerpc/prefix-pcrel-udi.c: New test for prefixed
> 	loads/stores with PC-relative addresses for the unsigned long
> 	type.
> 	* gcc.target/powerpc/prefix-pcrel-uhi.c: New test for prefixed
> 	loads/stores with PC-relative addresses for the unsigned short
> 	type.
> 	* gcc.target/powerpc/prefix-pcrel-uqi.c: New test for prefixed
> 	loads/stores with PC-relative addresses for the unsigned char
> 	type.
> 	* gcc.target/powerpc/prefix-pcrel-usi.c: New test for prefixed
> 	loads/stores with PC-relative addresses for the unsigned int
> 	type.
> 	* gcc.target/powerpc/prefix-pcrel-v2df.c: New test for prefixed
> 	loads/stores with PC-relative addresses for the vector double
> 	type.
> 
> --- /tmp/61oqzU_prefix-pcrel-dd.c	2020-04-27 14:11:22.981249397 -0400
> +++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-dd.c	2020-04-27 14:11:22.751252547 -0400
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target powerpc_pcrel } */
> +/* { dg-options "-O2 -mdejagnu-cpu=future" } */
> +
> +/* Tests for prefixed instructions testing whether pc-relative prefixed
> +   instructions are generated for the _Decimal64 type.  */


Too many test references?
Should that be simply "Test whether pc-relative prefixed instructions
are generated for the _Decimal64 type." 

(Same repeated later in the patch).


> +
> +#define TYPE _Decimal64
> +
> +#include "prefix-pcrel.h"
> +
> +/* { dg-final { scan-assembler-times {[@]pcrel}  4 } } */
> +/* { dg-final { scan-assembler-times {\mplfd\M}  2 } } */
> +/* { dg-final { scan-assembler-times {\mpstfd\M} 2 } } */
> --- /tmp/w5tyiy_prefix-pcrel-df.c	2020-04-27 14:11:22.990249274 -0400
> +++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-df.c	2020-04-27 14:11:22.755252492 -0400
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target powerpc_pcrel } */
> +/* { dg-options "-O2 -mdejagnu-cpu=future" } */
> +
> +/* Tests for prefixed instructions testing whether pc-relative prefixed
> +   instructions are generated for the double type.  */
> +
> +#define TYPE double
> +
> +#include "prefix-pcrel.h"
> +
> +/* { dg-final { scan-assembler-times {[@]pcrel}  4 } } */
> +/* { dg-final { scan-assembler-times {\mplfd\M}  2 } } */
> +/* { dg-final { scan-assembler-times {\mpstfd\M} 2 } } */
> --- /tmp/uE672b_prefix-pcrel-di.c	2020-04-27 14:11:22.998249164 -0400
> +++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-di.c	2020-04-27 14:11:22.759252437 -0400
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target powerpc_pcrel } */
> +/* { dg-options "-O2 -mdejagnu-cpu=future" } */
> +
> +/* Tests for prefixed instructions testing whether pc-relative prefixed
> +   instructions are generated for the long type.  */
> +
> +#define TYPE long
> +
> +#include "prefix-pcrel.h"
> +
> +/* { dg-final { scan-assembler-times {[@]pcrel} 4 } } */
> +/* { dg-final { scan-assembler-times {\mpld\M}  2 } } */
> +/* { dg-final { scan-assembler-times {\mpstd\M} 2 } } */
> --- /tmp/UHt8OP_prefix-pcrel-hi.c	2020-04-27 14:11:23.005249069 -0400
> +++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-hi.c	2020-04-27 14:11:22.763252383 -0400
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target powerpc_pcrel } */
> +/* { dg-options "-O2 -mdejagnu-cpu=future" } */
> +
> +/* Tests for prefixed instructions testing whether pc-relative prefixed
> +   instructions are generated for the short type.  */
> +
> +#define TYPE short
> +
> +#include "prefix-pcrel.h"
> +
> +/* { dg-final { scan-assembler-times {[@]pcrel}     4 } } */
> +/* { dg-final { scan-assembler-times {\mplh[az]\M}  2 } } */
> +/* { dg-final { scan-assembler-times {\mpsth\M}     2 } } */


<snip>


> --- /tmp/mOOQPU_prefix-pcrel.h	2020-04-27 14:11:23.087247946 -0400
> +++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel.h	2020-04-27 14:11:22.803251835 -0400
> @@ -0,0 +1,58 @@
> +/* Common tests for prefixed instructions testing whether pc-relative prefixed
> +   instructions are generated for each type.  */
> +
> +typedef signed char	schar;
> +typedef unsigned char	uchar;
> +typedef unsigned short	ushort;
> +typedef unsigned int	uint;
> +typedef unsigned long	ulong;
> +typedef long double	ldouble;
> +typedef vector double	v2df;
> +typedef vector long	v2di;
> +typedef vector float	v4sf;
> +typedef vector int	v4si;
> +
> +#ifndef TYPE
> +#define TYPE ulong
> +#endif
> +
> +#ifndef ITYPE
> +#define ITYPE TYPE
> +#endif
> +
> +#ifndef OTYPE
> +#define OTYPE TYPE
> +#endif
> +
> +static TYPE a;
> +TYPE *p = &a;
> +
> +#if !defined(DO_ADD) && !defined(DO_VALUE) && !defined(DO_SET)
> +#define DO_ADD		1
> +#define DO_VALUE	1
> +#define DO_SET		1
> +#endif
> +
> +#if DO_ADD
> +void
> +add (TYPE b)
> +{
> +  a += b;
> +}
> +#endif
> +
> +#if DO_VALUE
> +OTYPE
> +value (void)
> +{
> +  return (OTYPE)a;
> +}
> +#endif
> +
> +#if DO_SET
> +void
> +set (ITYPE b)
> +{
> +  a = (TYPE)b;
> +}
> +#endif

I didn't fine-tooth check the scan-assembler statements, but the bite-
size testcases seem reasonable.   lgtm
Thanks,
-Will

Re: [PATCH] PowerPC -mcpu=future Patch 7 of 7, Add test for stack checking and large stack frames

[will schmidt]

On Mon, 2020-04-27 at 16:04 -0400, Michael Meissner via Gcc-patches wrote:
> This patch adds a test for the case where we have prefixed load/store
> instructions, a large stack frame, and stack checking is enabled.
> 
> This is patch #7 of 7.  I have checked this patch on a little endian power8
> system running Linux, and the test passed.  Can I check this into the GCC 10
> trunk?
> 
> 2020-04-27  Michael Meissner  <meissner@linux.ibm.com>
> 
> 	* gcc.target/powerpc/prefix-stack-protect.c: New test to make sure
> 	-fstack-protect-strong works with prefixed addressing.
> 
> --- /tmp/OxuBEg_prefix-stack-protect.c	2020-04-27 14:12:53.883004507 -0400
> +++ gcc/testsuite/gcc.target/powerpc/prefix-stack-protect.c	2020-04-27 14:12:53.706006931 -0400
> @@ -0,0 +1,20 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target powerpc_prefixed_addr } */
> +/* { dg-options "-O2 -mdejagnu-cpu=future -fstack-protector-strong" } */
> +
> +/* Test that we can handle large stack frames with -fstack-protector-strong and
> +   prefixed addressing.  This was originally discovered in trying to build

s/in/when/

> +   glibc with -mcpu=future, and vfwprintf.c failed because it used
> +   -fstack-protector-strong.  */
> +
> +extern long foo (char *);
> +
> +long
> +bar (void)
> +{
> +  char buffer[0x20000];
> +  return foo (buffer) + 1;
> +}
> +
> +/* { dg-final { scan-assembler {\mpld\M}  } } */
> +/* { dg-final { scan-assembler {\mpstd\M} } } */
> 

lgtm,
thanks,
-Will

Re: [PATCH] PowerPC -mcpu=future Patch 1 of 7, add target supports for -mpcrel and -mprefixed

[Segher Boessenkool]

Hi!

As Will says, the subject is much too long.  50 chars max is the ideal.
"target supports" isn't clear; maybe

	rs6000: Add effective targets powerpc_{pcrel,prefixed_addr}

or something like it (prefix, colon, capital, no dot).


On Mon, Apr 27, 2020 at 03:46:06PM -0400, Michael Meissner wrote:
> 2020-04-27  Michael Meissner  <meissner@linux.ibm.com>
> 
> 	* lib/target-supports.exp (check_effective_target_powerpc_pcrel):
> 	New target for PowerPC -mcpu=future support.

This isn't a "new target", it's not a "target" after all?  Just say
"New.", you can't go wrong with that (if it is new, heh).

> 	(check_effective_target_powerpc_prefixed_addr): New target for
> 	PowerPC -mcpu=future support.

You also say the same thing for both new functions, which cannot be
right.

> +# Return 1 if the target generates PC-relative instructions automatically
> +proc check_effective_target_powerpc_pcrel { } {
> +    return [check_no_messages_and_pattern powerpc_pcrel \
> +	{\mpld\M.*[@]pcrel} assembly {
> +	    static long s;
> +	    long *p = &s;
> +	    long foo (void) { return s; }
> +	} {-O2 -mcpu=future}]
> +}

A comment on the "long *p" line wouldn't hurt ;-)

Does the "@" need quoting like that?

Do you want to test for the exact word "pcrel", or any word starting
with it?

"If the target generates pcrel automatically"...  well, your test passes
an -mcpu= that makes pcrel possible.  This needs a different description,
maybe a different name, or maybe the test should change?  How is this
effective target used?

> +# Return 1 if the target generates prefixed instructions automatically
> +proc check_effective_target_powerpc_prefixed_addr { } {
> +    return [check_no_messages_and_pattern powerpc_prefixed_addr \
> +	{\mpld\M} assembly {
> +	    long foo (long *p) { return p[0x12345]; }
> +	} {-O2 -mcpu=future}]
> +}

Similar here.


Segher

Re: [PATCH] PowerPC -mcpu=future Patch 2 of 7, Add PLI/PADDI tests

[Segher Boessenkool]

On Mon, Apr 27, 2020 at 04:48:02PM -0500, will schmidt wrote:
> On Mon, 2020-04-27 at 15:48 -0400, Michael Meissner via Gcc-patches
> wrote:
> > Add tests for generating PLI/PADDI with -mcpu=future.
> > 
> > This is patch #2 of 7.  This patch was run on a little endian power8
> > system
> > running Linux and the patches succeeded.
> > 
> > 2020-04-27  Michael Meissner  <meissner@linux.ibm.com>
> > 
> > 	* gcc.target/powerpc/prefix-add.c: New test for -mcpu=future
> > 	generating PADDI for large constant adds.
> > 	* gcc.target/powerpc/prefix-di-constant.c: New test for
> > 	-mcpu=future generating PLI to load up large DImode constants.
> > 	* gcc.target/powerpc/prefix-si-constant.c: New test for
> > 	-mcpu=future generating PLI to load up large SImode constants.
> > 
> > --- /tmp/V53gPm_prefix-add.c	2020-04-27 13:51:49.231124761 -0400
> > +++ gcc/testsuite/gcc.target/powerpc/prefix-add.c	2020-04-27 13:51:38.392270487 -0400
> > @@ -0,0 +1,12 @@
> > +/* { dg-do compile } */
> > +/* { dg-require-effective-target powerpc_prefixed_addr } */
> > +/* { dg-options "-O2 -mdejagnu-cpu=future" } */
> > +
> > +/* Test that PADDI is generated to add a large constant.  */
> > +unsigned long
> 
> Just 'long' or should that be 'long long' ? 
> 
> otherwise, seems straightforward.

The testsuite should usually use "int" and "long long", for 32-bit resp.
64-bit items, so that it works on both 32-bit and 64-bit configureations;
and "long" for register size.  Both "int" and "long" will work fine here.

The patch is okay for trunk, once the effective target situation has been
worked out.


Segher

Re: [PATCH] PowerPC -mcpu=future Patch 3 of 7, Add test for generating prefixed load/store

[Segher Boessenkool]

Hi!

On Mon, Apr 27, 2020 at 05:01:34PM -0500, will schmidt wrote:
> On Mon, 2020-04-27 at 15:53 -0400, Michael Meissner via Gcc-patches wrote:
> > This patch adds a test that verifies that the compiler generates a prefixed
> > load/store instruction where the compiler cannot generate the instruction
> > directly because the offset is not a valid DS or DQ offset.  A DS offset must
> > have the bottom 2 bits clear.  A DQ offset must have the bottom 4 bits clear.
> > Due to the way PowerPC instructions are encoded, some instructions use the DS
> > format and some use the DQ format.
> > 
> > This is patch #3 of 7.  The tests in this patch run on a little endian power8
> > system running Linux.
> > 
> > 2020-04-27  Michael Meissner  <meissner@linux.ibm.com>
> > 
> > 	* gcc.target/powerpc/prefix-ds-dq.c: New test to verify that we
> > 	generate the prefix load/store instructions for traditional
> > 	instructions with an offset that doesn't match DS/DQ
> > 	requirements.
> 
> Can probably safely be shortened to end at "... for traditional
> instructions."   if not even just "New test".  

Yes, just "New." or "New test." please.  An explanation what the test
tests belongs in the test itself (it already is there in this case).

> > +/* { dg-require-effective-target powerpc_prefixed_addr } */
> > +/* { dg-options "-O2 -mdejagnu-cpu=future" } */

Same as for all other tests...  What do the effective targets mean
exactly, do they require some -mcpu=, etc.

> > +unsigned long
> > +load_us_offset1 (unsigned char *p)
> > +{
> > +  return *(unsigned short *)(p + 1);	/* should generate LHZ.  */
> > +}

This violates aliasing rules (without -fno-strict-aliasing), unless p
points to some "short" object -- in which case it has alignment 2
already!

So this testcase needs -fno-strict-aliasing, but also, you need to make
sure GCC does not assume alignment 2 (after the cast) already.  There
are attributes for this.

> > +void
> > +store_ul_offset1 (unsigned long ul, unsigned char *p)
> > +{
> > +  *(unsigned long *)(p + 1) = ul;	/* should generate PSTD.  */
> > +}
> > +
> > +void
> > +store_sl_offset1 (signed long sl, unsigned char *p)
> > +{
> > +  *(signed long *)(p + 1) = sl;		/* should generate PSTD.  */
> > +}

"long long".

> > +void
> > +store_float_offset1 (float f, unsigned char *p)
> > +{
> > +  *(float *)(p + 1) = f;		/* should generate STF.  */
> 
> Comment should be STFD ?
> 
> > +}
> > +
> > +void
> > +store_double_offset1 (double d, unsigned char *p)
> > +{
> > +  *(double *)(p + 1) = d;		/* should generate STD.  */
> 
> Comment should be STFS ? 

The other way around :-)  stfs is for single precision float ("float",
in C), while stfd is for double precision float ("double", in C).

> > +/* { dg-final { scan-assembler-times {\mextsb\M} 1 } } */

Maybe also test there are no extsh and extsw generated?


Segher

Re: [PATCH] PowerPC -mcpu=future Patch 3 of 7, Add test for generating prefixed load/store

[will schmidt]

On Fri, 2020-05-01 at 10:48 -0500, Segher Boessenkool wrote:
> Hi!
> 
> On Mon, Apr 27, 2020 at 05:01:34PM -0500, will schmidt wrote:
> > On Mon, 2020-04-27 at 15:53 -0400, Michael Meissner via Gcc-patches 
> > wrote:
> > > This patch adds a test that verifies that the compiler generates
> > > a prefixed
> > > load/store instruction where the compiler cannot generate the
> > > instruction
> > > directly because the offset is not a valid DS or DQ offset.  A DS
> > > offset must
> > > have the bottom 2 bits clear.  A DQ offset must have the bottom 4
> > > bits clear.
> > > Due to the way PowerPC instructions are encoded, some
> > > instructions use the DS
> > > format and some use the DQ format.
> > > 
> > > This is patch #3 of 7.  The tests in this patch run on a little
> > > endian power8
> > > system running Linux.
> > > 
> > > 
<snip>

> "long long".
> 
> > > +void
> > > +store_float_offset1 (float f, unsigned char *p)
> > > +{
> > > +  *(float *)(p + 1) = f;		/* should generate STF.  */
> > 
> > Comment should be STFD ?
> > 
> > > +}
> > > +
> > > +void
> > > +store_double_offset1 (double d, unsigned char *p)
> > > +{
> > > +  *(double *)(p + 1) = d;		/* should generate
> > > STD.  */
> > 
> > Comment should be STFS ? 
> 
> The other way around :-)  stfs is for single precision float
> ("float",
> in C), while stfd is for double precision float ("double", in C).

I came up with my comment based on what was being tested for further
below.   If the comment is correct the test below is wrong.
(unless i mis-counted something .. always possible but worth double-
checking).  :-)

Thanks,
-Will

> 
> > > +/* { dg-final { scan-assembler-times {\mextsb\M} 1 } } */
> 
> Maybe also test there are no extsh and extsw generated?
> 
> 
> Segher

Re: [PATCH] PowerPC -mcpu=future Patch 3 of 7, Add test for generating prefixed load/store

[Segher Boessenkool]

On Fri, May 01, 2020 at 03:54:26PM -0500, will schmidt wrote:
> > The other way around :-)  stfs is for single precision float
> > ("float",
> > in C), while stfd is for double precision float ("double", in C).
> 
> I came up with my comment based on what was being tested for further
> below.   If the comment is correct the test below is wrong.
> (unless i mis-counted something .. always possible but worth double-
> checking).  :-)

Ah.  The order of the scan-assembler statements does not matter; for
each, dejagnu looks at the whole file.  (And both instructions are
generated only once).


Segher

Re: [PATCH] PowerPC -mcpu=future Patch 3 of 7, Add test for generating prefixed load/store

[will schmidt]

On Fri, 2020-05-01 at 17:02 -0500, Segher Boessenkool wrote:
> On Fri, May 01, 2020 at 03:54:26PM -0500, will schmidt wrote:
> > > The other way around :-)  stfs is for single precision float
> > > ("float",
> > > in C), while stfd is for double precision float ("double", in C).
> > 
> > I came up with my comment based on what was being tested for
> > further
> > below.   If the comment is correct the test below is wrong.
> > (unless i mis-counted something .. always possible but worth
> > double-
> > checking).  :-)
> 
> Ah.  The order of the scan-assembler statements does not matter; for
> each, dejagnu looks at the whole file.  (And both instructions are
> generated only once).
> 

Ok, yeah, right, I misread/misunderstood your comment..  :-)  

Gist of it was that there is a mismatch between asm and comments.  


+  *(float *)(p + 1) = f;		/* should generate STFS.  */
+  *(double *)(p + 1) = d;		/* should generate STFD.  */

+/* { dg-final { scan-assembler-times {\mstfd\M}  1 } } */
+/* { dg-final { scan-assembler-times {\mstfs\M}  1 } } */


thanks,
-Will


> 
> Segher

Re: [PATCH] PowerPC -mcpu=future Patch 4 of 7, Make sure an invalid instruction is not generated

[Segher Boessenkool]

Hi!

On Mon, Apr 27, 2020 at 05:09:15PM -0500, will schmidt wrote:
> > 	* gcc.target/powerpc/prefix-no-premodify.c: Make sure we do not
> > 	generate the non-existent PLWZU instruction if -mcpu=future.
> 
> Should "premodify" instead be "no-update" or "no-update-forms" ?   I
> don't immediately see why "modify" is referenced.

The Power ISA calls it "update form", while GCC calls it "pre-modify"
("pre-increment", "pre-decrement"), or "address side effects", for how
it is put in RTL.

The ISA name makes more sense here I think, yes.


Segher

Re: [PATCH] PowerPC -mcpu=future Patch 4 of 7, Make sure an invalid instruction is not generated

[Segher Boessenkool]

Hi!

On Mon, Apr 27, 2020 at 03:57:59PM -0400, Michael Meissner wrote:
> +#ifndef SIZE
> +#define SIZE 50000
> +#endif
> +
> +struct foo {
> +  unsigned int field;
> +  char pad[SIZE];
> +};
> +
> +struct foo *inc_load (struct foo *p, unsigned int *q)
> +{
> +  *q = (++p)->field;	/* PLWZ, PADDI, STW.  */
> +  return p;
> +}

This makes me wonder what we do if the struct is a multiple of 65536
bytes big, do we still generate a paddi, or will we do the (smaller,
faster) addis?  Not that that matters so very much...

  ...

Yeah, we do do addis, neat!  :-)

Is it better to do paddi and then stw on the modified pointer, or to do
pstw on the original pointer (and the paddi independently)?  In this
testcase, and in general?  The second sequence is lower latency (via the
store), but takes more space.  We probably should do the same tradeoff
as we do with non-prefixed code (or is there any significant difference?)
but maybe that should be looked at again as well.  (Maybe it doesn't
happen often enough to matter either way?)


Segher

Re: [PATCH] PowerPC -mcpu=future Patch 3 of 7, Add test for generating prefixed load/store

[Hans-Peter Nilsson]

On Fri, 1 May 2020, Segher Boessenkool wrote:
> On Mon, Apr 27, 2020 at 05:01:34PM -0500, will schmidt wrote:
> > On Mon, 2020-04-27 at 15:53 -0400, Michael Meissner via Gcc-patches wrote:
> > > +unsigned long
> > > +load_us_offset1 (unsigned char *p)
> > > +{
> > > +  return *(unsigned short *)(p + 1);	/* should generate LHZ.  */
> > > +}
>
> This violates aliasing rules (without -fno-strict-aliasing), unless p
> points to some "short" object -- in which case it has alignment 2
> already!

Ackchyually... that'd be 'unless p+1 points to some "short" object'.

You're allowed to do weird things passing char pointers around
(at least), as long as you point to the right-type object (the
one used when it was assigned) when you dereference it.

Though, I don't know if the same goes if p was something other
than a "char *" or "unsigned char *".

> So this testcase needs -fno-strict-aliasing, but also, you need to make
> sure GCC does not assume alignment 2 (after the cast) already.  There
> are attributes for this.

FWIW, if it needs -fno-strict-aliasing it's for some other
reason than the above (we don't see the assigner in the test).

brgds, H-P

Re: [PATCH] PowerPC -mcpu=future Patch 3 of 7, Add test for generating prefixed load/store

[Segher Boessenkool]

Hi!

On Tue, May 05, 2020 at 08:41:35PM -0400, Hans-Peter Nilsson wrote:
> On Fri, 1 May 2020, Segher Boessenkool wrote:
> > On Mon, Apr 27, 2020 at 05:01:34PM -0500, will schmidt wrote:
> > > On Mon, 2020-04-27 at 15:53 -0400, Michael Meissner via Gcc-patches wrote:
> > > > +unsigned long
> > > > +load_us_offset1 (unsigned char *p)
> > > > +{
> > > > +  return *(unsigned short *)(p + 1);	/* should generate LHZ.  */
> > > > +}
> >
> > This violates aliasing rules (without -fno-strict-aliasing), unless p
> > points to some "short" object -- in which case it has alignment 2
> > already!
> 
> Ackchyually... that'd be 'unless p+1 points to some "short" object'.

Erm yes.

> You're allowed to do weird things passing char pointers around
> (at least), as long as you point to the right-type object (the
> one used when it was assigned) when you dereference it.

And when you cast it to the "bigger" pointer type, already, in general.
Which isn't a problem for any of the powerpc targets at least, not sure
there is any GCC target where it matters currently?

> Though, I don't know if the same goes if p was something other
> than a "char *" or "unsigned char *".

Sure, it is true always: you can do whatever you want with the address,
cast it (validly) to other pointer types, to integer types, slice it,
dice it, whatever you want; but when you dereference it, *that* is where
the "aliasing rules" apply.

> > So this testcase needs -fno-strict-aliasing, but also, you need to make
> > sure GCC does not assume alignment 2 (after the cast) already.  There
> > are attributes for this.
> 
> FWIW, if it needs -fno-strict-aliasing it's for some other
> reason than the above (we don't see the assigner in the test).

Not to be valid code, no.  But for the testcase to test what it wants
to test, it would help.

The point is that you can do a misaligned "lhz" instruction just fine;
you do not need a prefixed form for it, as with say "ld", where the
offset addressing form always does a multiple of four ("DS-form"), while
"pld" (its prefixed version) can take any integer offset ("D-form").  If
GCC already would assume the memory access is naturally aligned the test
doesn't test anything.

But together with it choosing the prefixed forms for ld and lwa etc.,
it's probably good enough anyway.


Segher