From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by sourceware.org (Postfix) with ESMTP id EB5843857020; Tue, 7 Jul 2020 00:18:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org EB5843857020 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=segher@kernel.crashing.org Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id 0670I31V002724; Mon, 6 Jul 2020 19:18:03 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id 0670I3hL002723; Mon, 6 Jul 2020 19:18:03 -0500 X-Authentication-Warning: gate.crashing.org: segher set sender to segher@kernel.crashing.org using -f Date: Mon, 6 Jul 2020 19:18:03 -0500 From: Segher Boessenkool To: Xionghu Luo Cc: gcc-patches@gcc.gnu.org, dje.gcc@gmail.com, wschmidt@linux.ibm.com, guojiufu@linux.ibm.com, linkw@gcc.gnu.org Subject: Re: [PATCH] rs6000: Split movsf_from_si from high word before reload[PR89310] Message-ID: <20200707001803.GR3598@gate.crashing.org> References: <20200706021757.1118129-1-luoxhu@linux.ibm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200706021757.1118129-1-luoxhu@linux.ibm.com> User-Agent: Mutt/1.4.2.3i X-Spam-Status: No, score=-10.4 required=5.0 tests=BAYES_00, JMQ_SPF_NEUTRAL, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, TXREP, T_SPF_HELO_PERMERROR, T_SPF_PERMERROR autolearn=no autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 07 Jul 2020 00:18:06 -0000 Hi! On Sun, Jul 05, 2020 at 09:17:57PM -0500, Xionghu Luo wrote: > For extracting high part element from DImode register like: > > {%1:SF=unspec[r122:DI>>0x20#0] 86;clobber scratch;} > > split it before reload with "and mask" to avoid generating shift right > 32 bit then shift left 32 bit. > > srdi 3,3,32 > sldi 9,3,32 > mtvsrd 1,9 > xscvspdpn 1,1 > > => > > rldicr 3,3,0,31 > mtvsrd 1,3 > xscvspdpn 1,1 Great :-) > +;; For extracting high part element from DImode register like: > +;; {%1:SF=unspec[r122:DI>>0x20#0] 86;clobber scratch;} > +;; split it before reload with "and mask" to avoid generating shift right > +;; 32 bit then shift left 32 bit. > +(define_insn_and_split "movsf_from_si2" > + [(set (match_operand:SF 0 "nonimmediate_operand" > + "=!r, f, v, wa, m, Z, > + Z, wa, ?r, !r") > + (unspec:SF [ > + (subreg:SI (ashiftrt:DI > + (match_operand:DI 1 "input_operand" > + "m, m, wY, Z, r, f, > + wa, r, wa, r") > + (const_int 32)) 0)] > + UNSPEC_SF_FROM_SI)) > + (clobber (match_scratch:DI 2 > + "=X, X, X, X, X, X, > + X, r, X, X"))] > + "TARGET_NO_SF_SUBREG > + && (register_operand (operands[0], SFmode) > + && register_operand (operands[1], DImode))" If the insn condition requires operands 0 and 1 to be register_operands, it can ask for that in the predicates, instead: not nonimmediate_operand and input_operand, but just gpc_reg_operand instead. You can leave out the impossible alternatives as well (0, 1, 2, 3, 4, 5, 6), leaving just (define_insn_and_split "movsf_from_si2" [(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r,!r") (unspec:SF [(subreg:SI (ashiftrt:DI (match_operand:DI 1 "input_operand" "r,wa,r") (const_int 32)) 0)] UNSPEC_SF_FROM_SI)))] "TARGET_NO_SF_SUBREG" "@ # mfvsrwz %0,%x1 mr %0,%1" "&& !reload_completed && vsx_reg_sfsubreg_ok (operands[0], SFmode)" [(const_int 0)] { rtx op0 = operands[0]; rtx op1 = operands[1]; rtx tmp = gen_reg_rtx (DImode); You cannot call gen_reg_rtx too late in the pass pipeline. What we usually do for such cases is put it as a match_scratch in the pattern, and then do code like if (GET_CODE (operands[2]) == SCRATCH) operands[2] = gen_reg_rtx (DImode); so that it will work both before and after reload. /* Avoid split {r155:SI#0=unspec[r133:DI>>0x20#0] 86;clobber scratch;} from PR42745. */ (This line is too long, btw.) if (!SUBREG_P (operands[0])) { rtx mask = GEN_INT (HOST_WIDE_INT_M1U << 32); emit_insn (gen_anddi3 (tmp, op1, mask)); emit_insn (gen_p8_mtvsrd_sf (op0, tmp)); emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0)); DONE; } else FAIL; } [(set_attr "length" "12,*,*") (set_attr "type" "vecfloat,mffgpr,*") (set_attr "isa" "p8v,p8v,*")]) I wonder what will happen if you actually do FAIL here... There then is no insn alternative that can match, so we ICE? In that case, just leave out the whole FAIL thing, it is useless? You can do a gcc_assert if you want to check something. Oh, and maybe you only want to handle GPRs here, not VSRs? So just the "r", not the "wa" at all? What code would it generate for vector regs? Lots of questions, sorry! Segher