From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by sourceware.org (Postfix) with ESMTPS id 391173857C5A for ; Thu, 23 Jul 2020 15:47:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 391173857C5A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=mittosystems.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=jozef.l@mittosystems.com Received: by mail-wm1-x32c.google.com with SMTP id f18so5642158wml.3 for ; Thu, 23 Jul 2020 08:47:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mittosystems.com; s=google; h=date:from:to:subject:message-id:mail-followup-to:references :mime-version:content-disposition:in-reply-to; bh=j5xb4bV12LS6PD8y0fDSy3Z8cyP+fJmyIJ1g+nF6wyg=; b=cJQijxrvXc6+gVKFomzPC2/RvVylE8Z4/HADi4HTfJ/ukjWa7Bulej4JVHH2uFD2x5 E8J2ypWngBNxdNRJt36o6BYC4k/aHgS8Vxn7XI8ycaujxwp21bf4nTU/ue0RQRiZj0/R 2ndHWOZcNYzOgR7DKWSrE4RlSYm+0KSLkXSsZybUiBX+N5JQ9qT82L96vQEeKeJy19ms /4Rc+IrUJGp0twzqvysjGdqBzIinLF3+qTlqRFwh1J5O/GsRjYsPYju+wGrLtyiZCnag Sog88YSYjRiRy4dLx/qeXyx/w5PAiK0rmGS4ER2alhNQdQ72cxQ8BrBC06vbaJtZGRXi NG6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:subject:message-id:mail-followup-to :references:mime-version:content-disposition:in-reply-to; bh=j5xb4bV12LS6PD8y0fDSy3Z8cyP+fJmyIJ1g+nF6wyg=; b=quXRFSFsg1evj3Gy3rSUX/1Vu8ESZk52HZdlYxSDjFMUkfa03fyRI7nKFPtpGzCQAF oRxxjGYaXCyFMSVu8tC1h79Q3lbFoVBk3sFfD21Pn2Z4PqlEBX++F7Oe9epluOW96l4v f8Emcr13XwzaQpvHq6DjsZehKM+JolrZDJDsQMvYfZHQrspc9HDSj2LHgrGhK+zyBFcj 0LyY2UksdkCd22v5T/P4EvWySGMHY0cvoOyBCRhZQOqCU0Yc3+tgNyTp8K3GzcXzXrYt I5YsyMMYlzTMOl+kp6v3Il5PrYJRGdVgrqSNwDZgmFYrRnmu3PwP6BHmIGfIfnq8boxG zNVA== X-Gm-Message-State: AOAM530XRbSVJz0U7qdvUvrYMY2QNe4MzI6Me7Nqz0WqyzItv+6kQ3+B PQXR0OT5PiIqBX2C1sjpQpOL9ysbklk= X-Google-Smtp-Source: ABdhPJz7HRmPY8BuGAQssdre7iYeV0naavjMtr1bF3tdNpEH/7bTNSMHM/xf7h9PdV4LgbFtAQUOsQ== X-Received: by 2002:a7b:cf16:: with SMTP id l22mr5150583wmg.68.1595519241130; Thu, 23 Jul 2020 08:47:21 -0700 (PDT) Received: from jozef-acer-manjaro ([2a01:4b00:87fd:900:5e1d:5c99:56da:76e8]) by smtp.gmail.com with ESMTPSA id v29sm4605626wrv.51.2020.07.23.08.47.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2020 08:47:20 -0700 (PDT) Date: Thu, 23 Jul 2020 16:47:56 +0100 From: Jozef Lawrynowicz To: gcc-patches@gcc.gnu.org Subject: [PATCH 1/5] MSP430: Implement TARGET_MEMORY_MOVE_COST Message-ID: <20200723154756.dgh7y6l6ngej6gpe@jozef-acer-manjaro> Mail-Followup-To: gcc-patches@gcc.gnu.org References: <20200723154356.63ws2xairlmdufji@jozef-acer-manjaro> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="uywiophoi2oqykbl" Content-Disposition: inline In-Reply-To: <20200723154356.63ws2xairlmdufji@jozef-acer-manjaro> X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Jul 2020 15:47:23 -0000 --uywiophoi2oqykbl Content-Type: text/plain; charset=us-ascii Content-Disposition: inline The cycle and size cost of a MOV instruction in different addressing modes can be used to calculate the TARGET_MEMORY_MOVE_COST relative to TARGET_REGISTER_MOVE_COST. --uywiophoi2oqykbl Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename="0001-MSP430-Implement-TARGET_MEMORY_MOVE_COST.patch" >From c801a2851d47601218578c411854de9540486335 Mon Sep 17 00:00:00 2001 From: Jozef Lawrynowicz Date: Thu, 16 Jul 2020 11:28:11 +0100 Subject: [PATCH 1/5] MSP430: Implement TARGET_MEMORY_MOVE_COST The cycle and size cost of a MOV instruction in different addressing modes can be used to calculate the TARGET_MEMORY_MOVE_COST relative to TARGET_REGISTER_MOVE_COST. gcc/ChangeLog: * config/msp430/msp430.c (struct single_op_cost): New struct. (struct double_op_cost): Likewise. (TARGET_REGISTER_MOVE_COST): Don't define but add comment. (TARGET_MEMORY_MOVE_COST): Define to... (msp430_memory_move_cost): New function. (BRANCH_COST): Don't define but add comment. --- gcc/config/msp430/msp430.c | 131 +++++++++++++++++++++++++++++++++++++ 1 file changed, 131 insertions(+) diff --git a/gcc/config/msp430/msp430.c b/gcc/config/msp430/msp430.c index c2b24974364..9e739233fa0 100644 --- a/gcc/config/msp430/msp430.c +++ b/gcc/config/msp430/msp430.c @@ -1043,6 +1043,137 @@ msp430_legitimate_constant (machine_mode mode, rtx x) } +/* Describing Relative Costs of Operations + To model the cost of an instruction, use the number of cycles when + optimizing for speed, and the number of words when optimizing for size. + The cheapest instruction will execute in one cycle and cost one word. + The cycle and size costs correspond to 430 ISA instructions, not 430X + instructions or 430X "address" instructions. The relative costs of 430X + instructions is accurately modeled with the 430 costs. The relative costs + of some "address" instructions can differ, but these are not yet handled. + Adding support for this could improve performance/code size. */ + +const int debug_rtx_costs = 0; + +struct single_op_cost +{ + const int reg; + /* Indirect register (@Rn) or indirect autoincrement (@Rn+). */ + const int ind; + const int mem; +}; + +static const struct single_op_cost cycle_cost_single_op = +{ + 1, 3, 4 +}; + +static const struct single_op_cost size_cost_single_op = +{ + 1, 1, 2 +}; + +/* When the destination of an insn is memory, the cost is always the same + regardless of whether that memory is accessed using indirect register, + indexed or absolute addressing. + When the source operand is memory, indirect register and post-increment have + the same cost, which is lower than indexed and absolute, which also have + the same cost. */ +struct double_op_cost +{ + /* Source operand is a register. */ + const int r2r; + const int r2pc; + const int r2m; + + /* Source operand is memory, using indirect register (@Rn) or indirect + autoincrement (@Rn+) addressing modes. */ + const int ind2r; + const int ind2pc; + const int ind2m; + + /* Source operand is an immediate. */ + const int imm2r; + const int imm2pc; + const int imm2m; + + /* Source operand is memory, using indexed (x(Rn)) or absolute (&ADDR) + addressing modes. */ + const int mem2r; + const int mem2pc; + const int mem2m; +}; + +/* These structures describe the cost of MOV, BIT and CMP instructions, in terms + of clock cycles or words. */ +static const struct double_op_cost cycle_cost_double_op_mov = +{ + 1, 3, 3, + 2, 4, 4, + 2, 3, 4, + 3, 5, 5 +}; + +/* Cycle count when memory is the destination operand is one larger than above + for instructions that aren't MOV, BIT or CMP. */ +static const struct double_op_cost cycle_cost_double_op = +{ + 1, 3, 4, + 2, 4, 5, + 2, 3, 5, + 3, 5, 6 +}; + +static const struct double_op_cost size_cost_double_op = +{ + 1, 1, 2, + 1, 1, 2, + 2, 2, 3, + 2, 2, 3 +}; + +/* TARGET_REGISTER_MOVE_COST + There is only one class of general-purpose, non-fixed registers, and the + relative cost of moving data between them is always the same. + Therefore, the default of 2 is optimal. */ + +#undef TARGET_MEMORY_MOVE_COST +#define TARGET_MEMORY_MOVE_COST msp430_memory_move_cost + +/* Return the cost of moving data between registers and memory. + The returned cost must be relative to the default TARGET_REGISTER_MOVE_COST + of 2. + IN is false if the value is to be written to memory. */ +static int +msp430_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED, + reg_class_t rclass ATTRIBUTE_UNUSED, + bool in) +{ + int cost; + const struct double_op_cost *cost_p; + /* Optimize with a code size focus by default, unless -O2 or above is + specified. */ + bool speed = (!optimize_size && optimize >= 2); + + cost_p = (speed ? &cycle_cost_double_op_mov : &size_cost_double_op); + + if (in) + /* Reading from memory using indirect addressing is assumed to be the more + common case. */ + cost = cost_p->ind2r; + else + cost = cost_p->r2m; + + /* All register to register moves cost 1 cycle or 1 word, so multiply by 2 + to get the costs relative to TARGET_REGISTER_MOVE_COST of 2. */ + return 2 * cost; +} + +/* BRANCH_COST + Changing from the default of 1 doesn't affect code generation, presumably + because there are no conditional move insns - when a condition is involved, + the only option is to use a cbranch. */ + #undef TARGET_RTX_COSTS #define TARGET_RTX_COSTS msp430_rtx_costs -- 2.27.0 --uywiophoi2oqykbl--