From: Segher Boessenkool <segher@kernel.crashing.org>
To: Michael Meissner <meissner@linux.ibm.com>,
gcc-patches@gcc.gnu.org, David Edelsohn <dje.gcc@gmail.com>
Subject: Re: [PATCH] Power10: Add BRH, BRW, BRD support.
Date: Thu, 6 Aug 2020 13:11:21 -0500 [thread overview]
Message-ID: <20200806181121.GU6753@gate.crashing.org> (raw)
In-Reply-To: <20200805024015.GA22456@ibm-tinman.the-meissners.org>
On Tue, Aug 04, 2020 at 10:40:15PM -0400, Michael Meissner wrote:
> The power10 processor adds 3 new instructions (BRH, BRW, BRD) that byte swaps
> half-words, words, and double-words within a GPR register.
The brh insn reverses the bytes in each of four 16-bit words in a GPR,
but this patch only does it for HImode. Similar for brw. Okay.
> 2020-08-04 Michael Meissner <meissner@linux.ibm.com>
>
> * config/rs6000/rs6000.md (bswaphi2_reg): Generate the BRH
> instruction on ISA 3.1.
The changelog should just describe the change, not the effect of the
change, so just "New define_insn." or "New pattern." or "New." here.
All other info goes in the commit message.
This patch is okay for trunk, and all backports later. Thanks Mike!
Segher
prev parent reply other threads:[~2020-08-06 18:11 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-05 2:40 Michael Meissner
2020-08-06 18:11 ` Segher Boessenkool [this message]
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