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Date: Mon, 21 Sep 2020 10:56:06 -0500
From: Segher Boessenkool <segher@kernel.crashing.org>
To: Alan Modra <amodra@gmail.com>
Cc: gcc-patches@sourceware.org, Peter Bergner <bergner@vnet.ibm.com>
Subject: Re: [RS6000] rotate and mask constants
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On Tue, Sep 15, 2020 at 04:46:08PM +0930, Alan Modra wrote:
> On Tue, Sep 15, 2020 at 10:49:46AM +0930, Alan Modra wrote:
> > Implement more two insn constants.
> 
> And tests.  rot_cst1 checks the values generated, rot_cst2 checks
> instruction count.
> 
> 	* gcc.target/powerpc/rot_cst.h,
> 	* gcc.target/powerpc/rot_cst1.c,
> 	* gcc.target/powerpc/rot_cst2.c: New tests.

> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/rot_cst1.c
> @@ -0,0 +1,68 @@
> +/* { dg-do run { target lp64 } } */

This doesn't need lp64.

> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/rot_cst2.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile { target lp64 } } */
> +/* { dg-options "-O2" } */
> +
> +#include "rot_cst.h"
> +
> +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 122 } } */

Please write (in comments) how much of each insn are expected, and
possibly for what function?  Also, bonus points if you make this work
for 32 bit as well (it is almost required even).


Segher