From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 3C0913A53804 for ; Thu, 24 Sep 2020 20:43:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 3C0913A53804 Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 08OKWpdb057957; Thu, 24 Sep 2020 16:43:03 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 33s1hssxj6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Sep 2020 16:43:03 -0400 Received: from m0098409.ppops.net (m0098409.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 08OKWr8w058152; Thu, 24 Sep 2020 16:43:02 -0400 Received: from ppma03dal.us.ibm.com (b.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.11]) by mx0a-001b2d01.pphosted.com with ESMTP id 33s1hssxhu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Sep 2020 16:43:02 -0400 Received: from pps.filterd (ppma03dal.us.ibm.com [127.0.0.1]) by ppma03dal.us.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 08OKaxbL020022; Thu, 24 Sep 2020 20:43:01 GMT Received: from b01cxnp22036.gho.pok.ibm.com (b01cxnp22036.gho.pok.ibm.com [9.57.198.26]) by ppma03dal.us.ibm.com with ESMTP id 33n9m9x7qr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Sep 2020 20:43:01 +0000 Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp22036.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 08OKh1XY40763718 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 24 Sep 2020 20:43:01 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 16220124054; Thu, 24 Sep 2020 20:43:01 +0000 (GMT) Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8B7F9124052; Thu, 24 Sep 2020 20:43:00 +0000 (GMT) Received: from ibm-toto.the-meissners.org (unknown [9.160.88.183]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTPS; Thu, 24 Sep 2020 20:43:00 +0000 (GMT) Date: Thu, 24 Sep 2020 16:42:59 -0400 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt , Peter Bergner , Jeff Law , Jonathan Wakely Subject: [PATCH 7/9] PowerPC: Update IEEE 128-bit built-in functions to work if long double is IEEE 128-bit. Message-ID: <20200924204259.GG31597@ibm-toto.the-meissners.org> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt , Peter Bergner , Jeff Law , Jonathan Wakely References: <20200924202036.GA28437@ibm-toto.the-meissners.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200924202036.GA28437@ibm-toto.the-meissners.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-09-24_15:2020-09-24, 2020-09-24 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 mlxscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009240150 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Sep 2020 20:43:06 -0000 PowerPC: Update IEEE 128-bit built-in functions to work if long double is IEEE 128-bit. This patch adds long double variants of the power10 __float128 built-in functions. This is needed because __float128 uses TFmode in this case instead of KFmode. gcc/ 2020-09-23 Michael Meissner * config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Add built-in functions for long double built-ins that use IEEE 128-bit. (rs6000_expand_builtin): Change the KF IEEE 128-bit comparison insns to TF if long double is IEEE 128-bit. * config/rs6000/rs6000-builtin.def (scalar_extract_exptf): Add support for long double being IEEE 128-bit built-in functions. (scalar_extract_sigtf): Likewise. (scalar_test_neg_tf): Likewise. (scalar_insert_exp_tf): Likewise. (scalar_insert_exp_tfp): Likewise. (scalar_cmp_exp_tf_gt): Likewise. (scalar_cmp_exp_tf_lt): Likewise. (scalar_cmp_exp_tf_eq): Likewise. (scalar_cmp_exp_tf_unordered): Likewise. (scalar_test_data_class_tf): Likewise. --- gcc/config/rs6000/rs6000-builtin.def | 11 ++++++++ gcc/config/rs6000/rs6000-call.c | 40 ++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index e91a48ddf5f..7d52961c8cf 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -2401,8 +2401,11 @@ BU_P9V_64BIT_VSX_1 (VSESDP, "scalar_extract_sig", CONST, xsxsigdp) BU_FLOAT128_HW_VSX_1 (VSEEQP, "scalar_extract_expq", CONST, xsxexpqp_kf) BU_FLOAT128_HW_VSX_1 (VSESQP, "scalar_extract_sigq", CONST, xsxsigqp_kf) +BU_FLOAT128_HW_VSX_1 (VSEETF, "scalar_extract_exptf", CONST, xsxexpqp_tf) +BU_FLOAT128_HW_VSX_1 (VSESTF, "scalar_extract_sigtf", CONST, xsxsigqp_tf) BU_FLOAT128_HW_VSX_1 (VSTDCNQP, "scalar_test_neg_qp", CONST, xststdcnegqp_kf) +BU_FLOAT128_HW_VSX_1 (VSTDCNTF, "scalar_test_neg_tf", CONST, xststdcnegqp_tf) BU_P9V_VSX_1 (VSTDCNDP, "scalar_test_neg_dp", CONST, xststdcnegdp) BU_P9V_VSX_1 (VSTDCNSP, "scalar_test_neg_sp", CONST, xststdcnegsp) @@ -2420,6 +2423,8 @@ BU_P9V_64BIT_VSX_2 (VSIEDPF, "scalar_insert_exp_dp", CONST, xsiexpdpf) BU_FLOAT128_HW_VSX_2 (VSIEQP, "scalar_insert_exp_q", CONST, xsiexpqp_kf) BU_FLOAT128_HW_VSX_2 (VSIEQPF, "scalar_insert_exp_qp", CONST, xsiexpqpf_kf) +BU_FLOAT128_HW_VSX_2 (VSIETF, "scalar_insert_exp_tf", CONST, xsiexpqp_tf) +BU_FLOAT128_HW_VSX_2 (VSIETFF, "scalar_insert_exp_tfp", CONST, xsiexpqpf_tf) BU_P9V_VSX_2 (VSCEDPGT, "scalar_cmp_exp_dp_gt", CONST, xscmpexpdp_gt) BU_P9V_VSX_2 (VSCEDPLT, "scalar_cmp_exp_dp_lt", CONST, xscmpexpdp_lt) @@ -2431,7 +2436,13 @@ BU_P9V_VSX_2 (VSCEQPLT, "scalar_cmp_exp_qp_lt", CONST, xscmpexpqp_lt_kf) BU_P9V_VSX_2 (VSCEQPEQ, "scalar_cmp_exp_qp_eq", CONST, xscmpexpqp_eq_kf) BU_P9V_VSX_2 (VSCEQPUO, "scalar_cmp_exp_qp_unordered", CONST, xscmpexpqp_unordered_kf) +BU_P9V_VSX_2 (VSCETFGT, "scalar_cmp_exp_tf_gt", CONST, xscmpexpqp_gt_tf) +BU_P9V_VSX_2 (VSCETFLT, "scalar_cmp_exp_tf_lt", CONST, xscmpexpqp_lt_tf) +BU_P9V_VSX_2 (VSCETFEQ, "scalar_cmp_exp_tf_eq", CONST, xscmpexpqp_eq_tf) +BU_P9V_VSX_2 (VSCETFUO, "scalar_cmp_exp_tf_unordered", CONST, xscmpexpqp_unordered_tf) + BU_FLOAT128_HW_VSX_2 (VSTDCQP, "scalar_test_data_class_qp", CONST, xststdcqp_kf) +BU_FLOAT128_HW_VSX_2 (VSTDCTF, "scalar_test_data_class_tf", CONST, xststdcqp_tf) BU_P9V_VSX_2 (VSTDCDP, "scalar_test_data_class_dp", CONST, xststdcdp) BU_P9V_VSX_2 (VSTDCSP, "scalar_test_data_class_sp", CONST, xststdcsp) diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index a8b520834c7..8dc779df1f9 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -4587,6 +4587,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 }, { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCQP, RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 }, + { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCTF, + RS6000_BTI_bool_int, RS6000_BTI_long_double, RS6000_BTI_INTSI, 0 }, { P9V_BUILTIN_VEC_VSTDCSP, P9V_BUILTIN_VSTDCSP, RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 }, @@ -4594,6 +4596,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 }, { P9V_BUILTIN_VEC_VSTDCQP, P9V_BUILTIN_VSTDCQP, RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 }, + { P9V_BUILTIN_VEC_VSTDCQP, P9V_BUILTIN_VSTDCTF, + RS6000_BTI_bool_int, RS6000_BTI_long_double, RS6000_BTI_INTSI, 0 }, { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNSP, RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 }, @@ -4601,6 +4605,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 }, { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNQP, RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 }, + { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNTF, + RS6000_BTI_bool_int, RS6000_BTI_long_double, 0, 0 }, { P9V_BUILTIN_VEC_VSTDCNSP, P9V_BUILTIN_VSTDCNSP, RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 }, @@ -4608,16 +4614,22 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 }, { P9V_BUILTIN_VEC_VSTDCNQP, P9V_BUILTIN_VSTDCNQP, RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 }, + { P9V_BUILTIN_VEC_VSTDCNQP, P9V_BUILTIN_VSTDCNTF, + RS6000_BTI_bool_int, RS6000_BTI_long_double, 0, 0 }, { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEDP, RS6000_BTI_UINTSI, RS6000_BTI_double, 0, 0 }, { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEQP, RS6000_BTI_UINTDI, RS6000_BTI_ieee128_float, 0, 0 }, + { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEETF, + RS6000_BTI_UINTDI, RS6000_BTI_long_double, 0, 0 }, { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESDP, RS6000_BTI_UINTDI, RS6000_BTI_double, 0, 0 }, { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESQP, RS6000_BTI_UINTTI, RS6000_BTI_ieee128_float, 0, 0 }, + { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESTF, + RS6000_BTI_UINTTI, RS6000_BTI_long_double, 0, 0 }, { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDP, RS6000_BTI_double, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 }, @@ -4626,25 +4638,37 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQP, RS6000_BTI_ieee128_float, RS6000_BTI_UINTTI, RS6000_BTI_UINTDI, 0 }, + { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIETF, + RS6000_BTI_long_double, RS6000_BTI_UINTTI, RS6000_BTI_UINTDI, 0 }, { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQPF, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, RS6000_BTI_UINTDI, 0 }, + { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIETFF, + RS6000_BTI_long_double, RS6000_BTI_long_double, RS6000_BTI_UINTDI, 0 }, { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEDPGT, RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEQPGT, RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, + { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCETFGT, + RS6000_BTI_INTSI, RS6000_BTI_long_double, RS6000_BTI_long_double, 0 }, { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEDPLT, RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEQPLT, RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, + { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCETFLT, + RS6000_BTI_INTSI, RS6000_BTI_long_double, RS6000_BTI_long_double, 0 }, { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEDPEQ, RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEQPEQ, RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, + { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCETFEQ, + RS6000_BTI_INTSI, RS6000_BTI_long_double, RS6000_BTI_long_double, 0 }, { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEDPUO, RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEQPUO, RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, + { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCETFUO, + RS6000_BTI_INTSI, RS6000_BTI_long_double, RS6000_BTI_long_double, 0 }, { P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_XL_LEN_R, RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI, @@ -12534,6 +12558,22 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, case CODE_FOR_xsiexpqp_kf: icode = CODE_FOR_xsiexpqp_tf; break; case CODE_FOR_xsiexpqpf_kf: icode = CODE_FOR_xsiexpqpf_tf; break; case CODE_FOR_xststdcqp_kf: icode = CODE_FOR_xststdcqp_tf; break; + + case CODE_FOR_xscmpexpqp_eq_kf: + icode = CODE_FOR_xscmpexpqp_eq_tf; + break; + + case CODE_FOR_xscmpexpqp_lt_kf: + icode = CODE_FOR_xscmpexpqp_lt_tf; + break; + + case CODE_FOR_xscmpexpqp_gt_kf: + icode = CODE_FOR_xscmpexpqp_gt_tf; + break; + + case CODE_FOR_xscmpexpqp_unordered_kf: + icode = CODE_FOR_xscmpexpqp_unordered_tf; + break; } if (TARGET_DEBUG_BUILTIN) -- 2.22.0 -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meissner@linux.ibm.com, phone: +1 (978) 899-4797