From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by sourceware.org (Postfix) with ESMTP id B59CA3857001 for ; Mon, 5 Oct 2020 15:37:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org B59CA3857001 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=segher@kernel.crashing.org Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id 095FaNqa032766; Mon, 5 Oct 2020 10:36:24 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id 095FaMJJ032759; Mon, 5 Oct 2020 10:36:22 -0500 X-Authentication-Warning: gate.crashing.org: segher set sender to segher@kernel.crashing.org using -f Date: Mon, 5 Oct 2020 10:36:22 -0500 From: Segher Boessenkool To: Hans-Peter Nilsson Cc: will schmidt , Raoni Fassina Firmino , gcc-patches@gcc.gnu.org, joseph@codesourcery.com Subject: Re: [PATCH v2] builtins: rs6000: Add builtins for fegetround, feclearexcept and feraiseexcept [PR94193] Message-ID: <20201005153622.GE2672@gate.crashing.org> References: <20200904155230.nyssphhldu47hbve@work-tp> <7f35c652dda1a1dd99a4db64d6d15987ce160169.camel@vnet.ibm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.3i X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, JMQ_SPF_NEUTRAL, KAM_DMARC_STATUS, TXREP, T_SPF_HELO_PERMERROR, T_SPF_PERMERROR autolearn=no autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 05 Oct 2020 15:37:28 -0000 Hi! On Sun, Oct 04, 2020 at 09:56:01PM -0400, Hans-Peter Nilsson wrote: > Please excuse a comment from the gallery: > > On Mon, 28 Sep 2020, will schmidt via Gcc-patches wrote: > > On Fri, 2020-09-04 at 12:52 -0300, Raoni Fassina Firmino via Gcc-patches wrote: > > > +(define_expand "feraiseexceptsi" > > > + [(use (match_operand:SI 1 "const_int_operand" "n")) > > > + (set (match_operand:SI 0 "gpc_reg_operand") > > > + (const_int 0))] > > > + "TARGET_HARD_FLOAT" > > > +{ > > > + switch (INTVAL (operands[1])) > > > + { > > > + case 0x2000000: /* FE_INEXACT */ > > > + case 0x4000000: /* FE_DIVBYZERO */ > > > + case 0x8000000: /* FE_UNDERFLOW */ > > > + case 0x10000000: /* FE_OVERFLOW */ > > > + break; > > > + default: > > > + FAIL; > > > + } > > > + > > > + rtx tmp = gen_rtx_CONST_INT (SImode, __builtin_clz (INTVAL (operands[1]))); > > This doesn't appear to be very portable, to any-cxx11-compiler > that doesn't pretend to be gcc-intrinsics-compatible. Yeah, very good point! Should this pattern not allow setting more than one exception bit at once, btw? So you can first see if any out-of-range bits are set: unsigned int fe = INTVAL (operands[1]); if ((fe & 0x1e000000) != fe) FAIL; and then see if more than one bit is set: if (fe & (fe - 1)) FAIL; but also disallow zero: if (!fe) FAIL; Or, you can just put the bit number in the switch cases for the four bits. There are only four, after all. Thanks, Segher