Re: [PATCH] dwarf: Multi-register CFI address support

[Jakub Jelinek <jakub@redhat.com>]

On Fri, Aug 28, 2020 at 01:04:51PM +0100, Andrew Stubbs wrote:
> This patch introduces DWARF CFI support for architectures that require
> multiple registers to hold pointers, such as the stack pointer, frame
> pointer, and return address. The motivating case is the AMD GCN architecture
> which has 64-bit address pointers, but 32-bit registers.
> 
> The current implementation permits program variables to span as many
> registers as they need, but assumes that CFI expressions will only need a
> single register for each frame value.
> 
> To be fair, the DWARF standard makes a similar assumption; the engineers
> working on LLVM and GDB, at AMD, have therefore invented some new DWARF
> operators that they plan to propose for a future standard. Only one is
> relevant here, however: DW_OP_LLVM_piece_end. (Unfortunately this clashes
> with an AArch64 extension, but I think we can cope using an alias -- only
> GCC dumps will be confusing.)

First of all, in GCC it definitely should not be called DW_OP_LLVM_*, either
we adopt it also as a GNU extension and then we should call it DW_OP_GNU_*,
or we don't and then we shouldn't emit it.

For the beginning, it would help if you posted some examples of how
the CFI info would look like on typical functions.

I fear the piece_end is just a sign of misunderstanding of the DWARF
expression vs. DWARF location description differences on the AMD side.
Because all of DW_CFA_def_cfa_expression, DW_CFA_expression and
DW_CFA_val_expression take as one of their operands a DWARF expression
rather than DWARF location description, so e.g. DW_OP_piece can't appear in
those.

And, if GCN DWARF uses 64-bit addresses, it isn't clear why one can't use
existing
DW_CFA_def_cfa_expression <DW_OP_breg4 0 DW_OP_const1u 32 DW_OP_shl DW_OP_breg5 16 DW_OP_plus>
or similar (assuming you want CFA of (reg4 << 32) + reg5 + 16.

	Jakub