From: Alan Modra <amodra@gmail.com>
To: gcc-patches@gcc.gnu.org
Cc: Segher Boessenkool <segher@kernel.crashing.org>,
David Edelsohn <dje.gcc@gmail.com>
Subject: [RS6000] Tests that use int128_t and -m32
Date: Sun, 25 Oct 2020 21:50:01 +1030 [thread overview]
Message-ID: <20201025112001.GC15956@bubble.grove.modra.org> (raw)
All these tests fail with -m32 due to lack of int128 support, in some
cases with what I thought was not the best error message. For example
vsx_mask-move-runnable.c:34:3: error: unknown type name 'vector'
is misleading. The problem isn't "vector" but "vector __uint128_t".
* gcc.target/powerpc/vsx-load-element-extend-char.c: Require int128.
* gcc.target/powerpc/vsx-load-element-extend-int.c: Likewise.
* gcc.target/powerpc/vsx-load-element-extend-longlong.c: Likewise.
* gcc.target/powerpc/vsx-load-element-extend-short.c: Likewise.
* gcc.target/powerpc/vsx-store-element-truncate-char.c: Likewise.
* gcc.target/powerpc/vsx-store-element-truncate-int.c: Likewise.
* gcc.target/powerpc/vsx-store-element-truncate-longlong.c: Likewise.
* gcc.target/powerpc/vsx-store-element-truncate-short.c: Likewise.
* gcc.target/powerpc/vsx_mask-count-runnable.c: Likewise.
* gcc.target/powerpc/vsx_mask-expand-runnable.c: Likewise.
* gcc.target/powerpc/vsx_mask-extract-runnable.c: Likewise.
* gcc.target/powerpc/vsx_mask-move-runnable.c: Likewise.
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
index 0b8cfd610f8..7a7cb77c3a0 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
@@ -4,6 +4,7 @@
/* { dg-do compile {target power10_ok} } */
/* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
/* { dg-options "-mdejagnu-cpu=power10 -O3" } */
/* At the time of writing, the number of lxvrbx instructions is
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c
index b10d3cb43d2..414678c9461 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c
@@ -4,6 +4,7 @@
/* { dg-do compile {target power10_ok} } */
/* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
/* Deliberately set optization to zero for this test to confirm
the lxvr*x instruction is generated. At higher optimization levels
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c
index 52fcf2e572f..c1e3ebc25ca 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c
@@ -4,6 +4,7 @@
/* { dg-do compile {target power10_ok} } */
/* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
/* { dg-options "-mdejagnu-cpu=power10 -O3" } */
/* At time of writing, we also geenerate a .constrprop copy
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c
index 8fc0cc66eb7..698ba30c6f8 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c
@@ -4,6 +4,7 @@
/* { dg-do compile {target power10_ok} } */
/* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
/* Deliberately set optization to zero for this test to confirm
the lxvr*x instruction is generated. At higher optimization levels
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c
index 99f3904983b..53fc2cc9bae 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c
@@ -3,6 +3,7 @@
/* { dg-do compile {target power10_ok} } */
/* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
/* Deliberately set optization to zero for this test to confirm
the stxvr*x instruction is generated. At higher optimization levels
the instruction we are looking for is sometimes replaced by other
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c
index 6e2acf83c38..4c64b413e16 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c
@@ -3,6 +3,7 @@
/* { dg-do compile {target power10_ok} } */
/* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
/* Deliberately set optization to zero for this test to confirm
the stxvr*x instruction is generated. At higher optimization levels
the instruction we are looking for is sometimes replaced by other
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c
index 7fce6a44d4f..465fbeaf6ab 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c
@@ -3,6 +3,7 @@
/* { dg-do compile {target power10_ok} } */
/* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
/* Deliberately set optization to zero for this test to confirm
the stxvr*x instruction is generated. At higher optimization levels
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c
index 17925c87732..f87256921bf 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c
@@ -3,6 +3,7 @@
/* { dg-do compile {target power10_ok} } */
/* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
/* Deliberately set optization to zero for this test to confirm
the stxvr*x instruction is generated. At higher optimization levels
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
index 5862517eae9..6ac4ed2173f 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { power10_hw } } } */
/* { dg-do link { target { ! power10_hw } } } */
/* { dg-options "-mcpu=power10 -O2" } */
-/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target { int128 && power10_ok } } */
/* Check that the expected 128-bit instructions are generated if the processor
supports the 128-bit integer instructions. */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
index 13b4c8afd4f..05fedf77eb9 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { power10_hw } } } */
/* { dg-do link { target { ! power10_hw } } } */
/* { dg-options "-mcpu=power10 -O2" } */
-/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target { int128 && power10_ok } } */
/* Check that the expected 128-bit instructions are generated if the processor
supports the 128-bit integer instructions. */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
index d58a6b0b682..6e952695905 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { power10_hw } } } */
/* { dg-do link { target { ! power10_hw } } } */
/* { dg-options "-mcpu=power10 -O2" } */
-/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target { int128 && power10_ok } } */
/* Check that the expected 128-bit instructions are generated if the processor
supports the 128-bit integer instructions. */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
index 9147d67c9d1..c2eb53d3bb2 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { power10_hw } } } */
/* { dg-do link { target { ! power10_hw } } } */
/* { dg-options "-mcpu=power10 -O2" } */
-/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target { int128 && power10_ok } } */
/* Check that the expected 128-bit instructions are generated if the processor
supports the 128-bit integer instructions. */
--
Alan Modra
Australia Development Lab, IBM
next reply other threads:[~2020-10-25 11:20 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-25 11:20 Alan Modra [this message]
2020-10-25 14:43 ` David Edelsohn
2020-10-26 12:04 ` Alan Modra
2020-10-26 12:35 ` Segher Boessenkool
2020-10-26 12:33 ` Segher Boessenkool
2020-10-26 23:09 ` Alan Modra
2020-10-27 0:57 ` [RS6000] Separate dg-require-effective-target options Alan Modra
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