* Enable MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for march=tremont
@ 2020-11-09 8:49 Cui, Lili
2020-11-09 9:03 ` Uros Bizjak
0 siblings, 1 reply; 8+ messages in thread
From: Cui, Lili @ 2020-11-09 8:49 UTC (permalink / raw)
To: Uros Bizjak, GCC Patches
[-- Attachment #1: Type: text/plain, Size: 11681 bytes --]
Hi Uros,
This patch is to correct some instruction sets for march=Tremont/Broadwell/Silvermont/knl
Bootstrap is ok, and no regressions for i386/x86-64 testsuite.
OK for master?
[PATCH] Enable MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for
march=tremont
1. Enable MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for march=tremont
2. Move PREFETCHW from march=broadwell to march=silvermont.
3. Add PREFETCHWT1 to march=knl
gcc/ChangeLog:
PR target/97685
* config/i386/i386.h:
(PTA_BROADWELL): Delete PTA_PRFCHW.
(PTA_SILVERMONT): Add PTA_PRFCHW.
(PTA_KNL): Add PTA_PREFETCHWT1.
(PTA_TREMONT): Add PTA_MOVDIRI, PTA_MOVDIR64B, PTA_CLDEMOTE and PTA_WAITPKG.
* doc/invoke.texi: Delete PREFETCHW for broadwell, skylake, knl, knm,
skylake-avx512, cannonlake, icelake-client, icelake-server, cascadelake,
cooperlake, tigerlake and sapphirerapids.
Add PREFETCHW for silvermont, goldmont, goldmont-plus and tremont.
Add XSAVEC and XSAVES for goldmont, goldmont-plus and tremont.
Add MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for tremont.
Add KEYLOCKER and HREST for alderlake.
Add AMX-BF16, AMX-TILE, AMX-INT8 and UINTR for sapphirerapids.
Add KEYLOCKER for tigerlake.
---
gcc/config/i386/i386.h | 10 +++----
gcc/doc/invoke.texi | 59 +++++++++++++++++++++---------------------
2 files changed, 35 insertions(+), 34 deletions(-)
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index d0c157a9970..5e01fe6b841 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2515,8 +2515,7 @@ const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
| PTA_RDRND | PTA_F16C;
const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
| PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
-const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
- | PTA_RDSEED;
+const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_RDSEED;
const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES | PTA_CLFLUSHOPT
| PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
@@ -2541,16 +2540,17 @@ const wide_int_bitmask PTA_SAPPHIRERAPIDS = PTA_COOPERLAKE | PTA_MOVDIRI
const wide_int_bitmask PTA_ALDERLAKE = PTA_SKYLAKE | PTA_CLDEMOTE | PTA_PTWRITE
| PTA_WAITPKG | PTA_SERIALIZE | PTA_HRESET | PTA_KL | PTA_WIDEKL;
const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
- | PTA_AVX512F | PTA_AVX512CD;
+ | PTA_AVX512F | PTA_AVX512CD | PTA_PREFETCHWT1;
const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
-const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
+const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND
+ | PTA_PRFCHW;
const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_AES | PTA_SHA | PTA_XSAVE
| PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
| PTA_FSGSBASE;
const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
| PTA_SGX | PTA_PTWRITE;
const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
- | PTA_GFNI;
+ | PTA_GFNI | PTA_MOVDIRI | PTA_MOVDIR64B | PTA_CLDEMOTE | PTA_WAITPKG;
const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
| PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index d2a188d7c75..d01beb248e1 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -29528,14 +29528,14 @@ BMI, BMI2 and F16C instruction set support.
@item broadwell
Intel Broadwell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX and PREFETCHW instruction set support.
+SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2,
+F16C, RDSEED and ADCX instruction set support.
@item skylake
Intel Skylake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC and
-XSAVES instruction set support.
+BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC and XSAVES instruction set
+support.
@item bonnell
Intel Bonnell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
@@ -29543,52 +29543,53 @@ instruction set support.
@item silvermont
Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, POPCNT, AES, PCLMUL and RDRND instruction set support.
+SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL and RDRND instruction set support.
@item goldmont
Intel Goldmont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT and FSGSBASE
-instruction set support.
+SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES,
+XSAVEOPT and FSGSBASE instruction set support.
@item goldmont-plus
Intel Goldmont Plus CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
-SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE,
-PTWRITE, RDPID, SGX and UMIP instruction set support.
+SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,
+XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX and UMIP instruction set support.
@item tremont
Intel Tremont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, PTWRITE,
-RDPID, SGX, UMIP, GFNI-SSE, CLWB and ENCLV instruction set support.
+SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES,
+XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, UMIP, GFNI-SSE, CLWB, MOVDIRI,
+MOVDIR64B, CLDEMOTE and WAITPKG instruction set support.
@item knl
Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, AVX512F, AVX512PF, AVX512ER and
+BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHWT1, AVX512F, AVX512PF, AVX512ER and
AVX512CD instruction set support.
@item knm
Intel Knights Mill CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, AVX512F, AVX512PF, AVX512ER, AVX512CD,
+BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHWT1, AVX512F, AVX512PF, AVX512ER, AVX512CD,
AVX5124VNNIW, AVX5124FMAPS and AVX512VPOPCNTDQ instruction set support.
@item skylake-avx512
Intel Skylake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
+BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
CLWB, AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support.
@item cannonlake
Intel Cannonlake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
-RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
+RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC,
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
AVX512IFMA, SHA and UMIP instruction set support.
@item icelake-client
Intel Icelake Client CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
-RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
+RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC,
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
@@ -29596,7 +29597,7 @@ AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
@item icelake-server
Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
-RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
+RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC,
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES, PCONFIG and WBNOINVD instruction
@@ -29605,37 +29606,37 @@ set support.
@item cascadelake
Intel Cascadelake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
-BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
+BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
AVX512VL, AVX512BW, AVX512DQ, AVX512CD and AVX512VNNI instruction set support.
@item cooperlake
Intel cooperlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
-BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
+BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI and AVX512BF16 instruction
set support.
@item tigerlake
Intel Tigerlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
-BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
-AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP,
-RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ,
-VAES, PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B and AVX512VP2INTERSECT instruction
-set support.
+BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, AVX512VL,
+AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP, RDPID,
+GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES,
+PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT and KEYLOCKER
+instruction set support.
@item sapphirerapids
Intel sapphirerapids CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND,
-FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES,
-AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI, AVX512BF16,
-MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG,
-SERIALIZE and TSXLDTRK instruction set support.
+FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
+AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI, AVX512BF16, MOVDIRI,
+MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE,
+TSXLDTRK, UINTR, AMX-BF16, AMX-TILE and AMX-INT8 instruction set support.
@item alderlake
Intel Alderlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, CLDEMOTE,
-PTWRITE, WAITPKG and SERIALIZE instruction set support.
+PTWRITE, WAITPKG, SERIALIZE, KEYLOCKER and HRESET instruction set support.
@item k6
AMD K6 CPU with MMX instruction set support.
--
2.17.1
[-- Attachment #2: 0001-Enable-MOVDIRI-MOVDIR64B-CLDEMOTE-and-WAITPKG-for-ma.patch --]
[-- Type: application/octet-stream, Size: 11431 bytes --]
From 433b7c50e64b31725f818c5ef1d90825bc773976 Mon Sep 17 00:00:00 2001
From: "Cui,Lili" <lili.cui@intel.com>
Date: Wed, 4 Nov 2020 14:20:31 +0800
Subject: [PATCH] Enable MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for
march=tremont
1. Enable MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for march=tremont
2. Move PREFETCHW from march=broadwell to march=silvermont.
3. Add PREFETCHWT1 to march=knl
gcc/ChangeLog:
PR target/97685
* config/i386/i386.h:
(PTA_BROADWELL): Delete PTA_PRFCHW.
(PTA_SILVERMONT): Add PTA_PRFCHW.
(PTA_KNL): Add PTA_PREFETCHWT1.
(PTA_TREMONT): Add PTA_MOVDIRI, PTA_MOVDIR64B, PTA_CLDEMOTE and PTA_WAITPKG.
* doc/invoke.texi: Delete PREFETCHW for broadwell, skylake, knl, knm,
skylake-avx512, cannonlake, icelake-client, icelake-server, cascadelake,
cooperlake, tigerlake and sapphirerapids.
Add PREFETCHW for silvermont, goldmont, goldmont-plus and tremont.
Add XSAVEC and XSAVES for goldmont, goldmont-plus and tremont.
Add MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for tremont.
Add KEYLOCKER and HREST for alderlake.
Add AMX-BF16, AMX-TILE, AMX-INT8 and UINTR for sapphirerapids.
Add KEYLOCKER for tigerlake.
---
gcc/config/i386/i386.h | 10 +++----
gcc/doc/invoke.texi | 59 +++++++++++++++++++++---------------------
2 files changed, 35 insertions(+), 34 deletions(-)
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index d0c157a9970..5e01fe6b841 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2515,8 +2515,7 @@ const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
| PTA_RDRND | PTA_F16C;
const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
| PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
-const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
- | PTA_RDSEED;
+const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_RDSEED;
const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES | PTA_CLFLUSHOPT
| PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
@@ -2541,16 +2540,17 @@ const wide_int_bitmask PTA_SAPPHIRERAPIDS = PTA_COOPERLAKE | PTA_MOVDIRI
const wide_int_bitmask PTA_ALDERLAKE = PTA_SKYLAKE | PTA_CLDEMOTE | PTA_PTWRITE
| PTA_WAITPKG | PTA_SERIALIZE | PTA_HRESET | PTA_KL | PTA_WIDEKL;
const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
- | PTA_AVX512F | PTA_AVX512CD;
+ | PTA_AVX512F | PTA_AVX512CD | PTA_PREFETCHWT1;
const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
-const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
+const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND
+ | PTA_PRFCHW;
const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_AES | PTA_SHA | PTA_XSAVE
| PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
| PTA_FSGSBASE;
const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
| PTA_SGX | PTA_PTWRITE;
const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
- | PTA_GFNI;
+ | PTA_GFNI | PTA_MOVDIRI | PTA_MOVDIR64B | PTA_CLDEMOTE | PTA_WAITPKG;
const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
| PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index d2a188d7c75..d01beb248e1 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -29528,14 +29528,14 @@ BMI, BMI2 and F16C instruction set support.
@item broadwell
Intel Broadwell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX and PREFETCHW instruction set support.
+SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2,
+F16C, RDSEED and ADCX instruction set support.
@item skylake
Intel Skylake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC and
-XSAVES instruction set support.
+BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC and XSAVES instruction set
+support.
@item bonnell
Intel Bonnell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
@@ -29543,52 +29543,53 @@ instruction set support.
@item silvermont
Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, POPCNT, AES, PCLMUL and RDRND instruction set support.
+SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL and RDRND instruction set support.
@item goldmont
Intel Goldmont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT and FSGSBASE
-instruction set support.
+SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES,
+XSAVEOPT and FSGSBASE instruction set support.
@item goldmont-plus
Intel Goldmont Plus CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
-SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE,
-PTWRITE, RDPID, SGX and UMIP instruction set support.
+SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,
+XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX and UMIP instruction set support.
@item tremont
Intel Tremont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, PTWRITE,
-RDPID, SGX, UMIP, GFNI-SSE, CLWB and ENCLV instruction set support.
+SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES,
+XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, UMIP, GFNI-SSE, CLWB, MOVDIRI,
+MOVDIR64B, CLDEMOTE and WAITPKG instruction set support.
@item knl
Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, AVX512F, AVX512PF, AVX512ER and
+BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHWT1, AVX512F, AVX512PF, AVX512ER and
AVX512CD instruction set support.
@item knm
Intel Knights Mill CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, AVX512F, AVX512PF, AVX512ER, AVX512CD,
+BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHWT1, AVX512F, AVX512PF, AVX512ER, AVX512CD,
AVX5124VNNIW, AVX5124FMAPS and AVX512VPOPCNTDQ instruction set support.
@item skylake-avx512
Intel Skylake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
+BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
CLWB, AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support.
@item cannonlake
Intel Cannonlake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
-RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
+RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC,
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
AVX512IFMA, SHA and UMIP instruction set support.
@item icelake-client
Intel Icelake Client CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
-RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
+RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC,
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
@@ -29596,7 +29597,7 @@ AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
@item icelake-server
Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
-RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
+RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC,
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES, PCONFIG and WBNOINVD instruction
@@ -29605,37 +29606,37 @@ set support.
@item cascadelake
Intel Cascadelake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
-BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
+BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
AVX512VL, AVX512BW, AVX512DQ, AVX512CD and AVX512VNNI instruction set support.
@item cooperlake
Intel cooperlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
-BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
+BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI and AVX512BF16 instruction
set support.
@item tigerlake
Intel Tigerlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
-BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
-AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP,
-RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ,
-VAES, PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B and AVX512VP2INTERSECT instruction
-set support.
+BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, AVX512VL,
+AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP, RDPID,
+GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES,
+PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT and KEYLOCKER
+instruction set support.
@item sapphirerapids
Intel sapphirerapids CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND,
-FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES,
-AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI, AVX512BF16,
-MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG,
-SERIALIZE and TSXLDTRK instruction set support.
+FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
+AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI, AVX512BF16, MOVDIRI,
+MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE,
+TSXLDTRK, UINTR, AMX-BF16, AMX-TILE and AMX-INT8 instruction set support.
@item alderlake
Intel Alderlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, CLDEMOTE,
-PTWRITE, WAITPKG and SERIALIZE instruction set support.
+PTWRITE, WAITPKG, SERIALIZE, KEYLOCKER and HRESET instruction set support.
@item k6
AMD K6 CPU with MMX instruction set support.
--
2.17.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: Enable MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for march=tremont
2020-11-09 8:49 Enable MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for march=tremont Cui, Lili
@ 2020-11-09 9:03 ` Uros Bizjak
2020-11-09 19:21 ` Jason Merrill
2020-11-13 9:18 ` Cui, Lili
0 siblings, 2 replies; 8+ messages in thread
From: Uros Bizjak @ 2020-11-09 9:03 UTC (permalink / raw)
To: Cui, Lili; +Cc: GCC Patches
On Mon, Nov 9, 2020 at 9:50 AM Cui, Lili <lili.cui@intel.com> wrote:
>
> Hi Uros,
>
> This patch is to correct some instruction sets for march=Tremont/Broadwell/Silvermont/knl
>
> Bootstrap is ok, and no regressions for i386/x86-64 testsuite.
>
> OK for master?
>
> [PATCH] Enable MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for
> march=tremont
>
> 1. Enable MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for march=tremont
> 2. Move PREFETCHW from march=broadwell to march=silvermont.
> 3. Add PREFETCHWT1 to march=knl
>
> gcc/ChangeLog:
>
> PR target/97685
> * config/i386/i386.h:
> (PTA_BROADWELL): Delete PTA_PRFCHW.
> (PTA_SILVERMONT): Add PTA_PRFCHW.
> (PTA_KNL): Add PTA_PREFETCHWT1.
> (PTA_TREMONT): Add PTA_MOVDIRI, PTA_MOVDIR64B, PTA_CLDEMOTE and PTA_WAITPKG.
> * doc/invoke.texi: Delete PREFETCHW for broadwell, skylake, knl, knm,
> skylake-avx512, cannonlake, icelake-client, icelake-server, cascadelake,
> cooperlake, tigerlake and sapphirerapids.
> Add PREFETCHW for silvermont, goldmont, goldmont-plus and tremont.
> Add XSAVEC and XSAVES for goldmont, goldmont-plus and tremont.
> Add MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for tremont.
> Add KEYLOCKER and HREST for alderlake.
> Add AMX-BF16, AMX-TILE, AMX-INT8 and UINTR for sapphirerapids.
> Add KEYLOCKER for tigerlake.
OK.
Thanks,
Uros.
> ---
> gcc/config/i386/i386.h | 10 +++----
> gcc/doc/invoke.texi | 59 +++++++++++++++++++++---------------------
> 2 files changed, 35 insertions(+), 34 deletions(-)
>
> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> index d0c157a9970..5e01fe6b841 100644
> --- a/gcc/config/i386/i386.h
> +++ b/gcc/config/i386/i386.h
> @@ -2515,8 +2515,7 @@ const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
> | PTA_RDRND | PTA_F16C;
> const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
> | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
> -const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
> - | PTA_RDSEED;
> +const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_RDSEED;
> const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES | PTA_CLFLUSHOPT
> | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
> const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
> @@ -2541,16 +2540,17 @@ const wide_int_bitmask PTA_SAPPHIRERAPIDS = PTA_COOPERLAKE | PTA_MOVDIRI
> const wide_int_bitmask PTA_ALDERLAKE = PTA_SKYLAKE | PTA_CLDEMOTE | PTA_PTWRITE
> | PTA_WAITPKG | PTA_SERIALIZE | PTA_HRESET | PTA_KL | PTA_WIDEKL;
> const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
> - | PTA_AVX512F | PTA_AVX512CD;
> + | PTA_AVX512F | PTA_AVX512CD | PTA_PREFETCHWT1;
> const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
> -const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
> +const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND
> + | PTA_PRFCHW;
> const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_AES | PTA_SHA | PTA_XSAVE
> | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
> | PTA_FSGSBASE;
> const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
> | PTA_SGX | PTA_PTWRITE;
> const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
> - | PTA_GFNI;
> + | PTA_GFNI | PTA_MOVDIRI | PTA_MOVDIR64B | PTA_CLDEMOTE | PTA_WAITPKG;
> const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
> | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
>
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index d2a188d7c75..d01beb248e1 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -29528,14 +29528,14 @@ BMI, BMI2 and F16C instruction set support.
>
> @item broadwell
> Intel Broadwell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
> -SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
> -BMI, BMI2, F16C, RDSEED, ADCX and PREFETCHW instruction set support.
> +SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2,
> +F16C, RDSEED and ADCX instruction set support.
>
> @item skylake
> Intel Skylake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
> SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
> -BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC and
> -XSAVES instruction set support.
> +BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC and XSAVES instruction set
> +support.
>
> @item bonnell
> Intel Bonnell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
> @@ -29543,52 +29543,53 @@ instruction set support.
>
> @item silvermont
> Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
> -SSE4.1, SSE4.2, POPCNT, AES, PCLMUL and RDRND instruction set support.
> +SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL and RDRND instruction set support.
>
> @item goldmont
> Intel Goldmont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
> -SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT and FSGSBASE
> -instruction set support.
> +SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES,
> +XSAVEOPT and FSGSBASE instruction set support.
>
> @item goldmont-plus
> Intel Goldmont Plus CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
> -SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE,
> -PTWRITE, RDPID, SGX and UMIP instruction set support.
> +SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,
> +XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX and UMIP instruction set support.
>
> @item tremont
> Intel Tremont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
> -SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, PTWRITE,
> -RDPID, SGX, UMIP, GFNI-SSE, CLWB and ENCLV instruction set support.
> +SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES,
> +XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, UMIP, GFNI-SSE, CLWB, MOVDIRI,
> +MOVDIR64B, CLDEMOTE and WAITPKG instruction set support.
>
> @item knl
> Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
> SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
> -BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, AVX512F, AVX512PF, AVX512ER and
> +BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHWT1, AVX512F, AVX512PF, AVX512ER and
> AVX512CD instruction set support.
>
> @item knm
> Intel Knights Mill CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
> SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
> -BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, AVX512F, AVX512PF, AVX512ER, AVX512CD,
> +BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHWT1, AVX512F, AVX512PF, AVX512ER, AVX512CD,
> AVX5124VNNIW, AVX5124FMAPS and AVX512VPOPCNTDQ instruction set support.
>
> @item skylake-avx512
> Intel Skylake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
> SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
> -BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
> +BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
> CLWB, AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support.
>
> @item cannonlake
> Intel Cannonlake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
> -RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
> +RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC,
> XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
> AVX512IFMA, SHA and UMIP instruction set support.
>
> @item icelake-client
> Intel Icelake Client CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
> -RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
> +RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC,
> XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
> AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
> AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
> @@ -29596,7 +29597,7 @@ AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
> @item icelake-server
> Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
> -RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
> +RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC,
> XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
> AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
> AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES, PCONFIG and WBNOINVD instruction
> @@ -29605,37 +29606,37 @@ set support.
> @item cascadelake
> Intel Cascadelake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
> SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
> -BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
> +BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
> AVX512VL, AVX512BW, AVX512DQ, AVX512CD and AVX512VNNI instruction set support.
>
> @item cooperlake
> Intel cooperlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
> SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
> -BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
> +BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
> AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI and AVX512BF16 instruction
> set support.
>
> @item tigerlake
> Intel Tigerlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
> SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
> -BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
> -AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP,
> -RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ,
> -VAES, PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B and AVX512VP2INTERSECT instruction
> -set support.
> +BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, AVX512VL,
> +AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP, RDPID,
> +GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES,
> +PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT and KEYLOCKER
> +instruction set support.
>
> @item sapphirerapids
> Intel sapphirerapids CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
> SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND,
> -FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES,
> -AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI, AVX512BF16,
> -MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG,
> -SERIALIZE and TSXLDTRK instruction set support.
> +FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
> +AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI, AVX512BF16, MOVDIRI,
> +MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE,
> +TSXLDTRK, UINTR, AMX-BF16, AMX-TILE and AMX-INT8 instruction set support.
>
> @item alderlake
> Intel Alderlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
> SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, CLDEMOTE,
> -PTWRITE, WAITPKG and SERIALIZE instruction set support.
> +PTWRITE, WAITPKG, SERIALIZE, KEYLOCKER and HRESET instruction set support.
>
> @item k6
> AMD K6 CPU with MMX instruction set support.
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: Enable MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for march=tremont
2020-11-09 9:03 ` Uros Bizjak
@ 2020-11-09 19:21 ` Jason Merrill
2020-11-10 8:17 ` Hongtao Liu
2020-11-13 9:18 ` Cui, Lili
1 sibling, 1 reply; 8+ messages in thread
From: Jason Merrill @ 2020-11-09 19:21 UTC (permalink / raw)
To: Uros Bizjak; +Cc: Cui, Lili, GCC Patches
This patch was also applied to the GCC 9 and 10 branches and breaks those
builds, because PTA_CLDEMOTE is not defined.
On Mon, Nov 9, 2020 at 4:03 AM Uros Bizjak via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> On Mon, Nov 9, 2020 at 9:50 AM Cui, Lili <lili.cui@intel.com> wrote:
> >
> > Hi Uros,
> >
> > This patch is to correct some instruction sets for
> march=Tremont/Broadwell/Silvermont/knl
> >
> > Bootstrap is ok, and no regressions for i386/x86-64 testsuite.
> >
> > OK for master?
> >
> > [PATCH] Enable MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for
> > march=tremont
> >
> > 1. Enable MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for march=tremont
> > 2. Move PREFETCHW from march=broadwell to march=silvermont.
> > 3. Add PREFETCHWT1 to march=knl
> >
> > gcc/ChangeLog:
> >
> > PR target/97685
> > * config/i386/i386.h:
> > (PTA_BROADWELL): Delete PTA_PRFCHW.
> > (PTA_SILVERMONT): Add PTA_PRFCHW.
> > (PTA_KNL): Add PTA_PREFETCHWT1.
> > (PTA_TREMONT): Add PTA_MOVDIRI, PTA_MOVDIR64B, PTA_CLDEMOTE and
> PTA_WAITPKG.
> > * doc/invoke.texi: Delete PREFETCHW for broadwell, skylake, knl,
> knm,
> > skylake-avx512, cannonlake, icelake-client, icelake-server,
> cascadelake,
> > cooperlake, tigerlake and sapphirerapids.
> > Add PREFETCHW for silvermont, goldmont, goldmont-plus and
> tremont.
> > Add XSAVEC and XSAVES for goldmont, goldmont-plus and tremont.
> > Add MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for tremont.
> > Add KEYLOCKER and HREST for alderlake.
> > Add AMX-BF16, AMX-TILE, AMX-INT8 and UINTR for sapphirerapids.
> > Add KEYLOCKER for tigerlake.
>
> OK.
>
> Thanks,
> Uros.
>
> > ---
> > gcc/config/i386/i386.h | 10 +++----
> > gcc/doc/invoke.texi | 59 +++++++++++++++++++++---------------------
> > 2 files changed, 35 insertions(+), 34 deletions(-)
> >
> > diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> > index d0c157a9970..5e01fe6b841 100644
> > --- a/gcc/config/i386/i386.h
> > +++ b/gcc/config/i386/i386.h
> > @@ -2515,8 +2515,7 @@ const wide_int_bitmask PTA_IVYBRIDGE =
> PTA_SANDYBRIDGE | PTA_FSGSBASE
> > | PTA_RDRND | PTA_F16C;
> > const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
> > | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
> > -const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX |
> PTA_PRFCHW
> > - | PTA_RDSEED;
> > +const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX |
> PTA_RDSEED;
> > const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES |
> PTA_CLFLUSHOPT
> > | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
> > const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
> > @@ -2541,16 +2540,17 @@ const wide_int_bitmask PTA_SAPPHIRERAPIDS =
> PTA_COOPERLAKE | PTA_MOVDIRI
> > const wide_int_bitmask PTA_ALDERLAKE = PTA_SKYLAKE | PTA_CLDEMOTE |
> PTA_PTWRITE
> > | PTA_WAITPKG | PTA_SERIALIZE | PTA_HRESET | PTA_KL | PTA_WIDEKL;
> > const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF |
> PTA_AVX512ER
> > - | PTA_AVX512F | PTA_AVX512CD;
> > + | PTA_AVX512F | PTA_AVX512CD | PTA_PREFETCHWT1;
> > const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
> > -const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE |
> PTA_RDRND;
> > +const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE |
> PTA_RDRND
> > + | PTA_PRFCHW;
> > const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_AES |
> PTA_SHA | PTA_XSAVE
> > | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
> > | PTA_FSGSBASE;
> > const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
> > | PTA_SGX | PTA_PTWRITE;
> > const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
> > - | PTA_GFNI;
> > + | PTA_GFNI | PTA_MOVDIRI | PTA_MOVDIR64B | PTA_CLDEMOTE | PTA_WAITPKG;
> > const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
> > | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
> >
> > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> > index d2a188d7c75..d01beb248e1 100644
> > --- a/gcc/doc/invoke.texi
> > +++ b/gcc/doc/invoke.texi
> > @@ -29528,14 +29528,14 @@ BMI, BMI2 and F16C instruction set support.
> >
> > @item broadwell
> > Intel Broadwell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> SSE3, SSSE3,
> > -SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
> > -BMI, BMI2, F16C, RDSEED, ADCX and PREFETCHW instruction set support.
> > +SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
> BMI, BMI2,
> > +F16C, RDSEED and ADCX instruction set support.
> >
> > @item skylake
> > Intel Skylake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
> SSSE3,
> > SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
> > -BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC and
> > -XSAVES instruction set support.
> > +BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC and XSAVES
> instruction set
> > +support.
> >
> > @item bonnell
> > Intel Bonnell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3
> and SSSE3
> > @@ -29543,52 +29543,53 @@ instruction set support.
> >
> > @item silvermont
> > Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> SSE3, SSSE3,
> > -SSE4.1, SSE4.2, POPCNT, AES, PCLMUL and RDRND instruction set support.
> > +SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL and RDRND instruction
> set support.
> >
> > @item goldmont
> > Intel Goldmont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
> SSSE3,
> > -SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT and FSGSBASE
> > -instruction set support.
> > +SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,
> XSAVES,
> > +XSAVEOPT and FSGSBASE instruction set support.
> >
> > @item goldmont-plus
> > Intel Goldmont Plus CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> SSE3,
> > -SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT,
> FSGSBASE,
> > -PTWRITE, RDPID, SGX and UMIP instruction set support.
> > +SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE,
> XSAVEC,
> > +XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX and UMIP instruction
> set support.
> >
> > @item tremont
> > Intel Tremont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
> SSSE3,
> > -SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE,
> PTWRITE,
> > -RDPID, SGX, UMIP, GFNI-SSE, CLWB and ENCLV instruction set support.
> > +SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,
> XSAVES,
> > +XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, UMIP, GFNI-SSE, CLWB, MOVDIRI,
> > +MOVDIR64B, CLDEMOTE and WAITPKG instruction set support.
> >
> > @item knl
> > Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE,
> SSE2, SSE3,
> > SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND,
> FMA,
> > -BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, AVX512F, AVX512PF, AVX512ER
> and
> > +BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHWT1, AVX512F, AVX512PF, AVX512ER
> and
> > AVX512CD instruction set support.
> >
> > @item knm
> > Intel Knights Mill CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> SSE3,
> > SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND,
> FMA,
> > -BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, AVX512F, AVX512PF, AVX512ER,
> AVX512CD,
> > +BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHWT1, AVX512F, AVX512PF,
> AVX512ER, AVX512CD,
> > AVX5124VNNIW, AVX5124FMAPS and AVX512VPOPCNTDQ instruction set support.
> >
> > @item skylake-avx512
> > Intel Skylake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> SSE3,
> > SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
> RDRND, FMA,
> > -BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES,
> AVX512F,
> > +BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
> > CLWB, AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support.
> >
> > @item cannonlake
> > Intel Cannonlake Server CPU with 64-bit extensions, MOVBE, MMX, SSE,
> SSE2,
> > SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL,
> FSGSBASE,
> > -RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT,
> XSAVEC,
> > +RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC,
> > XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
> > AVX512IFMA, SHA and UMIP instruction set support.
> >
> > @item icelake-client
> > Intel Icelake Client CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> > SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL,
> FSGSBASE,
> > -RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT,
> XSAVEC,
> > +RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC,
> > XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
> > AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
> > AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
> > @@ -29596,7 +29597,7 @@ AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES
> instruction set support.
> > @item icelake-server
> > Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> > SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL,
> FSGSBASE,
> > -RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT,
> XSAVEC,
> > +RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC,
> > XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
> > AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
> > AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES, PCONFIG and WBNOINVD
> instruction
> > @@ -29605,37 +29606,37 @@ set support.
> > @item cascadelake
> > Intel Cascadelake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> SSE3, SSSE3,
> > SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND,
> FMA, BMI,
> > -BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES,
> AVX512F, CLWB,
> > +BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
> > AVX512VL, AVX512BW, AVX512DQ, AVX512CD and AVX512VNNI instruction set
> support.
> >
> > @item cooperlake
> > Intel cooperlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> SSE3, SSSE3,
> > SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND,
> FMA, BMI,
> > -BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES,
> AVX512F, CLWB,
> > +BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
> > AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI and AVX512BF16
> instruction
> > set support.
> >
> > @item tigerlake
> > Intel Tigerlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> SSE3, SSSE3,
> > SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND,
> FMA, BMI,
> > -BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES,
> AVX512F,
> > -AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA,
> CLWB, UMIP,
> > -RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI,
> VPCLMULQDQ,
> > -VAES, PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B and AVX512VP2INTERSECT
> instruction
> > -set support.
> > +BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, AVX512VL,
> > +AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP,
> RDPID,
> > +GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI,
> VPCLMULQDQ, VAES,
> > +PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT and KEYLOCKER
> > +instruction set support.
> >
> > @item sapphirerapids
> > Intel sapphirerapids CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> SSE3,
> > SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
> RDRND,
> > -FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
> XSAVES,
> > -AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI,
> AVX512BF16,
> > -MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE,
> WAITPKG,
> > -SERIALIZE and TSXLDTRK instruction set support.
> > +FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES,
> AVX512F, CLWB,
> > +AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI, AVX512BF16, MOVDIRI,
> > +MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG,
> SERIALIZE,
> > +TSXLDTRK, UINTR, AMX-BF16, AMX-TILE and AMX-INT8 instruction set
> support.
> >
> > @item alderlake
> > Intel Alderlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> SSE3, SSSE3,
> > SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
> CLDEMOTE,
> > -PTWRITE, WAITPKG and SERIALIZE instruction set support.
> > +PTWRITE, WAITPKG, SERIALIZE, KEYLOCKER and HRESET instruction set
> support.
> >
> > @item k6
> > AMD K6 CPU with MMX instruction set support.
> > --
> > 2.17.1
> >
>
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: Enable MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for march=tremont
2020-11-09 19:21 ` Jason Merrill
@ 2020-11-10 8:17 ` Hongtao Liu
2020-11-10 12:03 ` Hongtao Liu
0 siblings, 1 reply; 8+ messages in thread
From: Hongtao Liu @ 2020-11-10 8:17 UTC (permalink / raw)
To: Jason Merrill; +Cc: Uros Bizjak, GCC Patches
On Tue, Nov 10, 2020 at 3:22 AM Jason Merrill via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> This patch was also applied to the GCC 9 and 10 branches and breaks those
> builds, because PTA_CLDEMOTE is not defined.
>
Mine, let me fix it, sorry for that.
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: Enable MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for march=tremont
2020-11-10 8:17 ` Hongtao Liu
@ 2020-11-10 12:03 ` Hongtao Liu
2020-11-10 12:23 ` Jakub Jelinek
0 siblings, 1 reply; 8+ messages in thread
From: Hongtao Liu @ 2020-11-10 12:03 UTC (permalink / raw)
To: Jason Merrill; +Cc: Uros Bizjak, GCC Patches
[-- Attachment #1: Type: text/plain, Size: 1083 bytes --]
On Tue, Nov 10, 2020 at 4:17 PM Hongtao Liu <crazylht@gmail.com> wrote:
>
> On Tue, Nov 10, 2020 at 3:22 AM Jason Merrill via Gcc-patches
> <gcc-patches@gcc.gnu.org> wrote:
> >
> > This patch was also applied to the GCC 9 and 10 branches and breaks those
> > builds, because PTA_CLDEMOTE is not defined.
> >
> Mine, let me fix it, sorry for that.
>
Since CLDEMOTE already existed in gcc9 and later, define PTA_CLDEMOTE
instead of removing it.
Similar for MOVDIRI, MOVDIR64B.
GCC10-Fix.patch
gcc/ChangeLog
* config/i386/i386-options.c (ix86_option_override_internal):
Handle PTA_CLDEMOTE.
* config/i386/i386.h (PTA_CLDEMOTE): Define.
GCC9-Fix.patch
gcc/ChangeLog
* config/i386/i386.c (ix86_option_override_internal):
Handle PTA_CLDEMOTE, PTA_MOVDIRI, PTA_MOVDIR64B.
* config/i386/i386.h (PTA_CLDEMOTE, PTA_MOVDIRI,
PTA_MOVDIR64B.): Define.
Bootstrap and regression test for i386 backend is ok on releases/gcc-9
and releases/gcc-10 branch.
Sorry for such unnecessary inconvenience.
> --
> BR,
> Hongtao
--
BR,
Hongtao
[-- Attachment #2: GCC10-Fix.patch --]
[-- Type: text/x-patch, Size: 1840 bytes --]
From 7744c0f741e26123e63a90494efd4a6c989df7c6 Mon Sep 17 00:00:00 2001
From: liuhongt <hongtao.liu@intel.com>
Date: Tue, 10 Nov 2020 16:42:06 +0800
Subject: [PATCH] Fix missing defination of PTA_CLDEMOTE.
gcc/ChangeLog
* config/i386/i386-options.c (ix86_option_override_internal):
Handle PTA_CLDEMOTE.
* config/i386/i386.h (PTA_CLDEMOTE): Define.
---
gcc/config/i386/i386-options.c | 3 +++
gcc/config/i386/i386.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c
index 5c21fce06a4..14a57a17156 100644
--- a/gcc/config/i386/i386-options.c
+++ b/gcc/config/i386/i386-options.c
@@ -2226,6 +2226,9 @@ ix86_option_override_internal (bool main_args_p,
if (((processor_alias_table[i].flags & PTA_PTWRITE) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_PTWRITE))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PTWRITE;
+ if (((processor_alias_table[i].flags & PTA_CLDEMOTE) != 0)
+ && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_CLDEMOTE))
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLDEMOTE;
if ((processor_alias_table[i].flags
& (PTA_PREFETCH_SSE | PTA_SSE)) != 0)
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index d75a86bb8da..08f265fc8e0 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2437,6 +2437,7 @@ const wide_int_bitmask PTA_AVX512BF16 (0, HOST_WIDE_INT_1U << 11);
const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 12);
const wide_int_bitmask PTA_MOVDIRI(0, HOST_WIDE_INT_1U << 13);
const wide_int_bitmask PTA_MOVDIR64B(0, HOST_WIDE_INT_1U << 14);
+const wide_int_bitmask PTA_CLDEMOTE(0, HOST_WIDE_INT_1U << 16);
const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
| PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
--
2.18.1
[-- Attachment #3: GCC9-Fix.patch --]
[-- Type: text/x-patch, Size: 2383 bytes --]
From a1b774edeedadf69c56529fa52a9e2ef92cb7957 Mon Sep 17 00:00:00 2001
From: liuhongt <hongtao.liu@intel.com>
Date: Tue, 10 Nov 2020 16:48:08 +0800
Subject: [PATCH] Fix missing defination of PTA_CLDEMOTE, PTA_MOVDIRI,
PTA_MOVDIR64B.
gcc/ChangeLog
* config/i386/i386.c (ix86_option_override_internal):
Handle PTA_CLDEMOTE, PTA_MOVDIRI, PTA_MOVDIR64B.
* config/i386/i386.h (PTA_CLDEMOTE, PTA_MOVDIRI,
PTA_MOVDIR64B.): Define.
---
gcc/config/i386/i386.c | 9 +++++++++
gcc/config/i386/i386.h | 3 +++
2 files changed, 12 insertions(+)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index f968d033972..bd61be61fdf 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -4058,6 +4058,15 @@ ix86_option_override_internal (bool main_args_p,
if (((processor_alias_table[i].flags & PTA_PTWRITE) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_PTWRITE))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_PTWRITE;
+ if (((processor_alias_table[i].flags & PTA_MOVDIRI) != 0)
+ && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_MOVDIRI))
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI;
+ if (((processor_alias_table[i].flags & PTA_MOVDIR64B) != 0)
+ && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MOVDIR64B))
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVDIR64B;
+ if (((processor_alias_table[i].flags & PTA_CLDEMOTE) != 0)
+ && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_CLDEMOTE))
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLDEMOTE;
if ((processor_alias_table[i].flags
& (PTA_PREFETCH_SSE | PTA_SSE)) != 0)
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 17d6218e991..1cc9e3d9463 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2379,6 +2379,9 @@ const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7);
const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8);
const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
const wide_int_bitmask PTA_PTWRITE (0, HOST_WIDE_INT_1U << 10);
+const wide_int_bitmask PTA_MOVDIRI(0, HOST_WIDE_INT_1U << 13);
+const wide_int_bitmask PTA_MOVDIR64B(0, HOST_WIDE_INT_1U << 14);
+const wide_int_bitmask PTA_CLDEMOTE (0, HOST_WIDE_INT_1U << 16);
const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
| PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
--
2.18.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: Enable MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for march=tremont
2020-11-10 12:03 ` Hongtao Liu
@ 2020-11-10 12:23 ` Jakub Jelinek
0 siblings, 0 replies; 8+ messages in thread
From: Jakub Jelinek @ 2020-11-10 12:23 UTC (permalink / raw)
To: Hongtao Liu; +Cc: Jason Merrill, GCC Patches, Uros Bizjak
On Tue, Nov 10, 2020 at 08:03:29PM +0800, Hongtao Liu via Gcc-patches wrote:
> --- a/gcc/config/i386/i386.h
> +++ b/gcc/config/i386/i386.h
> @@ -2437,6 +2437,7 @@ const wide_int_bitmask PTA_AVX512BF16 (0, HOST_WIDE_INT_1U << 11);
> const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 12);
> const wide_int_bitmask PTA_MOVDIRI(0, HOST_WIDE_INT_1U << 13);
> const wide_int_bitmask PTA_MOVDIR64B(0, HOST_WIDE_INT_1U << 14);
> +const wide_int_bitmask PTA_CLDEMOTE(0, HOST_WIDE_INT_1U << 16);
Formatting, there should be a space between PTA_* and (.
Please fix this up on both branches not just for the entries you've added
but also for the older ones, and please fix it on the trunk too:
const wide_int_bitmask PTA_MOVDIRI(0, HOST_WIDE_INT_1U << 13);
const wide_int_bitmask PTA_MOVDIR64B(0, HOST_WIDE_INT_1U << 14);
...
const wide_int_bitmask PTA_AMX_TILE(0, HOST_WIDE_INT_1U << 19);
const wide_int_bitmask PTA_AMX_INT8(0, HOST_WIDE_INT_1U << 20);
const wide_int_bitmask PTA_AMX_BF16(0, HOST_WIDE_INT_1U << 21);
...
const wide_int_bitmask PTA_HRESET(0, HOST_WIDE_INT_1U << 23);
on the trunk suffer from this.
Ok for branches and the above change to trunk is preapproved too,
but please bootstrap/regtest all backports next time.
Jakub
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: Enable MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for march=tremont
2020-11-09 9:03 ` Uros Bizjak
2020-11-09 19:21 ` Jason Merrill
@ 2020-11-13 9:18 ` Cui, Lili
2020-11-13 10:00 ` Uros Bizjak
1 sibling, 1 reply; 8+ messages in thread
From: Cui, Lili @ 2020-11-13 9:18 UTC (permalink / raw)
To: Uros Bizjak; +Cc: GCC Patches
[-- Attachment #1: Type: text/plain, Size: 8755 bytes --]
Hi Uros,
This patch is to correct previous patch,
PREFETCHW should be both in march=broadwell and march=Silvermont,
but I move PREFETCHW from march=broadwell to march=silvermont in previous
patch, sorry for that.
Bootstrap is ok, and no regressions for i386/x86-64 testsuite.
OK for master?
[PATCH] Put PREFETCHW back to march=broadwell
PREFETCHW should be both in march=broadwell and march=silvermont.
I move PREFETCHW from march=broadwell to march=silvermont in previous
patch.
gcc/ChangeLog:
* config/i386/i386.h: Add PREFETCHW to march=broadwell.
* doc/invoke.texi: Put PREFETCHW back to relation arch.
---
gcc/config/i386/i386.h | 3 ++-
gcc/doc/invoke.texi | 50 +++++++++++++++++++++++-------------------
2 files changed, 29 insertions(+), 24 deletions(-)
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 3be7551d6c3..b8ae16e2865 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2518,7 +2518,8 @@ const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
| PTA_RDRND | PTA_F16C;
const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
| PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
-const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_RDSEED;
+const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_RDSEED
+ | PTA_PRFCHW;
const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES | PTA_CLFLUSHOPT
| PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 69bf1fa89dd..3c292593030 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -29560,13 +29560,13 @@ BMI, BMI2 and F16C instruction set support.
@item broadwell
Intel Broadwell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2,
-F16C, RDSEED and ADCX instruction set support.
+F16C, RDSEED ADCX and PREFETCHW instruction set support.
@item skylake
Intel Skylake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC and XSAVES instruction set
-support.
+BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC and XSAVES
+instruction set support.
@item bonnell
Intel Bonnell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
@@ -29595,32 +29595,33 @@ MOVDIR64B, CLDEMOTE and WAITPKG instruction set support.
@item knl
Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHWT1, AVX512F, AVX512PF, AVX512ER and
-AVX512CD instruction set support.
+BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, PREFETCHWT1, AVX512F, AVX512PF,
+AVX512ER and AVX512CD instruction set support.
@item knm
Intel Knights Mill CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHWT1, AVX512F, AVX512PF, AVX512ER, AVX512CD,
-AVX5124VNNIW, AVX5124FMAPS and AVX512VPOPCNTDQ instruction set support.
+BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, PREFETCHWT1, AVX512F, AVX512PF,
+AVX512ER, AVX512CD, AVX5124VNNIW, AVX5124FMAPS and AVX512VPOPCNTDQ instruction
+set support.
@item skylake-avx512
Intel Skylake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
+BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
CLWB, AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support.
@item cannonlake
Intel Cannonlake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
-RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC,
+RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
AVX512IFMA, SHA and UMIP instruction set support.
@item icelake-client
Intel Icelake Client CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
-RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC,
+RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
@@ -29628,7 +29629,7 @@ AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
@item icelake-server
Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
-RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC,
+RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES, PCONFIG and WBNOINVD instruction
@@ -29637,37 +29638,40 @@ set support.
@item cascadelake
Intel Cascadelake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
-BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
+BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
AVX512VL, AVX512BW, AVX512DQ, AVX512CD and AVX512VNNI instruction set support.
@item cooperlake
Intel cooperlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
-BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
+BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI and AVX512BF16 instruction
set support.
@item tigerlake
Intel Tigerlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
-BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, AVX512VL,
-AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP, RDPID,
-GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES,
-PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT and KEYLOCKER
+BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
+AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP,
+RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ,
+VAES, PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT and KEYLOCKER
instruction set support.
@item sapphirerapids
Intel sapphirerapids CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND,
-FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
-AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI, AVX512BF16, MOVDIRI,
-MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE,
-TSXLDTRK, UINTR, AMX-BF16, AMX-TILE and AMX-INT8 instruction set support.
+FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES,
+AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI, AVX512BF16,
+MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG,
+SERIALIZE, TSXLDTRK, UINTR, AMX-BF16, AMX-TILE, AMX-INT8 and AVX-VNNI
+instruction set support.
@item alderlake
Intel Alderlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, CLDEMOTE,
-PTWRITE, WAITPKG, SERIALIZE, KEYLOCKER and HRESET instruction set support.
+SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
+BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, CLDEMOTE,
+PTWRITE, WAITPKG, SERIALIZE, KEYLOCKER, HRESET and AVX-VNNI instruction set
+support.
@item k6
AMD K6 CPU with MMX instruction set support.
--
2.17.1
Thanks,
Lili.
[-- Attachment #2: 0001-Put-PREFETCHW-back-to-march-broadwell.patch --]
[-- Type: application/octet-stream, Size: 8428 bytes --]
From dbe2edb0b26abe92c050cbdf48b711c8fd3d2ad5 Mon Sep 17 00:00:00 2001
From: "Cui,Lili" <lili.cui@intel.com>
Date: Fri, 13 Nov 2020 14:20:31 +0800
Subject: [PATCH] Put PREFETCHW back to march=broadwell
PREFETCHW should be both in march=broadwell and march=silvermont.
I move PREFETCHW from march=broadwell to march=silvermont in previous
patch.
gcc/ChangeLog:
* config/i386/i386.h: Add PREFETCHW to march=broadwell.
* doc/invoke.texi: Put PREFETCHW back to relation arch.
---
gcc/config/i386/i386.h | 3 ++-
gcc/doc/invoke.texi | 50 +++++++++++++++++++++++-------------------
2 files changed, 29 insertions(+), 24 deletions(-)
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 3be7551d6c3..b8ae16e2865 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2518,7 +2518,8 @@ const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
| PTA_RDRND | PTA_F16C;
const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
| PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
-const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_RDSEED;
+const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_RDSEED
+ | PTA_PRFCHW;
const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES | PTA_CLFLUSHOPT
| PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 69bf1fa89dd..3c292593030 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -29560,13 +29560,13 @@ BMI, BMI2 and F16C instruction set support.
@item broadwell
Intel Broadwell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2,
-F16C, RDSEED and ADCX instruction set support.
+F16C, RDSEED ADCX and PREFETCHW instruction set support.
@item skylake
Intel Skylake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC and XSAVES instruction set
-support.
+BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC and XSAVES
+instruction set support.
@item bonnell
Intel Bonnell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
@@ -29595,32 +29595,33 @@ MOVDIR64B, CLDEMOTE and WAITPKG instruction set support.
@item knl
Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHWT1, AVX512F, AVX512PF, AVX512ER and
-AVX512CD instruction set support.
+BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, PREFETCHWT1, AVX512F, AVX512PF,
+AVX512ER and AVX512CD instruction set support.
@item knm
Intel Knights Mill CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHWT1, AVX512F, AVX512PF, AVX512ER, AVX512CD,
-AVX5124VNNIW, AVX5124FMAPS and AVX512VPOPCNTDQ instruction set support.
+BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, PREFETCHWT1, AVX512F, AVX512PF,
+AVX512ER, AVX512CD, AVX5124VNNIW, AVX5124FMAPS and AVX512VPOPCNTDQ instruction
+set support.
@item skylake-avx512
Intel Skylake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
+BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
CLWB, AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support.
@item cannonlake
Intel Cannonlake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
-RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC,
+RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
AVX512IFMA, SHA and UMIP instruction set support.
@item icelake-client
Intel Icelake Client CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
-RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC,
+RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
@@ -29628,7 +29629,7 @@ AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
@item icelake-server
Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
-RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC,
+RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES, PCONFIG and WBNOINVD instruction
@@ -29637,37 +29638,40 @@ set support.
@item cascadelake
Intel Cascadelake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
-BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
+BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
AVX512VL, AVX512BW, AVX512DQ, AVX512CD and AVX512VNNI instruction set support.
@item cooperlake
Intel cooperlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
-BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
+BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI and AVX512BF16 instruction
set support.
@item tigerlake
Intel Tigerlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
-BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, AVX512VL,
-AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP, RDPID,
-GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES,
-PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT and KEYLOCKER
+BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
+AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP,
+RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ,
+VAES, PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT and KEYLOCKER
instruction set support.
@item sapphirerapids
Intel sapphirerapids CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND,
-FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
-AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI, AVX512BF16, MOVDIRI,
-MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE,
-TSXLDTRK, UINTR, AMX-BF16, AMX-TILE and AMX-INT8 instruction set support.
+FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES,
+AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI, AVX512BF16,
+MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG,
+SERIALIZE, TSXLDTRK, UINTR, AMX-BF16, AMX-TILE, AMX-INT8 and AVX-VNNI
+instruction set support.
@item alderlake
Intel Alderlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, CLDEMOTE,
-PTWRITE, WAITPKG, SERIALIZE, KEYLOCKER and HRESET instruction set support.
+SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
+BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, CLDEMOTE,
+PTWRITE, WAITPKG, SERIALIZE, KEYLOCKER, HRESET and AVX-VNNI instruction set
+support.
@item k6
AMD K6 CPU with MMX instruction set support.
--
2.17.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: Enable MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for march=tremont
2020-11-13 9:18 ` Cui, Lili
@ 2020-11-13 10:00 ` Uros Bizjak
0 siblings, 0 replies; 8+ messages in thread
From: Uros Bizjak @ 2020-11-13 10:00 UTC (permalink / raw)
To: Cui, Lili; +Cc: GCC Patches
On Fri, Nov 13, 2020 at 10:18 AM Cui, Lili <lili.cui@intel.com> wrote:
>
> Hi Uros,
>
> This patch is to correct previous patch,
> PREFETCHW should be both in march=broadwell and march=Silvermont,
> but I move PREFETCHW from march=broadwell to march=silvermont in previous
> patch, sorry for that.
>
> Bootstrap is ok, and no regressions for i386/x86-64 testsuite.
>
> OK for master?
>
>
> [PATCH] Put PREFETCHW back to march=broadwell
>
> PREFETCHW should be both in march=broadwell and march=silvermont.
> I move PREFETCHW from march=broadwell to march=silvermont in previous
> patch.
>
> gcc/ChangeLog:
>
> * config/i386/i386.h: Add PREFETCHW to march=broadwell.
> * doc/invoke.texi: Put PREFETCHW back to relation arch.
OK.
These kinds of changes can be considered under obvious rule.
Thanks,
Uros.
> ---
> gcc/config/i386/i386.h | 3 ++-
> gcc/doc/invoke.texi | 50 +++++++++++++++++++++++-------------------
> 2 files changed, 29 insertions(+), 24 deletions(-)
>
> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> index 3be7551d6c3..b8ae16e2865 100644
> --- a/gcc/config/i386/i386.h
> +++ b/gcc/config/i386/i386.h
> @@ -2518,7 +2518,8 @@ const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
> | PTA_RDRND | PTA_F16C;
> const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
> | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
> -const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_RDSEED;
> +const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_RDSEED
> + | PTA_PRFCHW;
> const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES | PTA_CLFLUSHOPT
> | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
> const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index 69bf1fa89dd..3c292593030 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -29560,13 +29560,13 @@ BMI, BMI2 and F16C instruction set support.
> @item broadwell
> Intel Broadwell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
> SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2,
> -F16C, RDSEED and ADCX instruction set support.
> +F16C, RDSEED ADCX and PREFETCHW instruction set support.
>
> @item skylake
> Intel Skylake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
> SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
> -BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC and XSAVES instruction set
> -support.
> +BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC and XSAVES
> +instruction set support.
>
> @item bonnell
> Intel Bonnell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
> @@ -29595,32 +29595,33 @@ MOVDIR64B, CLDEMOTE and WAITPKG instruction set support.
> @item knl
> Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
> SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
> -BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHWT1, AVX512F, AVX512PF, AVX512ER and
> -AVX512CD instruction set support.
> +BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, PREFETCHWT1, AVX512F, AVX512PF,
> +AVX512ER and AVX512CD instruction set support.
>
> @item knm
> Intel Knights Mill CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
> SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
> -BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHWT1, AVX512F, AVX512PF, AVX512ER, AVX512CD,
> -AVX5124VNNIW, AVX5124FMAPS and AVX512VPOPCNTDQ instruction set support.
> +BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, PREFETCHWT1, AVX512F, AVX512PF,
> +AVX512ER, AVX512CD, AVX5124VNNIW, AVX5124FMAPS and AVX512VPOPCNTDQ instruction
> +set support.
>
> @item skylake-avx512
> Intel Skylake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
> SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
> -BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
> +BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
> CLWB, AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support.
>
> @item cannonlake
> Intel Cannonlake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
> -RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC,
> +RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
> XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
> AVX512IFMA, SHA and UMIP instruction set support.
>
> @item icelake-client
> Intel Icelake Client CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
> -RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC,
> +RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
> XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
> AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
> AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
> @@ -29628,7 +29629,7 @@ AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
> @item icelake-server
> Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
> -RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC,
> +RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
> XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
> AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
> AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES, PCONFIG and WBNOINVD instruction
> @@ -29637,37 +29638,40 @@ set support.
> @item cascadelake
> Intel Cascadelake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
> SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
> -BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
> +BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
> AVX512VL, AVX512BW, AVX512DQ, AVX512CD and AVX512VNNI instruction set support.
>
> @item cooperlake
> Intel cooperlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
> SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
> -BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
> +BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
> AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI and AVX512BF16 instruction
> set support.
>
> @item tigerlake
> Intel Tigerlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
> SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
> -BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, AVX512VL,
> -AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP, RDPID,
> -GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES,
> -PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT and KEYLOCKER
> +BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
> +AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP,
> +RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ,
> +VAES, PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT and KEYLOCKER
> instruction set support.
>
> @item sapphirerapids
> Intel sapphirerapids CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
> SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND,
> -FMA, BMI, BMI2, F16C, RDSEED, ADCX, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
> -AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI, AVX512BF16, MOVDIRI,
> -MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE,
> -TSXLDTRK, UINTR, AMX-BF16, AMX-TILE and AMX-INT8 instruction set support.
> +FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES,
> +AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI, AVX512BF16,
> +MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG,
> +SERIALIZE, TSXLDTRK, UINTR, AMX-BF16, AMX-TILE, AMX-INT8 and AVX-VNNI
> +instruction set support.
>
> @item alderlake
> Intel Alderlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
> -SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, CLDEMOTE,
> -PTWRITE, WAITPKG, SERIALIZE, KEYLOCKER and HRESET instruction set support.
> +SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
> +BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, CLDEMOTE,
> +PTWRITE, WAITPKG, SERIALIZE, KEYLOCKER, HRESET and AVX-VNNI instruction set
> +support.
>
> @item k6
> AMD K6 CPU with MMX instruction set support.
> --
> 2.17.1
>
> Thanks,
> Lili.
>
^ permalink raw reply [flat|nested] 8+ messages in thread
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2020-11-09 8:49 Enable MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for march=tremont Cui, Lili
2020-11-09 9:03 ` Uros Bizjak
2020-11-09 19:21 ` Jason Merrill
2020-11-10 8:17 ` Hongtao Liu
2020-11-10 12:03 ` Hongtao Liu
2020-11-10 12:23 ` Jakub Jelinek
2020-11-13 9:18 ` Cui, Lili
2020-11-13 10:00 ` Uros Bizjak
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