From: Michael Meissner <meissner@linux.ibm.com>
To: Michael Meissner <meissner@linux.ibm.com>,
gcc-patches@gcc.gnu.org,
Segher Boessenkool <segher@kernel.crashing.org>,
David Edelsohn <dje.gcc@gmail.com>,
Bill Schmidt <wschmidt@linux.ibm.com>,
Peter Bergner <bergner@linux.ibm.com>
Subject: [PATCH 1/2] Power10: Add IEEE 128-bit xsmaxcqp and xsmincqp support.
Date: Sun, 15 Nov 2020 23:50:51 -0500 [thread overview]
Message-ID: <20201116045051.GA3952@ibm-toto.the-meissners.org> (raw)
In-Reply-To: <20201116044538.GA2478@ibm-toto.the-meissners.org>
Power10: Add IEEE 128-bit xsmaxcqp and xsmincqp support.
This patch adds the support for the IEEE 128-bit floating point C minimum and
maximum instructions. The next patch will add the support for using the
compare and set mask instruction to implement conditional moves.
Originally, I tried to add the min/max instructions via a super defination that
covers all of the types. In this patch, based on patch feedback, I rewrote the
patch to be simpler and just provide the new instructions as a separate insn.
I have built little endian power9 bootstrap compilers with these patches in it,
and there were no regressions. I have also build big endian power8 bootstrap
compilers, and there were no regressions. Can I check this into the master
branch?
gcc/
2020-11-15 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA
3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp instructions.
* config/rs6000/rs60000.h (FLOAT128_MIN_MAX_FPMASK_P): New macro.
* config/rs6000/rs6000.md (s<minmax><mode>3): Add support for the
ISA 3.1 IEEE 128-bit minimum and maximum instructions.
gcc/testsuite/
2020-11-15 Michael Meissner <meissner@linux.ibm.com>
* gcc.target/powerpc/float128-minmax-2.c: New test.
---
gcc/config/rs6000/rs6000.c | 3 ++-
gcc/config/rs6000/rs6000.h | 5 +++++
gcc/config/rs6000/rs6000.md | 11 +++++++++++
.../gcc.target/powerpc/float128-minmax-2.c | 15 +++++++++++++++
4 files changed, 33 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index d7dcd93f088..f6a1f63e842 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -15741,7 +15741,8 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
/* VSX/altivec have direct min/max insns. */
if ((code == SMAX || code == SMIN)
&& (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
- || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
+ || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))
+ || FLOAT128_MIN_MAX_FPMASK_P (mode)))
{
emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
return;
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 5a47aa14722..886559dbfdf 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -345,6 +345,11 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
|| ((MODE) == TDmode) \
|| (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)))
+/* Macro whether the float128 minimum, maximum, and set compare mask
+ instructions are enabled. */
+#define FLOAT128_MIN_MAX_FPMASK_P(MODE) \
+ (TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (MODE))
+
/* Return true for floating point that does not use a vector register. */
#define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \
(SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE))
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 5e5ad9f7c3d..d8fbac124fb 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5163,6 +5163,17 @@ (define_insn "*s<minmax><mode>3_vsx"
}
[(set_attr "type" "fp")])
+;; Min/max for ISA 3.1 IEEE 128-bit floating point
+(define_insn "s<minmax><mode>3"
+ [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
+ (fp_minmax:IEEE128
+ (match_operand:IEEE128 1 "altivec_register_operand" "v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
+ "TARGET_POWER10"
+ "xs<minmax>cqp %0,%1,%2"
+ [(set_attr "type" "vecfloat")
+ (set_attr "size" "128")])
+
;; The conditional move instructions allow us to perform max and min operations
;; even when we don't have the appropriate max/min instruction using the FSEL
;; instruction.
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
new file mode 100644
index 00000000000..c71ba08c9f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
@@ -0,0 +1,15 @@
+/* { dg-require-effective-target ppc_float128_hw } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2 -ffast-math" } */
+
+#ifndef TYPE
+#define TYPE _Float128
+#endif
+
+/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a
+ call. */
+TYPE f128_min (TYPE a, TYPE b) { return __builtin_fminf128 (a, b); }
+TYPE f128_max (TYPE a, TYPE b) { return __builtin_fmaxf128 (a, b); }
+
+/* { dg-final { scan-assembler {\mxsmaxcqp\M} } } */
+/* { dg-final { scan-assembler {\mxsmincqp\M} } } */
--
2.22.0
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797
next prev parent reply other threads:[~2020-11-16 4:50 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-16 4:45 [PATCH 0/2] Power10 IEEE 128-bit min, max, cmove Michael Meissner
2020-11-16 4:50 ` Michael Meissner [this message]
2020-12-04 4:35 ` Ping: [PATCH 1/2] Power10: Add IEEE 128-bit xsmaxcqp and xsmincqp support Michael Meissner
2020-12-10 15:38 ` Ping x2: " Michael Meissner
2020-11-16 4:53 ` [PATCH 2/2] Power10: Add IEEE 128-bit fp conditional move Michael Meissner
2020-12-04 4:37 ` Ping: " Michael Meissner
2020-12-10 15:40 ` Ping x2: " Michael Meissner
-- strict thread matches above, loose matches on Subject: below --
2020-09-22 3:39 [PATCH 0/2] Rework adding Power10 IEEE 128-bit min, max, and " Michael Meissner
2020-09-22 3:41 ` [PATCH 1/2] Power10: Add IEEE 128-bit xsmaxcqp and xsmincqp support Michael Meissner
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