* [committed 1/6] arc: Don't use predicated vadd2 instructions in mov patterns.
@ 2020-12-29 11:36 Claudiu Zissulescu
2020-12-29 11:36 ` [committed 2/6] arc: Fix cached to uncached moves Claudiu Zissulescu
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Claudiu Zissulescu @ 2020-12-29 11:36 UTC (permalink / raw)
To: gcc-patches; +Cc: fbedard
Update movdi, movdf and mov vectors not to use predicated vadd2
instructions. vadd2 is used as a "fast" move in these patterns. This
fixes a number of failures in dejagnu.
gcc/
2020-12-29 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.md (movdi_insn): Update pattern, no predicated
vadd2 usage.
(movdf_insn): Likewise.
* config/arc/simdext.md (movVEC_insn): Likewise.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
---
gcc/config/arc/arc.md | 6 +++---
gcc/config/arc/simdext.md | 4 ++--
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index ae08146bcaf..75c32f6d3e9 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -1341,7 +1341,7 @@ (define_insn_and_split "*movdi_insn"
if (TARGET_PLUS_QMACW
&& even_register_operand (operands[0], DImode)
&& even_register_operand (operands[1], DImode))
- return \"vadd2\\t%0,%1,0\";
+ return \"vadd2%?\\t%0,%1,0\";
return \"#\";
case 2:
@@ -1421,7 +1421,7 @@ (define_insn_and_split "*movdf_insn"
if (TARGET_PLUS_QMACW
&& even_register_operand (operands[0], DFmode)
&& even_register_operand (operands[1], DFmode))
- return \"vadd2\\t%0,%1,0\";
+ return \"vadd2%?\\t%0,%1,0\";
return \"#\";
case 4:
@@ -1450,7 +1450,7 @@ (define_insn_and_split "*movdf_insn"
DONE;
}
[(set_attr "type" "move,move,move,move,load,store")
- (set_attr "predicable" "no,no,yes,yes,no,no")
+ (set_attr "predicable" "no,no,no,yes,no,no")
;; ??? The ld/st values could be 16 if it's [reg,bignum].
(set_attr "length" "4,16,8,16,16,16")])
diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md
index d2fc309ea87..58651b5fcac 100644
--- a/gcc/config/arc/simdext.md
+++ b/gcc/config/arc/simdext.md
@@ -1413,7 +1413,7 @@ (define_insn_and_split "*mov<mode>_insn"
if (TARGET_PLUS_QMACW
&& even_register_operand (operands[0], <MODE>mode)
&& even_register_operand (operands[1], <MODE>mode))
- return \"vadd2\\t%0,%1,0\";
+ return \"vadd2%?\\t%0,%1,0\";
return \"#\";
case 2:
@@ -1434,7 +1434,7 @@ (define_insn_and_split "*mov<mode>_insn"
DONE;
}
[(set_attr "type" "move,multi,load,store")
- (set_attr "predicable" "yes,no,no,no")
+ (set_attr "predicable" "no,no,no,no")
(set_attr "iscompact" "false,false,false,false")
])
--
2.26.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [committed 2/6] arc: Fix cached to uncached moves.
2020-12-29 11:36 [committed 1/6] arc: Don't use predicated vadd2 instructions in mov patterns Claudiu Zissulescu
@ 2020-12-29 11:36 ` Claudiu Zissulescu
2020-12-29 11:36 ` [committed 3/6] arc: Update test pattern Claudiu Zissulescu
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Claudiu Zissulescu @ 2020-12-29 11:36 UTC (permalink / raw)
To: gcc-patches; +Cc: fbedard
We need an temporary register when moving data from a cached memory to
an uncached memory. Fix this issue and add a test for it.
gcc/
2020-12-29 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (prepare_move_operands): Use a temporary
registers when we have cached mem-to-uncached mem moves.
gcc/testsuite/
2020-12-29 Claudiu Zissulescu <claziss@synopsys.com>
Vladimir Isaev <isaev@synopsys.com>
* cc.target/arc/uncached-9.c: New test.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
---
gcc/config/arc/arc.c | 12 +++++--
gcc/testsuite/gcc.target/arc/uncached-9.c | 39 +++++++++++++++++++++++
2 files changed, 49 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/arc/uncached-9.c
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 6a9e1fbf824..d0a52ee8b8d 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -9234,13 +9234,21 @@ prepare_move_operands (rtx *operands, machine_mode mode)
}
if (arc_is_uncached_mem_p (operands[1]))
{
+ rtx tmp = operands[0];
+
if (MEM_P (operands[0]))
- operands[0] = force_reg (mode, operands[0]);
+ tmp = gen_reg_rtx (mode);
+
emit_insn (gen_rtx_SET
- (operands[0],
+ (tmp,
gen_rtx_UNSPEC_VOLATILE
(mode, gen_rtvec (1, operands[1]),
VUNSPEC_ARC_LDDI)));
+ if (MEM_P (operands[0]))
+ {
+ operands[1] = tmp;
+ return false;
+ }
return true;
}
}
diff --git a/gcc/testsuite/gcc.target/arc/uncached-9.c b/gcc/testsuite/gcc.target/arc/uncached-9.c
new file mode 100644
index 00000000000..4caba293bc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/uncached-9.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+#include <stdlib.h>
+
+struct uncached_st
+{
+ int value;
+} __attribute__((uncached));
+
+struct cached_st
+{
+ int value;
+};
+
+struct uncached_st g_uncached_st =
+ {
+ .value = 17
+ };
+
+struct cached_st g_cached_st =
+ {
+ .value = 4
+ };
+
+void __attribute__((noinline)) test_struct_copy (void)
+{
+ g_cached_st.value = g_uncached_st.value;
+}
+
+int main (void)
+{
+ test_struct_copy();
+
+ if (g_cached_st.value != g_uncached_st.value)
+ abort ();
+
+ return 0;
+}
--
2.26.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [committed 3/6] arc: Update test pattern.
2020-12-29 11:36 [committed 1/6] arc: Don't use predicated vadd2 instructions in mov patterns Claudiu Zissulescu
2020-12-29 11:36 ` [committed 2/6] arc: Fix cached to uncached moves Claudiu Zissulescu
@ 2020-12-29 11:36 ` Claudiu Zissulescu
2020-12-29 11:36 ` [committed 4/6] arc: Make use reg_renumber safe Claudiu Zissulescu
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Claudiu Zissulescu @ 2020-12-29 11:36 UTC (permalink / raw)
To: gcc-patches; +Cc: fbedard
gcc/testsuite
2020-12-29 Claudiu Zissulescu <claziss@synopsys.com>
* gcc.target/arc/loop-3.c: Update test pattern.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
---
gcc/testsuite/gcc.target/arc/loop-3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/arc/loop-3.c b/gcc/testsuite/gcc.target/arc/loop-3.c
index bf7aec94842..7f55e2f43fa 100644
--- a/gcc/testsuite/gcc.target/arc/loop-3.c
+++ b/gcc/testsuite/gcc.target/arc/loop-3.c
@@ -23,5 +23,5 @@ void fn1(void)
}
}
-/* { dg-final { scan-assembler "bne_s @.L2" } } */
+/* { dg-final { scan-assembler "bne.*@.L2" } } */
/* { dg-final { scan-assembler-not "add.eq" } } */
--
2.26.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [committed 4/6] arc: Make use reg_renumber safe.
2020-12-29 11:36 [committed 1/6] arc: Don't use predicated vadd2 instructions in mov patterns Claudiu Zissulescu
2020-12-29 11:36 ` [committed 2/6] arc: Fix cached to uncached moves Claudiu Zissulescu
2020-12-29 11:36 ` [committed 3/6] arc: Update test pattern Claudiu Zissulescu
@ 2020-12-29 11:36 ` Claudiu Zissulescu
2020-12-29 11:36 ` [committed 5/6] arc: flip if-condition predicates in secondary reload hook Claudiu Zissulescu
2020-12-29 11:36 ` [committed 6/6] arc: generate mac(u) insn instead of macd(u) when destination is accl Claudiu Zissulescu
4 siblings, 0 replies; 6+ messages in thread
From: Claudiu Zissulescu @ 2020-12-29 11:36 UTC (permalink / raw)
To: gcc-patches; +Cc: fbedard
The REGNO_OK_FOR_BASE_P is using reg_renumber array. However, it is
not always defined. Use it only when it is defined.
gcc/
2020-12-29 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.h (REGNO_OK_FOR_BASE_P): Check if defined
reg_renumber.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
---
gcc/config/arc/arc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index fd6e21adfaa..c3886330f1b 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -588,7 +588,7 @@ extern enum reg_class arc_regno_reg_class[];
|| ((REGNO) == ARG_POINTER_REGNUM) \
|| ((REGNO) == FRAME_POINTER_REGNUM) \
|| ((REGNO) == PCL_REG) \
- || ((unsigned) reg_renumber[REGNO] < 29) \
+ || (reg_renumber && ((unsigned) reg_renumber[REGNO] < 29)) \
|| ((unsigned) (REGNO) == (unsigned) arc_tp_regno) \
|| (fixed_regs[REGNO] == 0 && IN_RANGE (REGNO, 32, 59)) \
|| (fixed_regs[REGNO] == 0 && (REGNO) == R30_REG))
--
2.26.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [committed 5/6] arc: flip if-condition predicates in secondary reload hook
2020-12-29 11:36 [committed 1/6] arc: Don't use predicated vadd2 instructions in mov patterns Claudiu Zissulescu
` (2 preceding siblings ...)
2020-12-29 11:36 ` [committed 4/6] arc: Make use reg_renumber safe Claudiu Zissulescu
@ 2020-12-29 11:36 ` Claudiu Zissulescu
2020-12-29 11:36 ` [committed 6/6] arc: generate mac(u) insn instead of macd(u) when destination is accl Claudiu Zissulescu
4 siblings, 0 replies; 6+ messages in thread
From: Claudiu Zissulescu @ 2020-12-29 11:36 UTC (permalink / raw)
To: gcc-patches; +Cc: fbedard
The ARC code contains code which should only work with the old reload
pass. Such code is found in arc_secondary_reload hook, however it was
not properly quarded. Reverse the if-condition predicate such that
req_equiv_mem is called when lra is not in progress.
gcc/
2020-12-29 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (arc_secondary_reload): Flip if-condition
predicates.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
---
gcc/config/arc/arc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index d0a52ee8b8d..fb672c75ff4 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -901,7 +901,7 @@ arc_secondary_reload (bool in_p,
/* It is a pseudo that ends in a stack location. This
procedure only works with the old reload step. */
- if (reg_equiv_mem (REGNO (x)) && !lra_in_progress)
+ if (!lra_in_progress && reg_equiv_mem (REGNO (x)))
{
/* Get the equivalent address and check the range of the
offset. */
--
2.26.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [committed 6/6] arc: generate mac(u) insn instead of macd(u) when destination is accl
2020-12-29 11:36 [committed 1/6] arc: Don't use predicated vadd2 instructions in mov patterns Claudiu Zissulescu
` (3 preceding siblings ...)
2020-12-29 11:36 ` [committed 5/6] arc: flip if-condition predicates in secondary reload hook Claudiu Zissulescu
@ 2020-12-29 11:36 ` Claudiu Zissulescu
4 siblings, 0 replies; 6+ messages in thread
From: Claudiu Zissulescu @ 2020-12-29 11:36 UTC (permalink / raw)
To: gcc-patches; +Cc: fbedard
Generate MAC(U) instruction instead of MACD(U) when the destination
register is already choosen as ACCL register.
gcc/
2020-12-29 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.md (maddsidi4_split): Skip macd gen, use mac insn
instead.
(macd): Update register letters.
(umaddsidi4_split): Skip macdu gen, use macu insn instead.
(macdu): Update register letters.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
---
gcc/config/arc/arc.md | 24 ++++++++++++++----------
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 75c32f6d3e9..b616c7fb82c 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -6176,12 +6176,14 @@ (define_insn_and_split "maddsidi4_split"
"{
rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
emit_move_insn (acc_reg, operands[3]);
- if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode))
- emit_insn (gen_macd (operands[0], operands[1], operands[2]));
+ if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode)
+ && REGNO (operands[0]) != ACCL_REGNO)
+ emit_insn (gen_macd (operands[0], operands[1], operands[2]));
else
{
emit_insn (gen_mac (operands[1], operands[2]));
- emit_move_insn (operands[0], acc_reg);
+ if (REGNO (operands[0]) != ACCL_REGNO)
+ emit_move_insn (operands[0], acc_reg);
}
DONE;
}"
@@ -6192,8 +6194,8 @@ (define_insn "macd"
[(set (match_operand:DI 0 "even_register_operand" "=Rcr,r,r")
(plus:DI
(mult:DI
- (sign_extend:DI (match_operand:SI 1 "register_operand" "%0,c,c"))
- (sign_extend:DI (match_operand:SI 2 "extend_operand" " c,cI,Cal")))
+ (sign_extend:DI (match_operand:SI 1 "register_operand" "%0,r,r"))
+ (sign_extend:DI (match_operand:SI 2 "extend_operand" "r,rI,Cal")))
(reg:DI ARCV2_ACC)))
(set (reg:DI ARCV2_ACC)
(plus:DI
@@ -6276,12 +6278,14 @@ (define_insn_and_split "umaddsidi4_split"
"{
rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
emit_move_insn (acc_reg, operands[3]);
- if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode))
- emit_insn (gen_macdu (operands[0], operands[1], operands[2]));
+ if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode)
+ && REGNO (operands[0]) != ACCL_REGNO)
+ emit_insn (gen_macdu (operands[0], operands[1], operands[2]));
else
{
emit_insn (gen_macu (operands[1], operands[2]));
- emit_move_insn (operands[0], acc_reg);
+ if (REGNO (operands[0]) != ACCL_REGNO)
+ emit_move_insn (operands[0], acc_reg);
}
DONE;
}"
@@ -6292,8 +6296,8 @@ (define_insn "macdu"
[(set (match_operand:DI 0 "even_register_operand" "=Rcr,r,r")
(plus:DI
(mult:DI
- (zero_extend:DI (match_operand:SI 1 "register_operand" "%0,c,c"))
- (zero_extend:DI (match_operand:SI 2 "extend_operand" " c,cI,i")))
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "%0,r,r"))
+ (zero_extend:DI (match_operand:SI 2 "extend_operand" "r,rI,i")))
(reg:DI ARCV2_ACC)))
(set (reg:DI ARCV2_ACC)
(plus:DI
--
2.26.2
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-12-29 11:37 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-29 11:36 [committed 1/6] arc: Don't use predicated vadd2 instructions in mov patterns Claudiu Zissulescu
2020-12-29 11:36 ` [committed 2/6] arc: Fix cached to uncached moves Claudiu Zissulescu
2020-12-29 11:36 ` [committed 3/6] arc: Update test pattern Claudiu Zissulescu
2020-12-29 11:36 ` [committed 4/6] arc: Make use reg_renumber safe Claudiu Zissulescu
2020-12-29 11:36 ` [committed 5/6] arc: flip if-condition predicates in secondary reload hook Claudiu Zissulescu
2020-12-29 11:36 ` [committed 6/6] arc: generate mac(u) insn instead of macd(u) when destination is accl Claudiu Zissulescu
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).