From: Kito Cheng <kito.cheng@sifive.com>
To: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, jimw@sifive.com
Cc: Kito Cheng <kito.cheng@sifive.com>
Subject: [PATCH 2/2] RISC-V: Implement new style of architecture extension test macros.
Date: Mon, 4 Jan 2021 17:48:05 +0800 [thread overview]
Message-ID: <20210104094805.2160-3-kito.cheng@sifive.com> (raw)
In-Reply-To: <20210104094805.2160-1-kito.cheng@sifive.com>
- This patch introduce new set of architecture extension test macros
which is accept on riscv-c-api-doc recently.
- https://github.com/riscv/riscv-c-api-doc/blob/master/riscv-c-api.md#architecture-extension-test-macro
- We will also mark deprecated for legacy architecture extension test macros
in GCC 11, but still support that for 1 or 2 release cycles.
gcc/ChangeLog:
* common/config/riscv/riscv-common.c (riscv_current_subset_list): New.
* config/riscv/riscv-c.c (riscv-protos.h): New.
(riscv_cpu_cpp_builtins): Add new style architecture extension
test macros.
* config/riscv/riscv-protos.h (string):
(riscv_subset_list::begin): New.
(riscv_subset_list::end): New.
(riscv_current_subset_list): New.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-10.c: New.
* gcc.target/riscv/predef-11.c: New.
* gcc.target/riscv/predef-12.c: New.
* gcc.target/riscv/predef-13.c: New.
---
gcc/common/config/riscv/riscv-common.c | 5 +++
gcc/config/riscv/riscv-c.c | 31 ++++++++++++++++
gcc/config/riscv/riscv-protos.h | 7 ++++
gcc/testsuite/gcc.target/riscv/predef-10.c | 43 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/predef-11.c | 43 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/predef-12.c | 43 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/predef-13.c | 43 ++++++++++++++++++++++
7 files changed, 215 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-13.c
diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
index 3a8bcbef006..c859440c477 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -111,6 +111,11 @@ static const char *riscv_supported_std_ext (void);
static riscv_subset_list *current_subset_list = NULL;
+const riscv_subset_list *riscv_current_subset_list ()
+{
+ return current_subset_list;
+}
+
riscv_subset_t::riscv_subset_t ()
: name (), major_version (0), minor_version (0), next (NULL),
explicit_version_p (false), implied_p (false)
diff --git a/gcc/config/riscv/riscv-c.c b/gcc/config/riscv/riscv-c.c
index c600badb313..e8c5f375374 100644
--- a/gcc/config/riscv/riscv-c.c
+++ b/gcc/config/riscv/riscv-c.c
@@ -26,6 +26,7 @@ along with GCC; see the file COPYING3. If not see
#include "tm.h"
#include "c-family/c-common.h"
#include "cpplib.h"
+#include "riscv-protos.h"
#define builtin_define(TXT) cpp_define (pfile, TXT)
@@ -101,4 +102,34 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
break;
}
+
+ /* Define architecture extension test macros. */
+ builtin_define_with_int_value ("__riscv_arch_test", 1);
+
+ const riscv_subset_list *subset_list = riscv_current_subset_list ();
+ size_t max_ext_len = 0;
+
+ /* Figure out the max length of extension name for reserving buffer. */
+ for (const riscv_subset_t *subset = subset_list->begin ();
+ subset != subset_list->end ();
+ subset = subset->next)
+ max_ext_len = MAX (max_ext_len, subset->name.length ());
+
+ char *buf = (char *)alloca (max_ext_len + 10 /* For __riscv_ and '\0'. */);
+
+ for (const riscv_subset_t *subset = subset_list->begin ();
+ subset != subset_list->end ();
+ subset = subset->next)
+ {
+ int version_value = (subset->major_version * 1000000)
+ + (subset->minor_version * 1000);
+ /* Special rule for zicsr and zifencei, it's used for ISA spec 2.2 or
+ earlier. */
+ if ((subset->name == "zicsr" || subset->name == "zifencei")
+ && version_value == 0)
+ version_value = 2000000;
+
+ sprintf (buf, "__riscv_%s", subset->name.c_str ());
+ builtin_define_with_int_value (buf, version_value);
+ }
}
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 1a258553d73..bbd38ff0170 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -22,6 +22,8 @@ along with GCC; see the file COPYING3. If not see
#ifndef GCC_RISCV_PROTOS_H
#define GCC_RISCV_PROTOS_H
+#include <string>
+
/* Symbol types we understand. The order of this list must match that of
the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */
enum riscv_symbol_type {
@@ -173,6 +175,11 @@ public:
static riscv_subset_list *parse (const char *, location_t);
int match_score (riscv_subset_list *) const;
+
+ const riscv_subset_t *begin () const {return m_head;};
+ const riscv_subset_t *end () const {return NULL;};
};
+extern const riscv_subset_list *riscv_current_subset_list (void);
+
#endif /* ! GCC_RISCV_PROTOS_H */
diff --git a/gcc/testsuite/gcc.target/riscv/predef-10.c b/gcc/testsuite/gcc.target/riscv/predef-10.c
new file mode 100644
index 00000000000..7c447bfb08d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-10.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32i2p0 -mabi=ilp32 -mcmodel=medlow -misa-spec=2.2" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 32
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i) || (__riscv_i != (2 * 1000 * 1000))
+#error "__riscv_i"
+#endif
+
+#if defined(__riscv_c)
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_e)
+#error "__riscv_e"
+#endif
+
+#if defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+#if defined(__riscv_m)
+#error "__riscv_m"
+#endif
+
+#if defined(__riscv_f)
+#error "__riscv_f"
+#endif
+
+#if defined(__riscv_d)
+#error "__riscv_d"
+#endif
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-11.c b/gcc/testsuite/gcc.target/riscv/predef-11.c
new file mode 100644
index 00000000000..80f48113dfa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-11.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i) || (__riscv_i != (2 * 1000 * 1000))
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_c) || (__riscv_c != (2 * 1000 * 1000))
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_e)
+#error "__riscv_e"
+#endif
+
+#if !defined(__riscv_a) || (__riscv_a != (2 * 1000 * 1000))
+#error "__riscv_a"
+#endif
+
+#if !defined(__riscv_m) || (__riscv_m != (2 * 1000 * 1000))
+#error "__riscv_m"
+#endif
+
+#if !defined(__riscv_f) || (__riscv_f != (2 * 1000 * 1000))
+#error "__riscv_f"
+#endif
+
+#if !defined(__riscv_d) || (__riscv_d != (2 * 1000 * 1000))
+#error "__riscv_d"
+#endif
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-12.c b/gcc/testsuite/gcc.target/riscv/predef-12.c
new file mode 100644
index 00000000000..dd35dbde925
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-12.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc -mabi=lp64 -mcmodel=medlow -misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i) || (__riscv_i != (2 * 1000 * 1000 + 1 * 1000))
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_c) || (__riscv_c != (2 * 1000 * 1000))
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_e)
+#error "__riscv_e"
+#endif
+
+#if !defined(__riscv_a) || (__riscv_a != (2 * 1000 * 1000 + 1 * 1000))
+#error "__riscv_a"
+#endif
+
+#if !defined(__riscv_m) || (__riscv_m != (2 * 1000 * 1000))
+#error "__riscv_m"
+#endif
+
+#if !defined(__riscv_f) || (__riscv_f != (2 * 1000 * 1000 + 2 * 1000))
+#error "__riscv_f"
+#endif
+
+#if !defined(__riscv_d) || (__riscv_d != (2 * 1000 * 1000 + 2 * 1000))
+#error "__riscv_d"
+#endif
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-13.c b/gcc/testsuite/gcc.target/riscv/predef-13.c
new file mode 100644
index 00000000000..95cf0012408
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-13.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32e -mabi=ilp32e -mcmodel=medlow -misa-spec=2.2" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 32
+#error "__riscv_xlen"
+#endif
+
+#if defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if defined(__riscv_c)
+#error "__riscv_c"
+#endif
+
+#if !defined(__riscv_e) || (__riscv_e != (1 * 1000 * 1000 + 9 * 1000))
+#error "__riscv_e"
+#endif
+
+#if defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+#if defined(__riscv_m)
+#error "__riscv_m"
+#endif
+
+#if defined(__riscv_f)
+#error "__riscv_f"
+#endif
+
+#if defined(__riscv_d)
+#error "__riscv_d"
+#endif
+
+ return 0;
+}
--
2.29.2
next prev parent reply other threads:[~2021-01-04 9:48 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-04 9:48 [PATCH 0/2] RISC-V: Introduce new " Kito Cheng
2021-01-04 9:48 ` [PATCH 1/2] RISC-V: Move class riscv_subset_list and riscv_subset_t to riscv-protos.h Kito Cheng
2021-01-04 9:48 ` Kito Cheng [this message]
2021-01-06 15:23 ` [PATCH 0/2] RISC-V: Introduce new architecture extension test macros Kito Cheng
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