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[135.181.61.214]) by smtp.gmail.com with ESMTPSA id g69sm495226lfd.161.2021.01.06.09.33.08 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Jan 2021 09:33:08 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Andrew Waterman , Kito Cheng , Philipp Tomsich Subject: [PATCH] RISC-V: Zihintpause: add __builtin_riscv_pause Date: Wed, 6 Jan 2021 18:33:03 +0100 Message-Id: <20210106173303.27988-1-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.18.4 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 17:33:12 -0000 The Zihintpause extension uses an opcode from the 'fence' opcode range to add a true hint instruction (i.e. if it is not supported on any given platform, the 'fence' that is encoded will not enforce any specific ordering on memory accesses) for entering a low-power state (e.g. in an idle thread). We expose this new instruction through a machine-dependent builtin to allow generating it without a requirement for any inline assembly. Given that the encoding of 'pause' is valid (as a 'fence' encoding) even for processors that do not (yet) support Zihintpause, we make this builtin available without any further TARGET_* constraints. The new builtin takes no arguments and has no return (void -> void), which requires a change to maybe_gen_insn; similar builtins w/o arguments and results in other architectures (e.g. rx_brk) bypass maybe_gen_insn... making this the first time that nops == 0 is seen here. gcc/ChangeLog: * config/riscv/riscv-builtins.c: add the pause machine-dependent builtin with no result and no arguments; mark it as always present (pause is a true hint that encodes into a fence-insn, if not supported with the new pause semantics). * config/riscv/riscv-ftypes.def: Add type for void -> void. * config/riscv/riscv.md: Add risc_pause and UNSPECV_PAUSE * doc/extend.texi: Document. * optabs.c (maybe_gen_insn): Allow nops == 0 (void -> void). gcc/testsuite/ChangeLog: * gcc.target/riscv/builtin_pause.c: New test. --- gcc/config/riscv/riscv-builtins.c | 4 +++- gcc/config/riscv/riscv-ftypes.def | 1 + gcc/config/riscv/riscv.md | 8 ++++++++ gcc/doc/extend.texi | 4 ++++ gcc/optabs.c | 2 ++ gcc/testsuite/gcc.target/riscv/builtin_pause.c | 10 ++++++++++ 6 files changed, 28 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/builtin_pause.c diff --git a/gcc/config/riscv/riscv-builtins.c b/gcc/config/riscv/riscv-builtins.c index bc959389c76..18b9dc579a1 100644 --- a/gcc/config/riscv/riscv-builtins.c +++ b/gcc/config/riscv/riscv-builtins.c @@ -86,6 +86,7 @@ struct riscv_builtin_description { }; AVAIL (hard_float, TARGET_HARD_FLOAT) +AVAIL (always, (!0)) /* Construct a riscv_builtin_description from the given arguments. @@ -129,7 +130,8 @@ AVAIL (hard_float, TARGET_HARD_FLOAT) static const struct riscv_builtin_description riscv_builtins[] = { DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float), - DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float) + DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float), + DIRECT_NO_TARGET_BUILTIN (pause, RISCV_VOID_FTYPE, always), }; /* Index I is the function declaration for riscv_builtins[I], or null if the diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def index 1c6bc4e9dce..fcb042222db 100644 --- a/gcc/config/riscv/riscv-ftypes.def +++ b/gcc/config/riscv/riscv-ftypes.def @@ -27,4 +27,5 @@ along with GCC; see the file COPYING3. If not see argument type. */ DEF_RISCV_FTYPE (0, (USI)) +DEF_RISCV_FTYPE (0, (VOID)) DEF_RISCV_FTYPE (1, (VOID, USI)) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 254147c112a..b8fb2b8c279 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -69,6 +69,9 @@ (define_c_enum "unspecv" [ ;; Stack Smash Protector UNSPEC_SSP_SET UNSPEC_SSP_TEST + + ;; Zihintpause unspec + UNSPECV_PAUSE ]) (define_constants @@ -1559,6 +1562,11 @@ (define_insn "fence_i" "TARGET_ZIFENCEI" "fence.i") +(define_insn "riscv_pause" + [(unspec_volatile [(const_int 0)] UNSPECV_PAUSE)] + "" + "pause") + ;; ;; .................... ;; diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index e73464a7f19..4cd19c2ebbb 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -22056,6 +22056,10 @@ processors. Returns the value that is currently set in the @samp{tp} register. @end deftypefn +@deftypefn {Built-in Function} void __builtin_riscv_pause (void) +Generates the @code{pause} (hint) machine instruction. +@end deftypefn + @node RX Built-in Functions @subsection RX Built-in Functions GCC supports some of the RX instructions which cannot be expressed in diff --git a/gcc/optabs.c b/gcc/optabs.c index 0427063e277..f7a1bf5be1c 100644 --- a/gcc/optabs.c +++ b/gcc/optabs.c @@ -7777,6 +7777,8 @@ maybe_gen_insn (enum insn_code icode, unsigned int nops, switch (nops) { + case 0: + return GEN_FCN (icode) (); case 1: return GEN_FCN (icode) (ops[0].value); case 2: diff --git a/gcc/testsuite/gcc.target/riscv/builtin_pause.c b/gcc/testsuite/gcc.target/riscv/builtin_pause.c new file mode 100644 index 00000000000..9250937cabb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/builtin_pause.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void test_pause() +{ + __builtin_riscv_pause (); +} + +/* { dg-final { scan-assembler "pause" } } */ + -- 2.18.4