From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from bahamut.mc.pp.se (bahamut.mc.pp.se [IPv6:2001:470:dcd3:1:214:4fff:fe97:7322]) by sourceware.org (Postfix) with ESMTP id 276B73857012 for ; Fri, 19 Mar 2021 19:49:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 276B73857012 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=mc.pp.se Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=marcus@mc.pp.se Received: from hakua (hakua [192.168.42.40]) by bahamut.mc.pp.se (Postfix) with SMTP id F239BA29FF; Fri, 19 Mar 2021 20:49:16 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=mc.pp.se; s=hedgehog; t=1616183357; bh=hSQcQLqMKq7rOPARE6jE8/APAHO0phCDwntEWVP6U+4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding; b=YpzMkAWlkbF7gYdEu7ReCbBf lD2Xuv1lW2+iNwCaZGeKH1TWmyCQGeiOGwK6aZS92Kelj1t7fjP0cflTAml/NMt4cSL q9lOP3yie+C5NN3zIpw36J/c4sUxTvIw4hjQ82E4/HYZMA5I6taIzZzYeqLqb+TylWp dWNkLRjm7nDFA= Received: by hakua (sSMTP sendmail emulation); Fri, 19 Mar 2021 20:49:16 +0100 From: "Marcus Comstedt" To: gcc-patches@gcc.gnu.org Cc: Marcus Comstedt Subject: [PATCH v4 2/7] RISC-V: Add riscv{32,64}be with big endian as default Date: Fri, 19 Mar 2021 20:49:04 +0100 Message-Id: <20210319194909.15653-3-marcus@mc.pp.se> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210319194909.15653-1-marcus@mc.pp.se> References: <20210319194909.15653-1-marcus@mc.pp.se> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 19 Mar 2021 19:49:20 -0000 gcc/ * common/config/riscv/riscv-common.c (TARGET_DEFAULT_TARGET_FLAGS): Set default endianness. * config.gcc (riscv32be-*, riscv64be-*): Set TARGET_BIG_ENDIAN_DEFAULT to 1. * config/riscv/elf.h (LINK_SPEC): Change -melf* value depending on default endianness. * config/riscv/freebsd.h (LINK_SPEC): Likewise. * config/riscv/linux.h (LINK_SPEC): Likewise. * config/riscv/riscv.c (TARGET_DEFAULT_TARGET_FLAGS): Set default endianness. * config/riscv/riscv.h (DEFAULT_ENDIAN_SPEC): New macro. --- gcc/common/config/riscv/riscv-common.c | 5 +++++ gcc/config.gcc | 15 +++++++++++++++ gcc/config/riscv/elf.h | 2 +- gcc/config/riscv/freebsd.h | 2 +- gcc/config/riscv/linux.h | 2 +- gcc/config/riscv/riscv.c | 5 +++++ gcc/config/riscv/riscv.h | 6 ++++++ 7 files changed, 34 insertions(+), 3 deletions(-) diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c index 6bbe25dba89..34b74e52a2d 100644 --- a/gcc/common/config/riscv/riscv-common.c +++ b/gcc/common/config/riscv/riscv-common.c @@ -32,6 +32,11 @@ along with GCC; see the file COPYING3. If not see #include "config/riscv/riscv-protos.h" #include "config/riscv/riscv-subset.h" +#ifdef TARGET_BIG_ENDIAN_DEFAULT +#undef TARGET_DEFAULT_TARGET_FLAGS +#define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_ENDIAN) +#endif + /* Type for implied ISA info. */ struct riscv_implied_info_t { diff --git a/gcc/config.gcc b/gcc/config.gcc index 17fea83b2e4..ae47e430062 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -2464,6 +2464,11 @@ riscv*-*-linux*) tmake_file="${tmake_file} riscv/t-riscv riscv/t-linux" gnu_ld=yes gas=yes + case $target in + riscv32be-*|riscv64be-*) + tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1" + ;; + esac # Force .init_array support. The configure script cannot always # automatically detect that GAS supports it, yet we require it. gcc_cv_initfini_array=yes @@ -2487,6 +2492,11 @@ riscv*-*-elf* | riscv*-*-rtems*) tmake_file="${tmake_file} riscv/t-riscv" gnu_ld=yes gas=yes + case $target in + riscv32be-*|riscv64be-*) + tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1" + ;; + esac # Force .init_array support. The configure script cannot always # automatically detect that GAS supports it, yet we require it. gcc_cv_initfini_array=yes @@ -2496,6 +2506,11 @@ riscv*-*-freebsd*) tmake_file="${tmake_file} riscv/t-riscv" gnu_ld=yes gas=yes + case $target in + riscv32be-*|riscv64be-*) + tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1" + ;; + esac # Force .init_array support. The configure script cannot always # automatically detect that GAS supports it, yet we require it. gcc_cv_initfini_array=yes diff --git a/gcc/config/riscv/elf.h b/gcc/config/riscv/elf.h index 973efdaed7b..7e65e499031 100644 --- a/gcc/config/riscv/elf.h +++ b/gcc/config/riscv/elf.h @@ -18,7 +18,7 @@ along with GCC; see the file COPYING3. If not see . */ #define LINK_SPEC "\ --melf" XLEN_SPEC "lriscv \ +-melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv \ %{mno-relax:--no-relax} \ %{mbig-endian:-EB} \ %{mlittle-endian:-EL} \ diff --git a/gcc/config/riscv/freebsd.h b/gcc/config/riscv/freebsd.h index f3aca9f7673..6018e7bb764 100644 --- a/gcc/config/riscv/freebsd.h +++ b/gcc/config/riscv/freebsd.h @@ -40,7 +40,7 @@ along with GCC; see the file COPYING3. If not see #undef LINK_SPEC #define LINK_SPEC " \ - -melf" XLEN_SPEC "lriscv \ + -melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv \ %{p:%nconsider using `-pg' instead of `-p' with gprof (1)} \ %{v:-V} \ %{assert*} %{R*} %{rpath*} %{defsym*} \ diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h index e74f5d3f914..fce5b896e6e 100644 --- a/gcc/config/riscv/linux.h +++ b/gcc/config/riscv/linux.h @@ -58,7 +58,7 @@ along with GCC; see the file COPYING3. If not see "%{mabi=ilp32:_ilp32}" #define LINK_SPEC "\ --melf" XLEN_SPEC "lriscv" LD_EMUL_SUFFIX " \ +-melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv" LD_EMUL_SUFFIX " \ %{mno-relax:--no-relax} \ %{mbig-endian:-EB} \ %{mlittle-endian:-EL} \ diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index fffd0814eee..eab14602355 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -5524,6 +5524,11 @@ riscv_asan_shadow_offset (void) #undef TARGET_ASAN_SHADOW_OFFSET #define TARGET_ASAN_SHADOW_OFFSET riscv_asan_shadow_offset +#ifdef TARGET_BIG_ENDIAN_DEFAULT +#undef TARGET_DEFAULT_TARGET_FLAGS +#define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_ENDIAN) +#endif + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-riscv.h" diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 0b667d2e8b9..3cc3e864a3e 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -30,6 +30,12 @@ along with GCC; see the file COPYING3. If not see /* Target CPU versions for D. */ #define TARGET_D_CPU_VERSIONS riscv_d_target_versions +#ifdef TARGET_BIG_ENDIAN_DEFAULT +#define DEFAULT_ENDIAN_SPEC "b" +#else +#define DEFAULT_ENDIAN_SPEC "l" +#endif + /* Default target_flags if no switches are specified */ #ifndef TARGET_DEFAULT -- 2.26.2