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Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak , Jakub Jelinek , Bernhard Reutner-Fischer , Martin Sebor , Richard Biener Subject: [PATCH v4 1/2] x86: Move OPTION_MASK_* to i386-common.h Date: Wed, 14 Apr 2021 15:39:17 -0700 Message-Id: <20210414223918.230495-2-hjl.tools@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210414223918.230495-1-hjl.tools@gmail.com> References: <20210414223918.230495-1-hjl.tools@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-3036.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, UPPERCASE_75_100 autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 14 Apr 2021 22:39:25 -0000 Move OPTION_MASK_* to i386-common.h so that they can be used in x86 backend. * common/config/i386/i386-common.c (OPTION_MASK_*): Move to ... * common/config/i386/i386-common.h: Here. New file. * config/i386/i386.h: Include common/config/i386/i386-common.h. --- gcc/common/config/i386/i386-common.c | 297 ------------------------- gcc/common/config/i386/i386-common.h | 315 +++++++++++++++++++++++++++ gcc/config/i386/i386.h | 1 + 3 files changed, 316 insertions(+), 297 deletions(-) create mode 100644 gcc/common/config/i386/i386-common.h diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index 1e6c1590ac4..37ff47bd676 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -29,303 +29,6 @@ along with GCC; see the file COPYING3. If not see #include "opts.h" #include "flags.h" -/* Define a set of ISAs which are available when a given ISA is - enabled. MMX and SSE ISAs are handled separately. */ - -#define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX -#define OPTION_MASK_ISA_3DNOW_SET \ - (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET) -#define OPTION_MASK_ISA_3DNOW_A_SET \ - (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET) - -#define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE -#define OPTION_MASK_ISA_SSE2_SET \ - (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET) -#define OPTION_MASK_ISA_SSE3_SET \ - (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET) -#define OPTION_MASK_ISA_SSSE3_SET \ - (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET) -#define OPTION_MASK_ISA_SSE4_1_SET \ - (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET) -#define OPTION_MASK_ISA_SSE4_2_SET \ - (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET) -#define OPTION_MASK_ISA_AVX_SET \ - (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \ - | OPTION_MASK_ISA_XSAVE_SET) -#define OPTION_MASK_ISA_FMA_SET \ - (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET) -#define OPTION_MASK_ISA_AVX2_SET \ - (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET) -#define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR -#define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE -#define OPTION_MASK_ISA_XSAVEOPT_SET \ - (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET) -#define OPTION_MASK_ISA_AVX512F_SET \ - (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET) -#define OPTION_MASK_ISA_AVX512CD_SET \ - (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA_AVX512PF_SET \ - (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA_AVX512ER_SET \ - (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA_AVX512DQ_SET \ - (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA_AVX512BW_SET \ - (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA_AVX512VL_SET \ - (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA_AVX512IFMA_SET \ - (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA_AVX512VBMI_SET \ - (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET) -#define OPTION_MASK_ISA2_AVX5124FMAPS_SET OPTION_MASK_ISA2_AVX5124FMAPS -#define OPTION_MASK_ISA2_AVX5124VNNIW_SET OPTION_MASK_ISA2_AVX5124VNNIW -#define OPTION_MASK_ISA_AVX512VBMI2_SET \ - (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA_AVX512VNNI_SET \ - (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA2_AVXVNNI_SET OPTION_MASK_ISA2_AVXVNNI -#define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \ - (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA_AVX512BITALG_SET \ - (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16 -#define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM -#define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW -#define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED -#define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX -#define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1 -#define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT -#define OPTION_MASK_ISA_XSAVES_SET \ - (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET) -#define OPTION_MASK_ISA_XSAVEC_SET \ - (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET) -#define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB -#define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT -#define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE -#define OPTION_MASK_ISA2_AMX_INT8_SET OPTION_MASK_ISA2_AMX_INT8 -#define OPTION_MASK_ISA2_AMX_BF16_SET OPTION_MASK_ISA2_AMX_BF16 - -/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same - as -msse4.2. */ -#define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET - -#define OPTION_MASK_ISA_SSE4A_SET \ - (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET) -#define OPTION_MASK_ISA_FMA4_SET \ - (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \ - | OPTION_MASK_ISA_AVX_SET) -#define OPTION_MASK_ISA_XOP_SET \ - (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET) -#define OPTION_MASK_ISA_LWP_SET \ - OPTION_MASK_ISA_LWP - -/* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */ -#define OPTION_MASK_ISA_AES_SET \ - (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET) -#define OPTION_MASK_ISA_SHA_SET \ - (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET) -#define OPTION_MASK_ISA_PCLMUL_SET \ - (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET) - -#define OPTION_MASK_ISA_ABM_SET \ - (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT) - -#define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG -#define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD -#define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX -#define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI -#define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2 -#define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT -#define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM -#define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT -#define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16 -#define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF -#define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE -#define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32 - -#define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE -#define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND -#define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE -#define OPTION_MASK_ISA_F16C_SET \ - (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET) -#define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX -#define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO -#define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU -#define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID -#define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI -#define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK -#define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES -#define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ -#define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI -#define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B -#define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG -#define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE -#define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD -#define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE -#define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK -#define OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR -#define OPTION_MASK_ISA2_HRESET_SET OPTION_MASK_ISA2_HRESET -#define OPTION_MASK_ISA2_KL_SET OPTION_MASK_ISA2_KL -#define OPTION_MASK_ISA2_WIDEKL_SET \ - (OPTION_MASK_ISA2_WIDEKL | OPTION_MASK_ISA2_KL_SET) - -/* Define a set of ISAs which aren't available when a given ISA is - disabled. MMX and SSE ISAs are handled separately. */ - -#define OPTION_MASK_ISA_MMX_UNSET \ - (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET) -#define OPTION_MASK_ISA_3DNOW_UNSET \ - (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET) -#define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A - -#define OPTION_MASK_ISA_SSE_UNSET \ - (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET) -#define OPTION_MASK_ISA_SSE2_UNSET \ - (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET) -#define OPTION_MASK_ISA_SSE3_UNSET \ - (OPTION_MASK_ISA_SSE3 \ - | OPTION_MASK_ISA_SSSE3_UNSET \ - | OPTION_MASK_ISA_SSE4A_UNSET ) -#define OPTION_MASK_ISA_SSSE3_UNSET \ - (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET) -#define OPTION_MASK_ISA_SSE4_1_UNSET \ - (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET) -#define OPTION_MASK_ISA_SSE4_2_UNSET \ - (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET ) -#define OPTION_MASK_ISA_AVX_UNSET \ - (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \ - | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \ - | OPTION_MASK_ISA_AVX2_UNSET ) -#define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA -#define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR -#define OPTION_MASK_ISA_XSAVE_UNSET \ - (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \ - | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET \ - | OPTION_MASK_ISA_AVX_UNSET) -#define OPTION_MASK_ISA2_XSAVE_UNSET OPTION_MASK_ISA2_AMX_TILE_UNSET -#define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT -#define OPTION_MASK_ISA_AVX2_UNSET \ - (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET) -#define OPTION_MASK_ISA2_AVX2_UNSET \ - (OPTION_MASK_ISA2_AVXVNNI_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET) -#define OPTION_MASK_ISA_AVX512F_UNSET \ - (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \ - | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \ - | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \ - | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \ - | OPTION_MASK_ISA_AVX512VBMI2_UNSET \ - | OPTION_MASK_ISA_AVX512VNNI_UNSET \ - | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET \ - | OPTION_MASK_ISA_AVX512BITALG_UNSET) -#define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD -#define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF -#define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER -#define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ -#define OPTION_MASK_ISA_AVX512BW_UNSET \ - (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET) -#define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL -#define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA -#define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI -#define OPTION_MASK_ISA2_AVX5124FMAPS_UNSET OPTION_MASK_ISA2_AVX5124FMAPS -#define OPTION_MASK_ISA2_AVX5124VNNIW_UNSET OPTION_MASK_ISA2_AVX5124VNNIW -#define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2 -#define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI -#define OPTION_MASK_ISA2_AVXVNNI_UNSET OPTION_MASK_ISA2_AVXVNNI -#define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ -#define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG -#define OPTION_MASK_ISA2_AVX512BF16_UNSET OPTION_MASK_ISA2_AVX512BF16 -#define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM -#define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW -#define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED -#define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX -#define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1 -#define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT -#define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC -#define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES -#define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB -#define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX -#define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO -#define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU -#define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID -#define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI -#define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK -#define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES -#define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ -#define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI -#define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B -#define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG -#define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE -#define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD -#define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE -#define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT -#define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK -#define OPTION_MASK_ISA2_AMX_TILE_UNSET OPTION_MASK_ISA2_AMX_TILE -#define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8 -#define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16 -#define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR -#define OPTION_MASK_ISA2_HRESET_UNSET OPTION_MASK_ISA2_HRESET -#define OPTION_MASK_ISA2_KL_UNSET \ - (OPTION_MASK_ISA2_KL | OPTION_MASK_ISA2_WIDEKL_UNSET) -#define OPTION_MASK_ISA2_WIDEKL_UNSET OPTION_MASK_ISA2_WIDEKL - -/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same - as -mno-sse4.1. */ -#define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET - -#define OPTION_MASK_ISA_SSE4A_UNSET \ - (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET) - -#define OPTION_MASK_ISA_FMA4_UNSET \ - (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET) -#define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP -#define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP - -#define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES -#define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA -#define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL -#define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM -#define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG -#define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD -#define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX -#define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI -#define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2 -#define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT -#define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM -#define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT -#define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16 -#define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF -#define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE -#define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32 - -#define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE -#define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND -#define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE -#define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C - -#define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \ - (OPTION_MASK_ISA_MMX_UNSET \ - | OPTION_MASK_ISA_SSE_UNSET) - -#define OPTION_MASK_ISA2_AVX512F_UNSET \ - (OPTION_MASK_ISA2_AVX512BF16_UNSET \ - | OPTION_MASK_ISA2_AVX5124FMAPS_UNSET \ - | OPTION_MASK_ISA2_AVX5124VNNIW_UNSET \ - | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET) -#define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ - (OPTION_MASK_ISA2_AVX512F_UNSET) -#define OPTION_MASK_ISA2_AVX_UNSET OPTION_MASK_ISA2_AVX2_UNSET -#define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET -#define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET -#define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET -#define OPTION_MASK_ISA2_SSSE3_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET -#define OPTION_MASK_ISA2_SSE3_UNSET OPTION_MASK_ISA2_SSSE3_UNSET -#define OPTION_MASK_ISA2_SSE2_UNSET \ - (OPTION_MASK_ISA2_SSE3_UNSET | OPTION_MASK_ISA2_KL_UNSET) -#define OPTION_MASK_ISA2_SSE_UNSET OPTION_MASK_ISA2_SSE2_UNSET - -#define OPTION_MASK_ISA2_AVX512BW_UNSET OPTION_MASK_ISA2_AVX512BF16_UNSET - /* Set 1 << value as value of -malign-FLAG option. */ static void diff --git a/gcc/common/config/i386/i386-common.h b/gcc/common/config/i386/i386-common.h new file mode 100644 index 00000000000..4a7fd290bcf --- /dev/null +++ b/gcc/common/config/i386/i386-common.h @@ -0,0 +1,315 @@ +/* IA-32 common macros. + Copyright (C) 2021 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +/* Define a set of ISAs which are available when a given ISA is + enabled. MMX and SSE ISAs are handled separately. */ + +#define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX +#define OPTION_MASK_ISA_3DNOW_SET \ + (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET) +#define OPTION_MASK_ISA_3DNOW_A_SET \ + (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET) + +#define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE +#define OPTION_MASK_ISA_SSE2_SET \ + (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET) +#define OPTION_MASK_ISA_SSE3_SET \ + (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET) +#define OPTION_MASK_ISA_SSSE3_SET \ + (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET) +#define OPTION_MASK_ISA_SSE4_1_SET \ + (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET) +#define OPTION_MASK_ISA_SSE4_2_SET \ + (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET) +#define OPTION_MASK_ISA_AVX_SET \ + (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \ + | OPTION_MASK_ISA_XSAVE_SET) +#define OPTION_MASK_ISA_FMA_SET \ + (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET) +#define OPTION_MASK_ISA_AVX2_SET \ + (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET) +#define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR +#define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE +#define OPTION_MASK_ISA_XSAVEOPT_SET \ + (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET) +#define OPTION_MASK_ISA_AVX512F_SET \ + (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET) +#define OPTION_MASK_ISA_AVX512CD_SET \ + (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512PF_SET \ + (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512ER_SET \ + (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512DQ_SET \ + (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512BW_SET \ + (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512VL_SET \ + (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512IFMA_SET \ + (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512VBMI_SET \ + (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET) +#define OPTION_MASK_ISA2_AVX5124FMAPS_SET OPTION_MASK_ISA2_AVX5124FMAPS +#define OPTION_MASK_ISA2_AVX5124VNNIW_SET OPTION_MASK_ISA2_AVX5124VNNIW +#define OPTION_MASK_ISA_AVX512VBMI2_SET \ + (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512VNNI_SET \ + (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA2_AVXVNNI_SET OPTION_MASK_ISA2_AVXVNNI +#define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \ + (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA_AVX512BITALG_SET \ + (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET) +#define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16 +#define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM +#define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW +#define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED +#define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX +#define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1 +#define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT +#define OPTION_MASK_ISA_XSAVES_SET \ + (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET) +#define OPTION_MASK_ISA_XSAVEC_SET \ + (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET) +#define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB +#define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT +#define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE +#define OPTION_MASK_ISA2_AMX_INT8_SET OPTION_MASK_ISA2_AMX_INT8 +#define OPTION_MASK_ISA2_AMX_BF16_SET OPTION_MASK_ISA2_AMX_BF16 + +/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same + as -msse4.2. */ +#define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET + +#define OPTION_MASK_ISA_SSE4A_SET \ + (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET) +#define OPTION_MASK_ISA_FMA4_SET \ + (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \ + | OPTION_MASK_ISA_AVX_SET) +#define OPTION_MASK_ISA_XOP_SET \ + (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET) +#define OPTION_MASK_ISA_LWP_SET \ + OPTION_MASK_ISA_LWP + +/* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */ +#define OPTION_MASK_ISA_AES_SET \ + (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET) +#define OPTION_MASK_ISA_SHA_SET \ + (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET) +#define OPTION_MASK_ISA_PCLMUL_SET \ + (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET) + +#define OPTION_MASK_ISA_ABM_SET \ + (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT) + +#define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG +#define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD +#define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX +#define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI +#define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2 +#define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT +#define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM +#define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT +#define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16 +#define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF +#define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE +#define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32 + +#define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE +#define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND +#define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE +#define OPTION_MASK_ISA_F16C_SET \ + (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET) +#define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX +#define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO +#define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU +#define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID +#define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI +#define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK +#define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES +#define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ +#define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI +#define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B +#define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG +#define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE +#define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD +#define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE +#define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK +#define OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR +#define OPTION_MASK_ISA2_HRESET_SET OPTION_MASK_ISA2_HRESET +#define OPTION_MASK_ISA2_KL_SET OPTION_MASK_ISA2_KL +#define OPTION_MASK_ISA2_WIDEKL_SET \ + (OPTION_MASK_ISA2_WIDEKL | OPTION_MASK_ISA2_KL_SET) + +/* Define a set of ISAs which aren't available when a given ISA is + disabled. MMX and SSE ISAs are handled separately. */ + +#define OPTION_MASK_ISA_MMX_UNSET \ + (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET) +#define OPTION_MASK_ISA_3DNOW_UNSET \ + (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET) +#define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A + +#define OPTION_MASK_ISA_SSE_UNSET \ + (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET) +#define OPTION_MASK_ISA_SSE2_UNSET \ + (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET) +#define OPTION_MASK_ISA_SSE3_UNSET \ + (OPTION_MASK_ISA_SSE3 \ + | OPTION_MASK_ISA_SSSE3_UNSET \ + | OPTION_MASK_ISA_SSE4A_UNSET ) +#define OPTION_MASK_ISA_SSSE3_UNSET \ + (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET) +#define OPTION_MASK_ISA_SSE4_1_UNSET \ + (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET) +#define OPTION_MASK_ISA_SSE4_2_UNSET \ + (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET ) +#define OPTION_MASK_ISA_AVX_UNSET \ + (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \ + | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \ + | OPTION_MASK_ISA_AVX2_UNSET ) +#define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA +#define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR +#define OPTION_MASK_ISA_XSAVE_UNSET \ + (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \ + | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET \ + | OPTION_MASK_ISA_AVX_UNSET) +#define OPTION_MASK_ISA2_XSAVE_UNSET OPTION_MASK_ISA2_AMX_TILE_UNSET +#define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT +#define OPTION_MASK_ISA_AVX2_UNSET \ + (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET) +#define OPTION_MASK_ISA2_AVX2_UNSET \ + (OPTION_MASK_ISA2_AVXVNNI_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET) +#define OPTION_MASK_ISA_AVX512F_UNSET \ + (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \ + | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \ + | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \ + | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \ + | OPTION_MASK_ISA_AVX512VBMI2_UNSET \ + | OPTION_MASK_ISA_AVX512VNNI_UNSET \ + | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET \ + | OPTION_MASK_ISA_AVX512BITALG_UNSET) +#define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD +#define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF +#define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER +#define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ +#define OPTION_MASK_ISA_AVX512BW_UNSET \ + (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET) +#define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL +#define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA +#define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI +#define OPTION_MASK_ISA2_AVX5124FMAPS_UNSET OPTION_MASK_ISA2_AVX5124FMAPS +#define OPTION_MASK_ISA2_AVX5124VNNIW_UNSET OPTION_MASK_ISA2_AVX5124VNNIW +#define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2 +#define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI +#define OPTION_MASK_ISA2_AVXVNNI_UNSET OPTION_MASK_ISA2_AVXVNNI +#define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ +#define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG +#define OPTION_MASK_ISA2_AVX512BF16_UNSET OPTION_MASK_ISA2_AVX512BF16 +#define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM +#define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW +#define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED +#define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX +#define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1 +#define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT +#define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC +#define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES +#define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB +#define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX +#define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO +#define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU +#define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID +#define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI +#define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK +#define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES +#define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ +#define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI +#define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B +#define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG +#define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE +#define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD +#define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE +#define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT +#define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK +#define OPTION_MASK_ISA2_AMX_TILE_UNSET OPTION_MASK_ISA2_AMX_TILE +#define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8 +#define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16 +#define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR +#define OPTION_MASK_ISA2_HRESET_UNSET OPTION_MASK_ISA2_HRESET +#define OPTION_MASK_ISA2_KL_UNSET \ + (OPTION_MASK_ISA2_KL | OPTION_MASK_ISA2_WIDEKL_UNSET) +#define OPTION_MASK_ISA2_WIDEKL_UNSET OPTION_MASK_ISA2_WIDEKL + +/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same + as -mno-sse4.1. */ +#define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET + +#define OPTION_MASK_ISA_SSE4A_UNSET \ + (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET) + +#define OPTION_MASK_ISA_FMA4_UNSET \ + (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET) +#define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP +#define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP + +#define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES +#define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA +#define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL +#define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM +#define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG +#define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD +#define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX +#define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI +#define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2 +#define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT +#define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM +#define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT +#define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16 +#define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF +#define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE +#define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32 + +#define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE +#define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND +#define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE +#define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C + +#define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \ + (OPTION_MASK_ISA_MMX_UNSET \ + | OPTION_MASK_ISA_SSE_UNSET) + +#define OPTION_MASK_ISA2_AVX512F_UNSET \ + (OPTION_MASK_ISA2_AVX512BF16_UNSET \ + | OPTION_MASK_ISA2_AVX5124FMAPS_UNSET \ + | OPTION_MASK_ISA2_AVX5124VNNIW_UNSET \ + | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET) +#define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ + (OPTION_MASK_ISA2_AVX512F_UNSET) +#define OPTION_MASK_ISA2_AVX_UNSET OPTION_MASK_ISA2_AVX2_UNSET +#define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET +#define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET +#define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET +#define OPTION_MASK_ISA2_SSSE3_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET +#define OPTION_MASK_ISA2_SSE3_UNSET OPTION_MASK_ISA2_SSSE3_UNSET +#define OPTION_MASK_ISA2_SSE2_UNSET \ + (OPTION_MASK_ISA2_SSE3_UNSET | OPTION_MASK_ISA2_KL_UNSET) +#define OPTION_MASK_ISA2_SSE_UNSET OPTION_MASK_ISA2_SSE2_UNSET + +#define OPTION_MASK_ISA2_AVX512BW_UNSET OPTION_MASK_ISA2_AVX512BF16_UNSET diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 97700d797a7..cd5aed30325 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -2575,6 +2575,7 @@ constexpr wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW #include "insn-attr-common.h" +#include "common/config/i386/i386-common.h" #include "common/config/i386/i386-cpuinfo.h" class pta -- 2.30.2