From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by sourceware.org (Postfix) with ESMTPS id 1BDBC3851C1C for ; Thu, 15 Apr 2021 15:11:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 1BDBC3851C1C Received: by mail-pf1-x433.google.com with SMTP id m11so16255270pfc.11 for ; Thu, 15 Apr 2021 08:11:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=OOOYZM5yYvDT797GOTEA2tWo6Pe0Pkk/s2My2ggFplw=; b=ItlwiPq7WN8XR5EAFxskg6DiZW35J+yZ/uSVn6MFRpCC+8wnuXKATutGL7E8zpocoD 7dBUuXIsjx4E+OgFD8zAjiDhRIUVJooMoHXcfMSU260ZDjjU7HkCSJwSpN7cWyek8oYg iFZer6YYFBjgj3rJ7u8FrOV7l+TwJfdSRtucVE9Ocug9ahFPgSU9cZOHJid+HjSmtyRC q0g6RXbEg6LWJaC/o4QBnFQKdpT2uSWc0ohaTwS14mHlkpq9SnCTGvbD8/+as/dSjlGw p84XozaGmo9HXvyw//nLEXyB8jzdH+1mjIJ4Rzd447iGFySoVId8z70uc3DXulcYlT4U Xvvg== X-Gm-Message-State: AOAM5320S66eOQkqq1DUxzw44MISv82oeVAKeQUOY4ue+z+X/zySP0bK RTNl+ump2VwkrvjJLpHoBHoHMza7yhvJ+A== X-Google-Smtp-Source: ABdhPJxV38sfPsyfKjLapRXVwn21NXdNDaqPoOdECnxMWwCNE/n8FVjBTJcaFBP/mAxFJIoffmlUnA== X-Received: by 2002:a65:47ca:: with SMTP id f10mr3912620pgs.206.1618499507587; Thu, 15 Apr 2021 08:11:47 -0700 (PDT) Received: from gnu-cfl-2.localdomain ([2607:fb90:a62d:2d5e:38da:e56e:0:c66]) by smtp.gmail.com with ESMTPSA id f16sm2705184pfj.220.2021.04.15.08.11.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Apr 2021 08:11:46 -0700 (PDT) Received: from gnu-cfl-2.lan (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 99DA01A00E7; Thu, 15 Apr 2021 08:11:44 -0700 (PDT) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Subject: [PATCH] x86: Use crc32 target option for CRC32 intrinsics Date: Thu, 15 Apr 2021 08:11:44 -0700 Message-Id: <20210415151144.439294-1-hjl.tools@gmail.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-3035.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Apr 2021 15:11:50 -0000 Use crc32 target option for CRC32 intrinsics to support CRC32 intrinsics without enabling SSE vector instructions. * config/i386/gnu-property.c (file_end_indicate_exec_stack_and_gnu_property): Also check TARGET_CRC32 for GNU_PROPERTY_X86_ISA_1_V2. * config/i386/i386-c.c (ix86_target_macros_internal): Define __CRC32__ for -mcrc32. * config/i386/i386-options.c (ix86_option_override_internal): Handle PTA_CRC32. Enable crc32 instruction for -msse4.2. * config/i386/i386.h (PTA_CRC32): New. (PTA_X86_64_V2): Add PTA_CRC32. (PTA_NEHALEM): Likewise. * config/i386/i386.md (sse4_2_crc32): Remove TARGET_SSE4_2 check. (sse4_2_crc32di): Likewise. * config/i386/ia32intrin.h: Use crc32 target option for CRC32 intrinsics. --- gcc/config/i386/gnu-property.c | 1 + gcc/config/i386/i386-c.c | 2 ++ gcc/config/i386/i386-options.c | 8 ++++++++ gcc/config/i386/i386.h | 6 ++++-- gcc/config/i386/i386.md | 4 ++-- gcc/config/i386/ia32intrin.h | 28 ++++++++++++++-------------- 6 files changed, 31 insertions(+), 18 deletions(-) diff --git a/gcc/config/i386/gnu-property.c b/gcc/config/i386/gnu-property.c index 4ba04403002..b6a3bdf62ce 100644 --- a/gcc/config/i386/gnu-property.c +++ b/gcc/config/i386/gnu-property.c @@ -92,6 +92,7 @@ file_end_indicate_exec_stack_and_gnu_property (void) /* GNU_PROPERTY_X86_ISA_1_V2. */ if (TARGET_CMPXCHG16B || (TARGET_64BIT && TARGET_SAHF) + || TARGET_CRC32 || TARGET_POPCNT || TARGET_SSE3 || TARGET_SSSE3 diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index be46d0506ad..5ed0de006fb 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -532,6 +532,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__LZCNT__"); if (isa_flag & OPTION_MASK_ISA_TBM) def_or_undef (parse_in, "__TBM__"); + if (isa_flag & OPTION_MASK_ISA_CRC32) + def_or_undef (parse_in, "__CRC32__"); if (isa_flag & OPTION_MASK_ISA_POPCNT) def_or_undef (parse_in, "__POPCNT__"); if (isa_flag & OPTION_MASK_ISA_FSGSBASE) diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c index 91da2849c49..959ee163d2f 100644 --- a/gcc/config/i386/i386-options.c +++ b/gcc/config/i386/i386-options.c @@ -2162,6 +2162,9 @@ ix86_option_override_internal (bool main_args_p, if (((processor_alias_table[i].flags & PTA_CX16) != 0) && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_CX16)) opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CX16; + if (((processor_alias_table[i].flags & PTA_CRC32) != 0) + && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CRC32)) + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32; if (((processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)) != 0) && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT; @@ -2617,6 +2620,11 @@ ix86_option_override_internal (bool main_args_p, opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~opts->x_ix86_isa_flags_explicit; + /* Enable crc32 instruction for -msse4.2. */ + if (TARGET_SSE4_2_P (opts->x_ix86_isa_flags)) + opts->x_ix86_isa_flags + |= OPTION_MASK_ISA_CRC32 & ~opts->x_ix86_isa_flags_explicit; + /* Enable lzcnt instruction for -mabm. */ if (TARGET_ABM_P(opts->x_ix86_isa_flags)) opts->x_ix86_isa_flags diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 97700d797a7..c50f9ab24fa 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -2504,12 +2504,14 @@ constexpr wide_int_bitmask PTA_HRESET (0, HOST_WIDE_INT_1U << 23); constexpr wide_int_bitmask PTA_KL (0, HOST_WIDE_INT_1U << 24); constexpr wide_int_bitmask PTA_WIDEKL (0, HOST_WIDE_INT_1U << 25); constexpr wide_int_bitmask PTA_AVXVNNI (0, HOST_WIDE_INT_1U << 26); +constexpr wide_int_bitmask PTA_CRC32 (0, HOST_WIDE_INT_1U << 27); constexpr wide_int_bitmask PTA_X86_64_BASELINE = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR; constexpr wide_int_bitmask PTA_X86_64_V2 = (PTA_X86_64_BASELINE & (~PTA_NO_SAHF)) - | PTA_CX16 | PTA_POPCNT | PTA_SSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_SSSE3; + | PTA_CRC32 | PTA_CX16 | PTA_POPCNT | PTA_SSE3 | PTA_SSE4_1 | PTA_SSE4_2 + | PTA_SSSE3; constexpr wide_int_bitmask PTA_X86_64_V3 = PTA_X86_64_V2 | PTA_AVX | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_LZCNT | PTA_MOVBE | PTA_XSAVE; @@ -2519,7 +2521,7 @@ constexpr wide_int_bitmask PTA_X86_64_V4 = PTA_X86_64_V3 constexpr wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR; constexpr wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 - | PTA_POPCNT; + | PTA_CRC32 | PTA_POPCNT; constexpr wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_PCLMUL; constexpr wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT; diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 9ff35d9a607..1f1d74e6275 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -20998,7 +20998,7 @@ (define_insn "sse4_2_crc32" [(match_operand:SI 1 "register_operand" "0") (match_operand:SWI124 2 "nonimmediate_operand" "m")] UNSPEC_CRC32))] - "TARGET_SSE4_2 || TARGET_CRC32" + "TARGET_CRC32" "crc32{}\t{%2, %0|%0, %2}" [(set_attr "type" "sselog1") (set_attr "prefix_rep" "1") @@ -21019,7 +21019,7 @@ (define_insn "sse4_2_crc32di" [(match_operand:DI 1 "register_operand" "0") (match_operand:DI 2 "nonimmediate_operand" "rm")] UNSPEC_CRC32))] - "TARGET_64BIT && (TARGET_SSE4_2 || TARGET_CRC32)" + "TARGET_64BIT && TARGET_CRC32" "crc32{q}\t{%2, %0|%0, %2}" [(set_attr "type" "sselog1") (set_attr "prefix_rep" "1") diff --git a/gcc/config/i386/ia32intrin.h b/gcc/config/i386/ia32intrin.h index 591394076cc..5422b0fc9e0 100644 --- a/gcc/config/i386/ia32intrin.h +++ b/gcc/config/i386/ia32intrin.h @@ -51,11 +51,11 @@ __bswapd (int __X) #ifndef __iamcu__ -#ifndef __SSE4_2__ +#ifndef __CRC32__ #pragma GCC push_options -#pragma GCC target("sse4.2") -#define __DISABLE_SSE4_2__ -#endif /* __SSE4_2__ */ +#pragma GCC target("crc32") +#define __DISABLE_CRC32__ +#endif /* __CRC32__ */ /* 32bit accumulate CRC32 (polynomial 0x11EDC6F41) value. */ extern __inline unsigned int @@ -79,10 +79,10 @@ __crc32d (unsigned int __C, unsigned int __V) return __builtin_ia32_crc32si (__C, __V); } -#ifdef __DISABLE_SSE4_2__ -#undef __DISABLE_SSE4_2__ +#ifdef __DISABLE_CRC32__ +#undef __DISABLE_CRC32__ #pragma GCC pop_options -#endif /* __DISABLE_SSE4_2__ */ +#endif /* __DISABLE_CRC32__ */ #endif /* __iamcu__ */ @@ -199,11 +199,11 @@ __bswapq (long long __X) return __builtin_bswap64 (__X); } -#ifndef __SSE4_2__ +#ifndef __CRC32__ #pragma GCC push_options -#pragma GCC target("sse4.2") -#define __DISABLE_SSE4_2__ -#endif /* __SSE4_2__ */ +#pragma GCC target("crc32") +#define __DISABLE_CRC32__ +#endif /* __CRC32__ */ /* 64bit accumulate CRC32 (polynomial 0x11EDC6F41) value. */ extern __inline unsigned long long @@ -213,10 +213,10 @@ __crc32q (unsigned long long __C, unsigned long long __V) return __builtin_ia32_crc32di (__C, __V); } -#ifdef __DISABLE_SSE4_2__ -#undef __DISABLE_SSE4_2__ +#ifdef __DISABLE_CRC32__ +#undef __DISABLE_CRC32__ #pragma GCC pop_options -#endif /* __DISABLE_SSE4_2__ */ +#endif /* __DISABLE_CRC32__ */ /* 64bit popcnt */ extern __inline long long -- 2.30.2