From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 654393858012 for ; Mon, 19 Apr 2021 16:04:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 654393858012 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EA0BB1478 for ; Mon, 19 Apr 2021 09:04:07 -0700 (PDT) Received: from e126323.arm.com (unknown [10.57.58.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6B1543F7D7; Mon, 19 Apr 2021 09:04:07 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [comitted] arm: partial revert of r11-8168 [PR100067] Date: Mon, 19 Apr 2021 17:02:51 +0100 Message-Id: <20210419160251.22362-1-rearnsha@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------2.25.1" Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-14.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 19 Apr 2021 16:04:18 -0000 From: Richard Earnshaw This is a multi-part message in MIME format. --------------2.25.1 Content-Type: text/plain; charset=UTF-8; format=fixed Content-Transfer-Encoding: 8bit From: Richard Earnshaw This is a partial revert of r11-8168. The overall purpose of the commit is retained (to fix a bogus warning when -mfpu= is used in combination with eg -mcpu=neoverse-v1), but it removes the hunk that changed the subsequent feature bits for features of a simd/fp unit that cannot be described by -mfpu. While I still think that is the correct direction of travel, it's somewhat disruptive and not appropriate for late stage4. I'll revisit for gcc-12. gcc: PR target/100067 * config/arm/arm.c (arm_configure_build_target): Do not strip extended FPU/SIMD feature bits from the target ISA when -mfpu is specified (partial revert of r11-8168). --- gcc/config/arm/arm.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) --------------2.25.1 Content-Type: text/x-patch; name="0001-arm-partial-revert-of-r11-8168-PR100067.patch" Content-Transfer-Encoding: 8bit Content-Disposition: attachment; filename="0001-arm-partial-revert-of-r11-8168-PR100067.patch" diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 475fb0d827f..340f7c95d76 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3396,9 +3396,11 @@ arm_configure_build_target (struct arm_build_target *target, auto_sbitmap fpu_bits (isa_num_bits); arm_initialize_isa (fpu_bits, arm_selected_fpu->isa_bits); - /* Clear out ALL bits relating to the FPU/simd extensions, to avoid - potentially invalid combinations later on that we can't match. */ - bitmap_and_compl (target->isa, target->isa, isa_all_fpbits); + /* This should clear out ALL bits relating to the FPU/simd + extensions, to avoid potentially invalid combinations later on + that we can't match. At present we only clear out those bits + that can be set by -mfpu. This should be fixed in GCC-12. */ + bitmap_and_compl (target->isa, target->isa, isa_all_fpubits_internal); bitmap_ior (target->isa, target->isa, fpu_bits); } --------------2.25.1--