From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-f51.google.com (mail-ed1-f51.google.com [209.85.208.51]) by sourceware.org (Postfix) with ESMTPS id 6D0873944427; Mon, 26 Apr 2021 12:46:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 6D0873944427 Received: by mail-ed1-f51.google.com with SMTP id i3so39864660edt.1; Mon, 26 Apr 2021 05:46:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t6h3epVgaxOG5CWl/ju2RUwxI/ZhYGDQL2iqOZ/FkU0=; b=Z49fRjTmfkk2dU9vyHZWxMz1dwAyDJxez6QaGN76Avtg++WKP/xxiabr5y1jev/oaH PliVdQV8kICg8NB69mkIQEbqAH42XrFsTeys09tHHSKUlc3OX4Wbe6FvlaII6amd4omz EltdcA1jS0SILLCTgkHhVj3kr5y0cblKMKkUfydDhFP5IcdwELb4jb/AWMIKFMwoZwaJ WI3JhMp1/EHaU8ojf8ihvopd05sv3aisvnPVqhVmiGWn/eS6GqzxdLc7sGLBNOLhs2AM IlP2WILaFz4+wkl5Uv7Xm+r2xwf3r8t3cJUrxQIKZrTrk8z7bwy3nvSBtnjv4Qwq8dV5 EBjw== X-Gm-Message-State: AOAM533HSN40b91+r3l36VSWLpWGjZOEebCnhW8GQVnPd9wNYzsKSJGT JrgHCo7BA1Ce6WHJXDDGZnNHNq75fcMR+Q== X-Google-Smtp-Source: ABdhPJx68wl7mvwWcY5GcTriPIAMYjVfUDimfmJFIK9ssXWBviARyQjtZ5/p3tJz3xK3biNPYiG+Gg== X-Received: by 2002:a05:6402:cb4:: with SMTP id cn20mr20420591edb.167.1619441163288; Mon, 26 Apr 2021 05:46:03 -0700 (PDT) Received: from beast.fritz.box (62-178-178-158.cable.dynamic.surfer.at. [62.178.178.158]) by smtp.gmail.com with ESMTPSA id o20sm14126755eds.65.2021.04.26.05.46.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Apr 2021 05:46:02 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org Cc: Jim Wilson , Kito Cheng , Christoph Muellner Subject: [PATCH 07/10] RISC-V: Model INSNs for LR and SC [PR 100266] Date: Mon, 26 Apr 2021 14:45:49 +0200 Message-Id: <20210426124552.3316789-8-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210426124552.3316789-1-cmuellner@gcc.gnu.org> References: <20210426124552.3316789-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 26 Apr 2021 12:46:05 -0000 In order to emit LR/SC sequences, let's provide INSNs, which take care of memory ordering constraints. gcc/ PR 100266 * config/rsicv/sync.md (UNSPEC_LOAD_RESERVED): New. * config/rsicv/sync.md (UNSPEC_STORE_CONDITIONAL): New. * config/riscv/sync.md (riscv_load_reserved): New. * config/riscv/sync.md (riscv_store_conditional): New. --- gcc/config/riscv/sync.md | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index ceec324dfa30..edff6520b87e 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -26,6 +26,8 @@ UNSPEC_ATOMIC_LOAD UNSPEC_ATOMIC_STORE UNSPEC_MEMORY_BARRIER + UNSPEC_LOAD_RESERVED + UNSPEC_STORE_CONDITIONAL ]) (define_code_iterator any_atomic [plus ior xor and]) @@ -113,6 +115,28 @@ DONE; }) +(define_insn "@riscv_load_reserved" + [(set (match_operand:GPR 0 "register_operand" "=r") + (unspec_volatile:GPR + [(match_operand:GPR 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_LOAD_RESERVED))] + "TARGET_ATOMIC" + "lr.%A2 %0, %1" +) + +(define_insn "@riscv_store_conditional" + [(set (match_operand:GPR 0 "register_operand" "=&r") + (unspec_volatile:GPR [(const_int 0)] UNSPEC_STORE_CONDITIONAL)) + (set (match_operand:GPR 1 "memory_operand" "=A") + (unspec_volatile:GPR + [(match_operand:GPR 2 "reg_or_0_operand" "rJ") + (match_operand:SI 3 "const_int_operand")] ;; model + UNSPEC_STORE_CONDITIONAL))] + "TARGET_ATOMIC" + "sc.%A3 %0, %z2, %1" +) + (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") (unspec_volatile:GPR -- 2.31.1