From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) by sourceware.org (Postfix) with ESMTPS id 17B363861030; Wed, 5 May 2021 19:37:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 17B363861030 Received: by mail-ej1-f54.google.com with SMTP id r9so4672880ejj.3; Wed, 05 May 2021 12:37:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=iGdkm22Eopbp79n0OLry2lOcCMDory4VOfriULFfF78=; b=PCCJPSk+rLken2P89wcVv6PFu/UN2ChLzm0qZ9CA0y7tDacSJF8jlKSBzNlR7OlfEi 3igXlCkRRErLgg1s89pvH0+De/QQqG+la5zp7e9jnXE6qargjTLRVkBh6AL7hFkaOa4l zk9h19bcWwQCv8dFYuSyXmcwvBOdLc5gAUsDCdsByd4WdYc0T/HVl2ig8Qu49T0Ns8x/ aK3/ugp0slUNx6CXg+Knk07nbXu/rkvZAG7vm+K3w00IHrrlAFGiRUFY/X/2iyG4akGt rEYnkFvvvsWTyX2fC/dHnPS/6WrGhtLKv9m31cLo9igEVbFCMmGB4SzDEBKNwH/vmw7W kanw== X-Gm-Message-State: AOAM531F2jdlWf8kYOav47MJ7VVoXHY9QZGRA84g3zDce56EHZhyl+wz hAPvX3Oulv3qeL5dx/7wsA0HgvOl0zA2gvRq X-Google-Smtp-Source: ABdhPJyvBbPVRluBzJZGp2pKX/EuohFm0D1mimFAZvxkdMi/qV8YeIq/UN8nzUkx6Pmb5pLYA+tGOQ== X-Received: by 2002:a17:906:b251:: with SMTP id ce17mr356981ejb.149.1620243419822; Wed, 05 May 2021 12:36:59 -0700 (PDT) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id t7sm60531eds.26.2021.05.05.12.36.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 12:36:59 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org Cc: Jim Wilson , Kito Cheng , Christoph Muellner Subject: [PATCH v2 00/10] [RISC-V] Atomics improvements [PR100265/PR100266] Date: Wed, 5 May 2021 21:36:41 +0200 Message-Id: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=no autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 05 May 2021 19:37:03 -0000 This series provides a cleanup of the current atomics implementation of RISC-V: * PR100265: Use proper fences for atomic load/store * PR100266: Provide programmatic implementation of CAS As both are very related, I merged the patches into one series. The first patch could be squashed into the following patches, but I found it easier to understand the chances with it in place. The series has been tested as follows: * Building and testing a multilib RV32/64 toolchain (bootstrapped with riscv-gnu-toolchain repo) * Manual review of generated sequences for GCC's atomic builtins API The programmatic re-implementation of CAS benefits from a REE improvement (see PR100264): https://gcc.gnu.org/pipermail/gcc-patches/2021-April/568680.html If this patch is not in place, then an additional extension instruction is emitted after the SC.W (in case of RV64 and CAS for uint32_t). Further, the new CAS code requires cbranch INSN helpers to be present: https://gcc.gnu.org/pipermail/gcc-patches/2021-May/569689.html Changes for v2: * Guard LL/SC sequence by compiler barriers ("blockage") (suggested by Andrew Waterman) * Changed commit message for AMOSWAP->STORE change (suggested by Andrew Waterman) * Extracted cbranch4 patch from patchset (suggested by Kito Cheng) * Introduce predicate riscv_sync_memory_operand (suggested by Jim Wilson) * Fix small code style issue Christoph Muellner (10): RISC-V: Simplify memory model code [PR 100265] RISC-V: Emit proper memory ordering suffixes for AMOs [PR 100265] RISC-V: Eliminate %F specifier from riscv_print_operand() [PR 100265] RISC-V: Use STORE instead of AMOSWAP for atomic stores [PR 100265] RISC-V: Emit fences according to chosen memory model [PR 100265] RISC-V: Implement atomic_{load,store} [PR 100265] RISC-V: Model INSNs for LR and SC [PR 100266] RISC-V: Add s.ext-consuming INSNs for LR and SC [PR 100266] RISC-V: Provide programmatic implementation of CAS [PR 100266] RISC-V: Introduce predicate "riscv_sync_memory_operand" [PR 100266] gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv.c | 136 +++++++++++++------- gcc/config/riscv/sync.md | 216 +++++++++++++++++++++----------- 3 files changed, 235 insertions(+), 118 deletions(-) -- 2.31.1