From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) by sourceware.org (Postfix) with ESMTPS id B905E3861030; Wed, 5 May 2021 19:37:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org B905E3861030 Received: by mail-ed1-f54.google.com with SMTP id u13so3401534edd.3; Wed, 05 May 2021 12:37:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rfBqlL9A5zq+4eQye7vzX/8z8Y9dcGnDYwaNQqgW6F4=; b=mQA0gPAEqShIHT7YY4dZihQbjKrhj/w4E4tBk1U8LoJAgIUjxe6Sf6YczcVAmaghS2 1mP9k0MIh0vYW6IXPK4M9TPbu1r5skVqlt7JEmFI0vZNEy7WumxCYBrGjLhjG7driNav HqWg8tJUdc0n9dgHqe0Wkpuzd+ZLVNTJ38Dx5Afa2ec+kQykIqpK/DU52Pn3xg1ypSnA NutjVBmRG+MVFfVYyuwmY0CVmMqtN/N58kem6fxHPjINKz8mFqfgf9Gsy/ISSQRIb/Yt LXCUY1QbwIGc4UduZsVinmmnq/L8YVQvKaL13cgcbHwTzgxxcVAzwgaXf8i0AEGLKoen ozeg== X-Gm-Message-State: AOAM530Bi25HbAb7OVWhg6CsonFQic3/SIrVuiGpmQojfV7mSXicmNgU V++n+K1oaJktSGWJccFkHk3/KG9bmoW7xSyv X-Google-Smtp-Source: ABdhPJwcSg02GfIW5mjj4xqDTUfvNcjquNrRufrc8bFEu4VQHcfXc5V9hcFqdfJqLjrGBU+l/IbV1g== X-Received: by 2002:aa7:cc15:: with SMTP id q21mr724206edt.140.1620243422531; Wed, 05 May 2021 12:37:02 -0700 (PDT) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id t7sm60531eds.26.2021.05.05.12.37.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 12:37:02 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org Cc: Jim Wilson , Kito Cheng , Christoph Muellner Subject: [PATCH v2 03/10] RISC-V: Eliminate %F specifier from riscv_print_operand() [PR 100265] Date: Wed, 5 May 2021 21:36:44 +0200 Message-Id: <20210505193651.2075405-4-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> References: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 05 May 2021 19:37:05 -0000 A previous patch took care, that the proper memory ordering suffixes for AMOs are emitted. Therefore there is no reason to keep the fence generation mechanism for release operations. gcc/ PR 100265 * config/riscv/riscv.c (riscv_memmodel_needs_release_fence): Remove function. * config/riscv/riscv.c (riscv_print_operand): Remove %F format specifier. * config/riscv/sync.md: Remove %F format specifier uses. --- gcc/config/riscv/riscv.c | 29 ----------------------------- gcc/config/riscv/sync.md | 16 ++++++++-------- 2 files changed, 8 insertions(+), 37 deletions(-) diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 3edd5c239d7c..5fe65776e608 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -3371,29 +3371,6 @@ riscv_print_amo_memory_ordering_suffix (FILE *file, const enum memmodel model) } } -/* Return true if a FENCE should be emitted to before a memory access to - implement the release portion of memory model MODEL. */ - -static bool -riscv_memmodel_needs_release_fence (const enum memmodel model) -{ - switch (model) - { - case MEMMODEL_ACQ_REL: - case MEMMODEL_SEQ_CST: - case MEMMODEL_RELEASE: - return true; - - case MEMMODEL_ACQUIRE: - case MEMMODEL_CONSUME: - case MEMMODEL_RELAXED: - return false; - - default: - gcc_unreachable (); - } -} - /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are: 'h' Print the high-part relocation associated with OP, after stripping @@ -3401,7 +3378,6 @@ riscv_memmodel_needs_release_fence (const enum memmodel model) 'R' Print the low-part relocation associated with OP. 'C' Print the integer branch condition for comparison OP. 'A' Print the atomic operation suffix for memory model OP. - 'F' Print a FENCE if the memory model requires a release. 'z' Print x0 if OP is zero, otherwise print OP normally. 'i' Print i if the operand is not a register. */ @@ -3433,11 +3409,6 @@ riscv_print_operand (FILE *file, rtx op, int letter) riscv_print_amo_memory_ordering_suffix (file, model); break; - case 'F': - if (riscv_memmodel_needs_release_fence (model)) - fputs ("fence iorw,ow; ", file); - break; - case 'i': if (code != REG) fputs ("i", file); diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 747a799e2377..aeeb2e854b68 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -65,7 +65,7 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] "TARGET_ATOMIC" - "%F2amoswap.%A2 zero,%z1,%0" + "amoswap.%A2 zero,%z1,%0" [(set (attr "length") (const_int 8))]) (define_insn "atomic_" @@ -76,8 +76,8 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F2amo.%A2 zero,%z1,%0" - [(set (attr "length") (const_int 8))]) + "amo.%A2 zero,%z1,%0" +) (define_insn "atomic_fetch_" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -89,8 +89,8 @@ (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F3amo.%A3 %0,%z2,%1" - [(set (attr "length") (const_int 8))]) + "amo.%A3 %0,%z2,%1" +) (define_insn "atomic_exchange" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -101,8 +101,8 @@ (set (match_dup 1) (match_operand:GPR 2 "register_operand" "0"))] "TARGET_ATOMIC" - "%F3amoswap.%A3 %0,%z2,%1" - [(set (attr "length") (const_int 8))]) + "amoswap.%A3 %0,%z2,%1" +) (define_insn "atomic_cas_value_strong" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -115,7 +115,7 @@ UNSPEC_COMPARE_AND_SWAP)) (clobber (match_scratch:GPR 6 "=&r"))] "TARGET_ATOMIC" - "%F5 1: lr.%A5 %0,%1; bne %0,%z2,1f; sc.%A4 %6,%z3,%1; bnez %6,1b; 1:" + "1: lr.%A5 %0,%1; bne %0,%z2,1f; sc.%A4 %6,%z3,%1; bnez %6,1b; 1:" [(set (attr "length") (const_int 20))]) (define_expand "atomic_compare_and_swap" -- 2.31.1