From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-f42.google.com (mail-ed1-f42.google.com [209.85.208.42]) by sourceware.org (Postfix) with ESMTPS id 3C8BB383F412; Wed, 5 May 2021 19:37:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 3C8BB383F412 Received: by mail-ed1-f42.google.com with SMTP id di13so3403521edb.2; Wed, 05 May 2021 12:37:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xYPWDGbqPd5v4IzvxFqtSfKwuD0I4AtxaZQD68up5ow=; b=jz3ok5T3G7Veqv9bUZoz3WivhOql86YSWpL/4pRuPg4ttxMU1WoATe/J7LjVka203I NQVIXhACh0VYLyCnA6QRVIPUBWkmQ5zHEr0eHunuM7mVEqMoPS/kpgotprvAwB5py8RT hXWr35BkinZATxvqjydnh69OBKncIBc5faW4CFMKC7wDRX3Rt43+1IZRxFQEfYoCnhwL Y/aKo5jzJTk/xfs9jMIKIXM7WSwCW9I0+o2qlox4g5da5UUpAYNFur5Iqa/qjRNKkGrR VX8oZ1Zeq4vh9fXYllTU+3VH576vTC6l4xcLdyP932yz8sL0H4InUxe2wSItqYtc422X NZnQ== X-Gm-Message-State: AOAM531qeMn3hSd2i9o/9rZdHTmUO3J0PIccCR7TpxFwcU2NkT1XI0hV jO3nYOyFzo5dyTg8Q9HWDtstLbAJyPVIJnbZ X-Google-Smtp-Source: ABdhPJzQbtxkMcWJv+SLYbvPM+asMPaMF1ZF9F8vyvU/XrWTrldtUPk84bxEKfL6JXVtYSo7PGDlYQ== X-Received: by 2002:a05:6402:c7:: with SMTP id i7mr724136edu.194.1620243425119; Wed, 05 May 2021 12:37:05 -0700 (PDT) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id t7sm60531eds.26.2021.05.05.12.37.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 12:37:04 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org Cc: Jim Wilson , Kito Cheng , Christoph Muellner Subject: [PATCH v2 06/10] RISC-V: Implement atomic_{load,store} [PR 100265] Date: Wed, 5 May 2021 21:36:47 +0200 Message-Id: <20210505193651.2075405-7-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> References: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 05 May 2021 19:37:07 -0000 A recent commit introduced a mechanism to emit proper fences for RISC-V. Additionally, we already have emit_move_insn (). Let's reuse this code and provide atomic_load and atomic_store for RISC-V (as defined in section "Code Porting and Mapping Guidelines" of the unpriv spec). Note, that this works also for sub-word atomics. gcc/ PR 100265 * config/riscv/sync.md (atomic_load): New. * config/riscv/sync.md (atomic_store): New. --- gcc/config/riscv/sync.md | 41 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 406db1730b81..ceec324dfa30 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -23,6 +23,7 @@ UNSPEC_COMPARE_AND_SWAP UNSPEC_SYNC_OLD_OP UNSPEC_SYNC_EXCHANGE + UNSPEC_ATOMIC_LOAD UNSPEC_ATOMIC_STORE UNSPEC_MEMORY_BARRIER ]) @@ -72,6 +73,46 @@ ;; Atomic memory operations. +(define_expand "atomic_load" + [(set (match_operand:ANYI 0 "register_operand" "=r") + (unspec_volatile:ANYI + [(match_operand:ANYI 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_LOAD))] + "" + { + rtx target = operands[0]; + rtx mem = operands[1]; + enum memmodel model = memmodel_from_int (INTVAL (operands[2])); + + if (is_mm_seq_cst (model)) + emit_insn (gen_mem_fence (GEN_INT (MEMMODEL_SEQ_CST))); + emit_move_insn (target, mem); + if (is_mm_acquire (model) || is_mm_seq_cst (model)) + emit_insn (gen_mem_fence (GEN_INT (MEMMODEL_ACQUIRE))); + + DONE; +}) + +(define_expand "atomic_store" + [(set (match_operand:ANYI 0 "memory_operand" "=A") + (unspec_volatile:ANYI + [(match_operand:ANYI 1 "reg_or_0_operand" "rJ") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_STORE))] + "" + { + rtx mem = operands[0]; + rtx val = operands[1]; + enum memmodel model = memmodel_from_int (INTVAL (operands[2])); + + if (is_mm_release (model) || is_mm_seq_cst (model)) + emit_insn (gen_mem_fence (GEN_INT (MEMMODEL_RELEASE))); + emit_move_insn (mem, val); + + DONE; +}) + (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") (unspec_volatile:GPR -- 2.31.1