From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) by sourceware.org (Postfix) with ESMTPS id 16FEA3A4E874; Wed, 5 May 2021 19:37:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 16FEA3A4E874 Received: by mail-ed1-f52.google.com with SMTP id di13so3403561edb.2; Wed, 05 May 2021 12:37:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t6h3epVgaxOG5CWl/ju2RUwxI/ZhYGDQL2iqOZ/FkU0=; b=aAtWm8w7rvBlIG4PXosKyVw4GsgnoIYv91hs9wtrAFleiAH+oFwxw1Rh952EuYp9ig TLdN5bQTmJR2IBj97ui3u3f6kNh+r7naNhmeGcnQm61j/kw2HMrki3T6yGpTpmwzue/0 YQSOgG4KPmwmYixZEB7VRZ/tY3bt3AYD5zE/EYEdxtnUlAiykJ7/6CeVMG0rFIj/hrta bTKIwMtI0tegxGtYX9MT2pUjBv/XbBmulDqE7NKDSLRz7hqm82kEsAxrFS6qGvlUau4O f23Otofm4MrRqY0Gk7ytRZcMX9WbXq7J3KFk9QF5MJa2KbDRnZJXgJM7GIJpTrpCZxql 7i0g== X-Gm-Message-State: AOAM530i2tt/OrXYwUTC8g14CKqE/fhTAYT3MWW9ZIqeGqg4ew/HSyQ2 bsA+zUSIzVa9w+KGvlP6P1LgJh0dty370mda X-Google-Smtp-Source: ABdhPJwSO6N3q8eDV3WvUTsLpXCRiAsZz6Baaw5A7OKdOZ8mKMTBS09Eidkx4A6SfB2nm/yrLWrq/g== X-Received: by 2002:a05:6402:485:: with SMTP id k5mr669779edv.211.1620243425939; Wed, 05 May 2021 12:37:05 -0700 (PDT) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id t7sm60531eds.26.2021.05.05.12.37.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 12:37:05 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org Cc: Jim Wilson , Kito Cheng , Christoph Muellner Subject: [PATCH v2 07/10] RISC-V: Model INSNs for LR and SC [PR 100266] Date: Wed, 5 May 2021 21:36:48 +0200 Message-Id: <20210505193651.2075405-8-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> References: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 05 May 2021 19:37:08 -0000 In order to emit LR/SC sequences, let's provide INSNs, which take care of memory ordering constraints. gcc/ PR 100266 * config/rsicv/sync.md (UNSPEC_LOAD_RESERVED): New. * config/rsicv/sync.md (UNSPEC_STORE_CONDITIONAL): New. * config/riscv/sync.md (riscv_load_reserved): New. * config/riscv/sync.md (riscv_store_conditional): New. --- gcc/config/riscv/sync.md | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index ceec324dfa30..edff6520b87e 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -26,6 +26,8 @@ UNSPEC_ATOMIC_LOAD UNSPEC_ATOMIC_STORE UNSPEC_MEMORY_BARRIER + UNSPEC_LOAD_RESERVED + UNSPEC_STORE_CONDITIONAL ]) (define_code_iterator any_atomic [plus ior xor and]) @@ -113,6 +115,28 @@ DONE; }) +(define_insn "@riscv_load_reserved" + [(set (match_operand:GPR 0 "register_operand" "=r") + (unspec_volatile:GPR + [(match_operand:GPR 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_LOAD_RESERVED))] + "TARGET_ATOMIC" + "lr.%A2 %0, %1" +) + +(define_insn "@riscv_store_conditional" + [(set (match_operand:GPR 0 "register_operand" "=&r") + (unspec_volatile:GPR [(const_int 0)] UNSPEC_STORE_CONDITIONAL)) + (set (match_operand:GPR 1 "memory_operand" "=A") + (unspec_volatile:GPR + [(match_operand:GPR 2 "reg_or_0_operand" "rJ") + (match_operand:SI 3 "const_int_operand")] ;; model + UNSPEC_STORE_CONDITIONAL))] + "TARGET_ATOMIC" + "sc.%A3 %0, %z2, %1" +) + (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") (unspec_volatile:GPR -- 2.31.1