[PATCH 2/2] Fix tests when running on power10, PR testsuite/100166

[Michael Meissner <meissner@linux.ibm.com>]

[PATCH 2/2] Fix tests when running on power10, PR testsuite/100166

This patch updates the various tests in the testsuite to adjust the test
if power10 code generation is used.

Some tests would not generate the expected instructions because power10
provides new instructions that the compiler now generates.  These tests are
adjusted to use '#pragma GCC target ("cpu=power9"), or the new instructions
were added to regex.

One test was checking for 64-bit TOC calls, and it was adjusted to also allow
PC-relative calls.

I have bootstraped this on LE power9 and BE power8 systems.  There were no
regressions in the tests.  Can I check this into the trunk?

I would like to back port these patches to GCC 11 after a cooling off period.
Is that ok?

gcc/testsuite/
2021-05-18  Michael Meissner  <meissner@linux.ibm.com>

	PR testsuite/100166
	* gcc.dg/pr56727-2.c: Add support for PC-relative calls.
	* gcc.target/powerpc/fold-vec-div-longlong.c:
	* gcc.target/powerpc/fold-vec-mult-longlong.c: Disable power10
	code generation.
	* gcc.target/powerpc/ppc-eq0-1.c: Add support for the setbc
	instruction.
	* gcc.target/powerpc/ppc-ne0-1.c: Disable power10 code
	generation.
---
 gcc/testsuite/gcc.dg/pr56727-2.c                          | 2 +-
 gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c  | 7 +++++++
 gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c | 7 +++++++
 gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c              | 2 +-
 gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c              | 8 ++++++++
 5 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/pr56727-2.c b/gcc/testsuite/gcc.dg/pr56727-2.c
index c54369ed25e..77fdf4bc350 100644
--- a/gcc/testsuite/gcc.dg/pr56727-2.c
+++ b/gcc/testsuite/gcc.dg/pr56727-2.c
@@ -18,4 +18,4 @@ void h ()
 
 /* { dg-final { scan-assembler "@(PLT|plt)" { target i?86-*-* x86_64-*-* } } } */
 /* { dg-final { scan-assembler "@(PLT|plt)" { target { powerpc*-*-linux* && ilp32 } } } } */
-/* { dg-final { scan-assembler "bl f\n\\s*nop" { target { powerpc*-*-linux* && lp64 } } } } */
+/* { dg-final { scan-assembler "(bl f\n\\s*nop)|(bl f@notoc)" { target { powerpc*-*-linux* && lp64 } } } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
index 312e984d3cc..1d20b7ff100 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
@@ -6,6 +6,13 @@
 /* { dg-require-effective-target lp64 } */
 /* { dg-options "-mvsx -O2" } */
 
+/* If the compiler was configured to automatically generate power10 support with
+   --with-cpu=power10, turn it off.  Otherwise, it will generate VDIVSD and
+   VDIVUD instructions.  */
+#ifdef _ARCH_PWR10
+#pragma GCC target ("cpu=power9")
+#endif
+
 #include <altivec.h>
 
 vector signed long long
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c
index 38dba9f5023..7510dc5c7a7 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c
@@ -6,6 +6,13 @@
 /* { dg-options "-maltivec -mvsx -mpower8-vector" } */
 /* { dg-additional-options "-maix64" { target powerpc-ibm-aix* } } */
 
+/* If the compiler was configured to automatically generate power10 support with
+   --with-cpu=power10, turn it off.  Otherwise, it will generate VMULLD
+   instructions.  */
+#ifdef _ARCH_PWR10
+#pragma GCC target ("cpu=power9")
+#endif
+
 #include <altivec.h>
 
 vector signed long long
diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c
index 496a6e340c0..2ddf03117ab 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c
@@ -7,4 +7,4 @@ int foo(int x)
   return x == 0;
 }
 
-/* { dg-final { scan-assembler "cntlzw|isel" } } */
+/* { dg-final { scan-assembler "cntlzw|isel|setbc" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c
index 63c4b6087df..bf777979833 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c
@@ -2,6 +2,14 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -mno-isel" } */
 
+/* If the compiler was configured to automatically generate power10 support with
+   --with-cpu=power10, turn it off.  Otherwise, it will generate a SETBCR
+   instruction instead of ADDIC/SUBFE.  */
+
+#ifdef _ARCH_PWR10
+#pragma GCC target ("cpu=power9")
+#endif
+
 /* { dg-final { scan-assembler-times "addic" 4 } } */
 /* { dg-final { scan-assembler-times "subfe" 1 } } */
 /* { dg-final { scan-assembler-times "addze" 3 } } */
-- 
2.31.1


-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797