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[148.251.136.42]) by smtp.gmail.com with ESMTPSA id k6sm10064081wmi.42.2021.05.27.04.21.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 May 2021 04:21:30 -0700 (PDT) From: Christophe Lyon To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [PATCH] arm: Auto-vectorization for MVE: vabs Date: Thu, 27 May 2021 11:21:28 +0000 Message-Id: <20210527112128.26343-1-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-14.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 27 May 2021 11:21:34 -0000 This patch adds support for auto-vectorization of absolute value computation using vabs. We use a similar pattern to what is used in neon.md and extend the existing neg2 expander to match both 'neg' and 'abs'. This implies renaming the existing abs2 define_insn in neon.md to avoid a clash with the new expander with the same name. 2021-05-26 Christophe Lyon gcc/ * config/arm/mve.md (mve_vabsq_f): Use 'abs' instead of unspec. (mve_vabsq_s): Likewise. * config/arm/neon.md (abs2): Rename to neon_abs2. * config/arm/unspecs.md (VABSQ_F, VABSQ_S): Delete. * config/arm/vec-common.md (neg2): Rename to 2. gcc/testsuite/ * gcc.target/arm/simd/mve-vabs.c: New test. --- gcc/config/arm/mve.md | 6 +-- gcc/config/arm/neon.md | 2 +- gcc/config/arm/unspecs.md | 2 - gcc/config/arm/vec-common.md | 4 +- gcc/testsuite/gcc.target/arm/simd/mve-vabs.c | 44 ++++++++++++++++++++ 5 files changed, 49 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vabs.c diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 0a6ba80c99d..0bfa6a91d55 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -269,8 +269,7 @@ (define_insn "mve_vdupq_n_f" (define_insn "mve_vabsq_f" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] - VABSQ_F)) + (abs:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vabs.f%# %q0, %q1" @@ -481,8 +480,7 @@ (define_insn "@mve_vaddvq_" (define_insn "mve_vabsq_s" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] - VABSQ_S)) + (abs:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE" "vabs.s%#\t%q0, %q1" diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 6a6573317cf..077c62ffd20 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -739,7 +739,7 @@ (define_insn "one_cmpl2_neon" [(set_attr "type" "neon_move")] ) -(define_insn "abs2" +(define_insn "neon_abs2" [(set (match_operand:VDQW 0 "s_register_operand" "=w") (abs:VDQW (match_operand:VDQW 1 "s_register_operand" "w")))] "TARGET_NEON" diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index 0778db1bf4f..ed1bc293b78 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -538,7 +538,6 @@ (define_c_enum "unspec" [ VRNDAQ_F VREV64Q_F VDUPQ_N_F - VABSQ_F VREV32Q_F VCVTTQ_F32_F16 VCVTBQ_F32_F16 @@ -562,7 +561,6 @@ (define_c_enum "unspec" [ VCLSQ_S VADDVQ_S VADDVQ_U - VABSQ_S VREV32Q_U VREV32Q_S VMOVLTQ_U diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 8e35151da46..80b273229f5 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -208,9 +208,9 @@ (define_expand "one_cmpl2" "ARM_HAVE__ARITH && !TARGET_REALLY_IWMMXT" ) -(define_expand "neg2" +(define_expand "2" [(set (match_operand:VDQWH 0 "s_register_operand" "") - (neg:VDQWH (match_operand:VDQWH 1 "s_register_operand" "")))] + (ABSNEG:VDQWH (match_operand:VDQWH 1 "s_register_operand" "")))] "ARM_HAVE__ARITH && !TARGET_REALLY_IWMMXT" ) diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vabs.c b/gcc/testsuite/gcc.target/arm/simd/mve-vabs.c new file mode 100644 index 00000000000..64cd1c2eb4a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vabs.c @@ -0,0 +1,44 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O3 -funsafe-math-optimizations" } */ + +#include +#include + +#define ABS(a) ((a < 0) ? -a : a) + +#define FUNC(SIGN, TYPE, BITS, NB, NAME) \ + void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, TYPE##BITS##_t *a) { \ + int i; \ + for (i=0; i