From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from esa4.mentor.iphmx.com (esa4.mentor.iphmx.com [68.232.137.252]) by sourceware.org (Postfix) with ESMTPS id 8CC733853838 for ; Tue, 22 Jun 2021 17:15:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8CC733853838 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com IronPort-SDR: CDV3fN9VmGqak3PtRLXEN5AS0QsTKiYTxJZrWY49MeevQ2D1aqiewqWKQKFRyg20SJn4d+btW+ RY7SpSv26b0RJS2BsFcvdmm5G7g/hUX7RIBaDF84OTwjj3HroqgZXFnkgD89w7wYgyb0FZx3L/ cQH2D/LTmUtxR/5OolrsOAxSopTsj2Jktw5CZWARd9+TAelsSGIyf9CnFibMV7Mex5AzAKJA3E C9rDeht0rpYYORGV2iJuBRgXy0ENf1hmX0ess3b9IgoVWjzPpirhfKOTS1X74JkC001w5ueZT2 CWA= X-IronPort-AV: E=Sophos;i="5.83,291,1616486400"; d="scan'208";a="62879913" Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa4.mentor.iphmx.com with ESMTP; 22 Jun 2021 09:14:58 -0800 IronPort-SDR: 3z+dwml6BNwlWWZxJVvZzVuPs/nOPBKeAjgEJsIsXY6hqGpZmkAQ2/6xeBlgMDZxNdpZr22N2m jYZkALlkBQ0yO6rIoPI245KUzzzEKSb/lnBPifrOfRRABWlLxgKcy9Dsg8JB0mkeM74APopf1v UKziHZt+2lgHyDODq9HSNBQkDz7ExoOxD0XIvwUTfmD+7mNaiVJ4RhUJ/MnIqYYGjaJvNPLdc1 906FoVnR3j0PFvIjYzLHYU4EJBQ/mSFUZEQI0L8cFrA65xTqPzCF8Jq58w8jlno8ef7bFsuVyT Xj0= From: Hafiz Abid Qadeer To: CC: , Subject: [PATCH 1/3] [amdgcn] Update CFI configuration Date: Tue, 22 Jun 2021 18:14:41 +0100 Message-ID: <20210622171443.1287801-2-abidh@codesourcery.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210622171443.1287801-1-abidh@codesourcery.com> References: <20210622171443.1287801-1-abidh@codesourcery.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: SVR-IES-MBX-04.mgc.mentorg.com (139.181.222.4) To SVR-IES-MBX-03.mgc.mentorg.com (139.181.222.3) X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Jun 2021 17:15:03 -0000 Currently we don't get any call frame information for the amdgcn target. This patch makes necessary adjustments to generate CFI that can work with ROCGDB (ROCm 3.8+). gcc/ * config/gcn/gcn.c (move_callee_saved_registers): Emit CFI notes for prologue register saves. (gcn_debug_unwind_info): Use UI_DWARF2. (gcn_dwarf_register_number): Map DWARF_LINK_REGISTER to DWARF PC. (gcn_dwarf_register_span): DWARF_LINK_REGISTER doesn't span. * config/gcn/gcn.h: (DWARF_FRAME_RETURN_COLUMN): New define. (DWARF_LINK_REGISTER): New define. (FIRST_PSEUDO_REGISTER): Increment. (FIXED_REGISTERS): Add entry for DWARF_LINK_REGISTER. (CALL_USED_REGISTERS): Likewise. (REGISTER_NAMES): Likewise. --- gcc/config/gcn/gcn.c | 82 ++++++++++++++++++++++++++++++++++++++++---- gcc/config/gcn/gcn.h | 10 +++--- 2 files changed, 81 insertions(+), 11 deletions(-) diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c index 283a91fe50a..3ab16548aad 100644 --- a/gcc/config/gcn/gcn.c +++ b/gcc/config/gcn/gcn.c @@ -2649,6 +2649,7 @@ move_callee_saved_registers (rtx sp, machine_function *offsets, rtx as = gen_rtx_CONST_INT (VOIDmode, STACK_ADDR_SPACE); HOST_WIDE_INT exec_set = 0; int offreg_set = 0; + auto_vec saved_sgprs; start_sequence (); @@ -2665,7 +2666,10 @@ move_callee_saved_registers (rtx sp, machine_function *offsets, int lane = saved_scalars % 64; if (prologue) - emit_insn (gen_vec_setv64si (vreg, reg, GEN_INT (lane))); + { + emit_insn (gen_vec_setv64si (vreg, reg, GEN_INT (lane))); + saved_sgprs.safe_push (regno); + } else emit_insn (gen_vec_extractv64sisi (reg, vreg, GEN_INT (lane))); @@ -2698,7 +2702,7 @@ move_callee_saved_registers (rtx sp, machine_function *offsets, gcn_gen_undef (V64SImode), exec)); /* Move vectors. */ - for (regno = FIRST_VGPR_REG, offset = offsets->pretend_size; + for (regno = FIRST_VGPR_REG, offset = 0; regno < FIRST_PSEUDO_REGISTER; regno++) if ((df_regs_ever_live_p (regno) && !call_used_or_fixed_reg_p (regno)) || (regno == VGPR_REGNO (6) && saved_scalars > 0) @@ -2719,8 +2723,67 @@ move_callee_saved_registers (rtx sp, machine_function *offsets, } if (prologue) - emit_insn (gen_scatterv64si_insn_1offset_exec (vsp, const0_rtx, reg, - as, const0_rtx, exec)); + { + rtx insn = emit_insn (gen_scatterv64si_insn_1offset_exec + (vsp, const0_rtx, reg, as, const0_rtx, + exec)); + + /* Add CFI metadata. */ + rtx note; + if (regno == VGPR_REGNO (6) || regno == VGPR_REGNO (7)) + { + int start = (regno == VGPR_REGNO (7) ? 64 : 0); + int count = MIN (saved_scalars - start, 64); + int add_lr = (regno == VGPR_REGNO (6) + && df_regs_ever_live_p (LINK_REGNUM)); + int lrdest = -1; + rtvec seq = rtvec_alloc (count + add_lr); + + /* Add an REG_FRAME_RELATED_EXPR entry for each scalar + register that was saved in this batch. */ + for (int idx = 0; idx < count; idx++) + { + int stackaddr = offset + idx * 4; + rtx dest = gen_rtx_MEM (SImode, + gen_rtx_PLUS + (DImode, sp, + GEN_INT (stackaddr))); + rtx src = gen_rtx_REG (SImode, saved_sgprs[start + idx]); + rtx set = gen_rtx_SET (dest, src); + RTX_FRAME_RELATED_P (set) = 1; + RTVEC_ELT (seq, idx) = set; + + if (saved_sgprs[start + idx] == LINK_REGNUM) + lrdest = stackaddr; + } + + /* Add an additional expression for DWARF_LINK_REGISTER if + LINK_REGNUM was saved. */ + if (lrdest != -1) + { + rtx dest = gen_rtx_MEM (DImode, + gen_rtx_PLUS + (DImode, sp, + GEN_INT (lrdest))); + rtx src = gen_rtx_REG (DImode, DWARF_LINK_REGISTER); + rtx set = gen_rtx_SET (dest, src); + RTX_FRAME_RELATED_P (set) = 1; + RTVEC_ELT (seq, count) = set; + } + + note = gen_rtx_SEQUENCE (VOIDmode, seq); + } + else + { + rtx dest = gen_rtx_MEM (V64SImode, + gen_rtx_PLUS (DImode, sp, + GEN_INT (offset))); + rtx src = gen_rtx_REG (V64SImode, regno); + note = gen_rtx_SET (dest, src); + } + RTX_FRAME_RELATED_P (insn) = 1; + add_reg_note (insn, REG_FRAME_RELATED_EXPR, note); + } else emit_insn (gen_gatherv64si_insn_1offset_exec (reg, vsp, const0_rtx, as, const0_rtx, @@ -3224,8 +3287,7 @@ gcn_cannot_copy_insn_p (rtx_insn *insn) static enum unwind_info_type gcn_debug_unwind_info () { - /* No support for debug info, yet. */ - return UI_NONE; + return UI_DWARF2; } /* Determine if there is a suitable hardware conversion instruction. @@ -6214,6 +6276,8 @@ gcn_dwarf_register_number (unsigned int regno) return 768; */ else if (regno == SCC_REG) return 128; + else if (regno == DWARF_LINK_REGISTER) + return 16; else if (SGPR_REGNO_P (regno)) { if (regno - FIRST_SGPR_REG < 64) @@ -6243,8 +6307,12 @@ gcn_dwarf_register_span (rtx rtl) if (GET_MODE_SIZE (mode) != 8) return NULL_RTX; - rtx p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2)); unsigned regno = REGNO (rtl); + + if (regno == DWARF_LINK_REGISTER) + return NULL_RTX; + + rtx p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2)); XVECEXP (p, 0, 0) = gen_rtx_REG (SImode, regno); XVECEXP (p, 0, 1) = gen_rtx_REG (SImode, regno + 1); diff --git a/gcc/config/gcn/gcn.h b/gcc/config/gcn/gcn.h index eba4646f1bf..4992a4c02ef 100644 --- a/gcc/config/gcn/gcn.h +++ b/gcc/config/gcn/gcn.h @@ -85,6 +85,7 @@ #define FIRST_PARM_OFFSET(FNDECL) 0 #define DYNAMIC_CHAIN_ADDRESS(FP) plus_constant (Pmode, (FP), -16) #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGNUM) +#define DWARF_FRAME_RETURN_COLUMN 16 #define STACK_DYNAMIC_OFFSET(FNDECL) (-crtl->outgoing_args_size) #define ACCUMULATE_OUTGOING_ARGS 1 #define RETURN_ADDR_RTX(COUNT,FRAMEADDR) \ @@ -135,7 +136,8 @@ #define WORK_ITEM_ID_Z_REG 162 #define SOFT_ARG_REG 416 #define FRAME_POINTER_REGNUM 418 -#define FIRST_PSEUDO_REGISTER 420 +#define DWARF_LINK_REGISTER 420 +#define FIRST_PSEUDO_REGISTER 421 #define FIRST_PARM_REG 24 #define NUM_PARM_REGS 6 @@ -197,7 +199,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ /* Other registers. */ \ - 1, 1, 1, 1 \ + 1, 1, 1, 1, 1 \ } #define CALL_USED_REGISTERS { \ @@ -235,7 +237,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ /* Other registers. */ \ - 1, 1, 1, 1 \ + 1, 1, 1, 1, 1 \ } @@ -514,7 +516,7 @@ enum gcn_address_spaces "v236", "v237", "v238", "v239", "v240", "v241", "v242", "v243", "v244", \ "v245", "v246", "v247", "v248", "v249", "v250", "v251", "v252", "v253", \ "v254", "v255", \ - "?ap0", "?ap1", "?fp0", "?fp1" } + "?ap0", "?ap1", "?fp0", "?fp1", "?dwlr" } #define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE, X, CODE) #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) -- 2.25.1