From: Jojo R <rjiejie@linux.alibaba.com>
To: gcc-patches@gcc.gnu.org
Cc: Jojo R <rjiejie@linux.alibaba.com>
Subject: [PATCH 1/2] RISC-V: Add arch flags for T-HEAD.
Date: Tue, 29 Jun 2021 16:11:06 +0800 [thread overview]
Message-ID: <20210629081107.28391-2-rjiejie@linux.alibaba.com> (raw)
In-Reply-To: <20210629081107.28391-1-rjiejie@linux.alibaba.com>
gcc/
* gcc/config/riscv/riscv.opt (riscv_x_subext): New.
* gcc/config/riscv/riscv-opts.h (MASK_XTHEAD_C): New.
(TARGET_XTHEAD_C): Likewise.
* gcc/common/config/riscv/riscv-common.c
(riscv_ext_flag_table): Use riscv_x_subext & MASK_XTHEAD_C.
---
gcc/common/config/riscv/riscv-common.c | 2 ++
gcc/config/riscv/riscv-opts.h | 3 +++
gcc/config/riscv/riscv.opt | 3 +++
3 files changed, 8 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
index 10868fd417dc..a62080129259 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -906,6 +906,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
{"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
+ {"xtheadc", &gcc_options::x_riscv_x_subext, MASK_XTHEAD_C},
+
{NULL, NULL, 0}
};
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index f4cf6ca4b823..a2d84a66f037 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -73,4 +73,7 @@ enum stack_protector_guard {
#define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0)
#define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
+#define MASK_XTHEAD_C (1 << 0)
+#define TARGET_XTHEAD_C ((riscv_x_subext & MASK_XTHEAD_C) != 0)
+
#endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 5ff85c214307..84176aea05e9 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -195,6 +195,9 @@ long riscv_stack_protector_guard_offset = 0
TargetVariable
int riscv_zi_subext
+TargetVariable
+int riscv_x_subext
+
Enum
Name(isa_spec_class) Type(enum riscv_isa_spec_class)
Supported ISA specs (for use with the -misa-spec= option):
--
2.24.3 (Apple Git-128)
next prev parent reply other threads:[~2021-06-29 8:11 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-29 8:11 [PATCH 0/2] RISC-V: Add ldr/str instruction " Jojo R
2021-06-29 8:11 ` Jojo R [this message]
2021-07-13 18:06 ` [PATCH 1/2] RISC-V: Add arch flags " Palmer Dabbelt
2021-07-21 20:53 ` Jim Wilson
2021-07-22 2:16 ` Jojo R
2021-08-27 3:22 ` Jojo R
2021-06-29 8:11 ` [PATCH 2/2] RISC-V: Add ldr/str instruction " Jojo R
2021-07-13 18:06 ` Palmer Dabbelt
2021-07-09 1:30 ` [PATCH 0/2] " ALO
2021-07-11 2:31 ` ALO
2021-07-13 18:06 ` Palmer Dabbelt
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