From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id 6BB6D384F02A for ; Thu, 1 Jul 2021 06:17:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6BB6D384F02A X-IronPort-AV: E=McAfee;i="6200,9189,10031"; a="205474477" X-IronPort-AV: E=Sophos;i="5.83,313,1616482800"; d="scan'208";a="205474477" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2021 23:17:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,313,1616482800"; d="scan'208";a="455498329" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga008.jf.intel.com with ESMTP; 30 Jun 2021 23:17:38 -0700 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.236.50]) by scymds01.sc.intel.com with ESMTP id 1616Gmf8031625; Wed, 30 Jun 2021 23:17:36 -0700 From: liuhongt To: gcc-patches@gcc.gnu.org Cc: crazylht@gmail.com, hjl.tools@gmail.com, ubizjak@gmail.com, jakub@redhat.com Subject: [PATCH 29/62] AVX512FP16: Add testcase for vcvtw2ph/vcvtuw2ph/vcvtdq2ph/vcvtudq2ph/vcvtqq2ph/vcvtuqq2ph. Date: Thu, 1 Jul 2021 14:16:15 +0800 Message-Id: <20210701061648.9447-30-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20210701061648.9447-1-hongtao.liu@intel.com> References: <20210701061648.9447-1-hongtao.liu@intel.com> X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Jul 2021 06:17:43 -0000 gcc/testsuite/ChangeLog: * gcc.target/i386/avx512fp16-vcvtdq2ph-1a.c: New test. * gcc.target/i386/avx512fp16-vcvtdq2ph-1b.c: Ditto. * gcc.target/i386/avx512fp16-vcvtqq2ph-1a.c: Ditto. * gcc.target/i386/avx512fp16-vcvtqq2ph-1b.c: Ditto. * gcc.target/i386/avx512fp16-vcvtudq2ph-1a.c: Ditto. * gcc.target/i386/avx512fp16-vcvtudq2ph-1b.c: Ditto. * gcc.target/i386/avx512fp16-vcvtuqq2ph-1a.c: Ditto. * gcc.target/i386/avx512fp16-vcvtuqq2ph-1b.c: Ditto. * gcc.target/i386/avx512fp16-vcvtuw2ph-1a.c: Ditto. * gcc.target/i386/avx512fp16-vcvtuw2ph-1b.c: Ditto. * gcc.target/i386/avx512fp16-vcvtw2ph-1a.c: Ditto. * gcc.target/i386/avx512fp16-vcvtw2ph-1b.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtdq2ph-1a.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtdq2ph-1b.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtqq2ph-1a.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtqq2ph-1b.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtudq2ph-1a.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtudq2ph-1b.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1a.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1b.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtuw2ph-1a.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtuw2ph-1b.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtw2ph-1a.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtw2ph-1b.c: Ditto. --- .../gcc.target/i386/avx512fp16-vcvtdq2ph-1a.c | 24 +++++ .../gcc.target/i386/avx512fp16-vcvtdq2ph-1b.c | 79 ++++++++++++++++ .../gcc.target/i386/avx512fp16-vcvtqq2ph-1a.c | 24 +++++ .../gcc.target/i386/avx512fp16-vcvtqq2ph-1b.c | 84 +++++++++++++++++ .../i386/avx512fp16-vcvtudq2ph-1a.c | 24 +++++ .../i386/avx512fp16-vcvtudq2ph-1b.c | 79 ++++++++++++++++ .../i386/avx512fp16-vcvtuqq2ph-1a.c | 24 +++++ .../i386/avx512fp16-vcvtuqq2ph-1b.c | 83 +++++++++++++++++ .../gcc.target/i386/avx512fp16-vcvtuw2ph-1a.c | 24 +++++ .../gcc.target/i386/avx512fp16-vcvtuw2ph-1b.c | 93 +++++++++++++++++++ .../gcc.target/i386/avx512fp16-vcvtw2ph-1a.c | 24 +++++ .../gcc.target/i386/avx512fp16-vcvtw2ph-1b.c | 92 ++++++++++++++++++ .../i386/avx512fp16vl-vcvtdq2ph-1a.c | 27 ++++++ .../i386/avx512fp16vl-vcvtdq2ph-1b.c | 15 +++ .../i386/avx512fp16vl-vcvtqq2ph-1a.c | 28 ++++++ .../i386/avx512fp16vl-vcvtqq2ph-1b.c | 15 +++ .../i386/avx512fp16vl-vcvtudq2ph-1a.c | 27 ++++++ .../i386/avx512fp16vl-vcvtudq2ph-1b.c | 15 +++ .../i386/avx512fp16vl-vcvtuqq2ph-1a.c | 28 ++++++ .../i386/avx512fp16vl-vcvtuqq2ph-1b.c | 15 +++ .../i386/avx512fp16vl-vcvtuw2ph-1a.c | 29 ++++++ .../i386/avx512fp16vl-vcvtuw2ph-1b.c | 15 +++ .../i386/avx512fp16vl-vcvtw2ph-1a.c | 29 ++++++ .../i386/avx512fp16vl-vcvtw2ph-1b.c | 15 +++ 24 files changed, 912 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtdq2ph-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtdq2ph-1b.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtqq2ph-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtqq2ph-1b.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtudq2ph-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtudq2ph-1b.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuqq2ph-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuqq2ph-1b.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuw2ph-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuw2ph-1b.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtw2ph-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtw2ph-1b.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtdq2ph-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtdq2ph-1b.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtqq2ph-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtqq2ph-1b.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtudq2ph-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtudq2ph-1b.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1b.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuw2ph-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuw2ph-1b.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtw2ph-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtw2ph-1b.c diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtdq2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtdq2ph-1a.c new file mode 100644 index 00000000000..45697d94b1c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtdq2ph-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtdq2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2ph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2ph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m256h res, res1, res2; +volatile __m512i x1, x2, x3; +volatile __mmask16 m16; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtepi32_ph (x1); + res1 = _mm512_mask_cvtepi32_ph (res, m16, x2); + res2 = _mm512_maskz_cvtepi32_ph (m16, x3); + res = _mm512_cvt_roundepi32_ph (x1, 4); + res1 = _mm512_mask_cvt_roundepi32_ph (res, m16, x2, 8); + res2 = _mm512_maskz_cvt_roundepi32_ph (m16, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtdq2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtdq2ph-1b.c new file mode 100644 index 00000000000..a2bb56c25d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtdq2ph-1b.c @@ -0,0 +1,79 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 32) + +void NOINLINE +EMULATE(cvtd2_ph) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + v5.f32[i] = op1.u32[i]; + } + } + *dest = pack_twops_2ph(v5, v5); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtd2_ph)(&exp, src3, NET_MASK, 0); + H_HF(res) = INTRINSIC (_cvtepi32_ph) (SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtepi32_ph); + + init_dest(&res, &exp); + EMULATE(cvtd2_ph)(&exp, src3, HALF_MASK, 0); + H_HF(res) = INTRINSIC (_mask_cvtepi32_ph) (H_HF(res), HALF_MASK, SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtepi32_ph); + + EMULATE(cvtd2_ph)(&exp, src3, HALF_MASK, 1); + H_HF(res) = INTRINSIC (_maskz_cvtepi32_ph) (HALF_MASK, SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtepi32_ph); + +#if AVX512F_LEN == 512 + EMULATE(cvtd2_ph)(&exp, src3, NET_MASK, 0); + H_HF(res) = INTRINSIC (_cvt_roundepi32_ph) (SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvt_roundepi32_ph); + + init_dest(&res, &exp); + EMULATE(cvtd2_ph)(&exp, src3, HALF_MASK, 0); + H_HF(res) = INTRINSIC (_mask_cvt_roundepi32_ph) (H_HF(res), HALF_MASK, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvt_roundepi32_ph); + + EMULATE(cvtd2_ph)(&exp, src3, HALF_MASK, 1); + H_HF(res) = INTRINSIC (_maskz_cvt_roundepi32_ph) (HALF_MASK, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvt_roundepi32_ph); +#endif + + if (n_errs != 0) { + abort (); + } +} + + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtqq2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtqq2ph-1a.c new file mode 100644 index 00000000000..4e8515e9a3d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtqq2ph-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtqq2phz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2phz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2phz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2ph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2ph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m128h res, res1, res2; +volatile __m512i x1, x2, x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtepi64_ph (x1); + res1 = _mm512_mask_cvtepi64_ph (res, m8, x2); + res2 = _mm512_maskz_cvtepi64_ph (m8, x3); + res = _mm512_cvt_roundepi64_ph (x1, 4); + res1 = _mm512_mask_cvt_roundepi64_ph (res, m8, x2, 8); + res2 = _mm512_maskz_cvt_roundepi64_ph (m8, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtqq2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtqq2ph-1b.c new file mode 100644 index 00000000000..cb213b9d9f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtqq2ph-1b.c @@ -0,0 +1,84 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 64) + +void NOINLINE +EMULATE(cvtq2_ph) (V512 * dest, V512 op1, int n_el, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < n_el; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + v5.f32[i] = op1.u64[i]; + } + } + + // The left part should be zero + for (i = n_el; i < 16; i++) + v5.f32[i] = 0; + + *dest = pack_twops_2ph(v5, v5); +} + +void +TEST (void) +{ + + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, NET_MASK, 0); + res.xmmh[0] = INTRINSIC (_cvtepi64_ph) (SI(src3)); + CHECK_RESULT (&res, &exp, 8, _cvtepi64_ph); + + init_dest(&res, &exp); + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, 0xcc, 0); + res.xmmh[0] = INTRINSIC (_mask_cvtepi64_ph) (res.xmmh[0], 0xcc, SI(src3)); + CHECK_RESULT (&res, &exp, 8, _mask_cvtepi64_ph); + + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, 0xf1, 1); + res.xmmh[0] = INTRINSIC (_maskz_cvtepi64_ph) (0xf1, SI(src3)); + CHECK_RESULT (&res, &exp, 8, _maskz_cvtepi64_ph); + +#if AVX512F_LEN == 512 + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, NET_MASK, 0); + res.xmmh[0] = INTRINSIC (_cvt_roundepi64_ph) (SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, 8, _cvt_roundepi64_ph); + + init_dest(&res, &exp); + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, 0xcc, 0); + res.xmmh[0] = INTRINSIC (_mask_cvt_roundepi64_ph) (res.xmmh[0], 0xcc, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, 8, _mask_cvt_roundepi64_ph); + + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, 0xf1, 1); + res.xmmh[0] = INTRINSIC (_maskz_cvt_roundepi64_ph) (0xf1, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, 8, _maskz_cvt_roundepi64_ph); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtudq2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtudq2ph-1a.c new file mode 100644 index 00000000000..8d90ef6f168 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtudq2ph-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtudq2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtudq2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtudq2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtudq2ph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtudq2ph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m256h res, res1, res2; +volatile __m512i x1, x2, x3; +volatile __mmask16 m16; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtepu32_ph (x1); + res1 = _mm512_mask_cvtepu32_ph (res, m16, x2); + res2 = _mm512_maskz_cvtepu32_ph (m16, x3); + res = _mm512_cvt_roundepu32_ph (x1, 4); + res1 = _mm512_mask_cvt_roundepu32_ph (res, m16, x2, 8); + res2 = _mm512_maskz_cvt_roundepu32_ph (m16, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtudq2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtudq2ph-1b.c new file mode 100644 index 00000000000..e9c1cd1bcb0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtudq2ph-1b.c @@ -0,0 +1,79 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 32) + +void NOINLINE +EMULATE(cvtd2_ph) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + v5.f32[i] = op1.u32[i]; + } + } + *dest = pack_twops_2ph(v5, v5); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtd2_ph)(&exp, src3, NET_MASK, 0); + H_HF(res)= INTRINSIC (_cvtepu32_ph) (SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtepu32_ph); + + init_dest(&res, &exp); + EMULATE(cvtd2_ph)(&exp, src3, HALF_MASK, 0); + H_HF(res) = INTRINSIC (_mask_cvtepu32_ph) (H_HF(res), HALF_MASK, SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtepu32_ph); + + EMULATE(cvtd2_ph)(&exp, src3, HALF_MASK, 1); + H_HF(res) = INTRINSIC (_maskz_cvtepu32_ph) (HALF_MASK, SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtepu32_ph); + +#if AVX512F_LEN == 512 + EMULATE(cvtd2_ph)(&exp, src3, NET_MASK, 0); + H_HF(res)= INTRINSIC (_cvt_roundepu32_ph) (SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvt_roundepu32_ph); + + init_dest(&res, &exp); + EMULATE(cvtd2_ph)(&exp, src3, HALF_MASK, 0); + H_HF(res) = INTRINSIC (_mask_cvt_roundepu32_ph) (H_HF(res), HALF_MASK, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvt_roundepu32_ph); + + EMULATE(cvtd2_ph)(&exp, src3, HALF_MASK, 1); + H_HF(res) = INTRINSIC (_maskz_cvt_roundepu32_ph) (HALF_MASK, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvt_roundepu32_ph); +#endif + + if (n_errs != 0) { + abort (); + } +} + + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuqq2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuqq2ph-1a.c new file mode 100644 index 00000000000..a234bb50482 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuqq2ph-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtuqq2phz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtuqq2phz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuqq2phz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuqq2ph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuqq2ph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m128h res, res1, res2; +volatile __m512i x1, x2, x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtepu64_ph (x1); + res1 = _mm512_mask_cvtepu64_ph (res, m8, x2); + res2 = _mm512_maskz_cvtepu64_ph (m8, x3); + res = _mm512_cvt_roundepu64_ph (x1, 4); + res1 = _mm512_mask_cvt_roundepu64_ph (res, m8, x2, 8); + res2 = _mm512_maskz_cvt_roundepu64_ph (m8, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuqq2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuqq2ph-1b.c new file mode 100644 index 00000000000..873d9109e47 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuqq2ph-1b.c @@ -0,0 +1,83 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 64) + +void NOINLINE +EMULATE(cvtq2_ph) (V512 * dest, V512 op1, int n_el, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < n_el; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + v5.f32[i] = op1.u64[i]; + } + } + + // The left part should be zero + for (i = n_el; i < 16; i++) + v5.f32[i] = 0; + + *dest = pack_twops_2ph(v5, v5); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, NET_MASK, 0); + res.xmmh[0] = INTRINSIC (_cvtepu64_ph) (SI(src3)); + CHECK_RESULT (&res, &exp, 8, _cvtepu64_ph); + + init_dest(&res, &exp); + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, 0xcc, 0); + res.xmmh[0] = INTRINSIC (_mask_cvtepu64_ph) (res.xmmh[0], 0xcc, SI(src3)); + CHECK_RESULT (&res, &exp, 8, _mask_cvtepu64_ph); + + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, 0xc1, 1); + res.xmmh[0] = INTRINSIC (_maskz_cvtepu64_ph) (0xc1, SI(src3)); + CHECK_RESULT (&res, &exp, 8, _maskz_cvtepu64_ph); + +#if AVX512F_LEN == 512 + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, NET_MASK, 0); + res.xmmh[0] = INTRINSIC (_cvt_roundepu64_ph) (SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, 8, _cvt_roundepu64_ph); + + init_dest(&res, &exp); + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, 0xcc, 0); + res.xmmh[0] = INTRINSIC (_mask_cvt_roundepu64_ph) (res.xmmh[0], 0xcc, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, 8, _mask_cvt_roundepu64_ph); + + EMULATE(cvtq2_ph)(&exp, src3, N_ELEMS, 0xc1, 1); + res.xmmh[0] = INTRINSIC (_maskz_cvt_roundepu64_ph) (0xc1, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, 8, _maskz_cvt_roundepu64_ph); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuw2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuw2ph-1a.c new file mode 100644 index 00000000000..43c96a0d2fc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuw2ph-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m512h res; +volatile __m512i x1; +volatile __mmask32 m32; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtepu16_ph (x1); + res = _mm512_mask_cvtepu16_ph (res, m32, x1); + res = _mm512_maskz_cvtepu16_ph (m32, x1); + res = _mm512_cvt_roundepu16_ph (x1, 4); + res = _mm512_mask_cvt_roundepu16_ph (res, m32, x1, 8); + res = _mm512_maskz_cvt_roundepu16_ph (m32, x1, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuw2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuw2ph-1b.c new file mode 100644 index 00000000000..6d6b6da342f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtuw2ph-1b.c @@ -0,0 +1,93 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtw2_ph) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + m2 = (k >> 16) & 0xffff; + + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.f32[i] = v7.f32[i]; + } + } + else { + v5.f32[i] = op1.u16[i]; + + } + + if (((1 << i) & m2) == 0) { + if (zero_mask) { + v6.f32[i] = 0; + } + else { + v6.f32[i] = v8.f32[i]; + } + } + else { + v6.f32[i] = op1.u16[i+16]; + } + } + + *dest = pack_twops_2ph(v5, v6); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtw2_ph)(&exp, src3, NET_MASK, 0); + HF(res) = INTRINSIC (_cvtepu16_ph) (SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtepu16_ph); + + init_dest(&res, &exp); + EMULATE(cvtw2_ph)(&exp, src3, MASK_VALUE, 0); + HF(res) = INTRINSIC (_mask_cvtepu16_ph) (HF(res), MASK_VALUE, SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtepu16_ph); + + EMULATE(cvtw2_ph)(&exp, src3, ZMASK_VALUE, 1); + HF(res) = INTRINSIC (_maskz_cvtepu16_ph) (ZMASK_VALUE, SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtepu16_ph); + +#if AVX512F_LEN == 512 + EMULATE(cvtw2_ph)(&exp, src3, NET_MASK, 0); + HF(res) = INTRINSIC (_cvt_roundepu16_ph) (SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvt_roundepu16_ph); + + init_dest(&res, &exp); + EMULATE(cvtw2_ph)(&exp, src3, MASK_VALUE, 0); + HF(res) = INTRINSIC (_mask_cvt_roundepu16_ph) (HF(res), MASK_VALUE, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvt_roundepu16_ph); + + EMULATE(cvtw2_ph)(&exp, src3, ZMASK_VALUE, 1); + HF(res) = INTRINSIC (_maskz_cvt_roundepu16_ph) (ZMASK_VALUE, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvt_roundepu16_ph); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtw2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtw2ph-1a.c new file mode 100644 index 00000000000..c6eaee1772b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtw2ph-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m512h res; +volatile __m512i x1; +volatile __mmask32 m32; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtepi16_ph (x1); + res = _mm512_mask_cvtepi16_ph (res, m32, x1); + res = _mm512_maskz_cvtepi16_ph (m32, x1); + res = _mm512_cvt_roundepi16_ph (x1, 4); + res = _mm512_mask_cvt_roundepi16_ph (res, m32, x1, 8); + res = _mm512_maskz_cvt_roundepi16_ph (m32, x1, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtw2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtw2ph-1b.c new file mode 100644 index 00000000000..e02b6fcdbf7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtw2ph-1b.c @@ -0,0 +1,92 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtw2_ph) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + m2 = (k >> 16) & 0xffff; + + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.f32[i] = v7.f32[i]; + } + } + else { + v5.f32[i] = op1.u16[i]; + + } + + if (((1 << i) & m2) == 0) { + if (zero_mask) { + v6.f32[i] = 0; + } + else { + v6.f32[i] = v8.f32[i]; + } + } + else { + v6.f32[i] = op1.u16[i+16]; + } + } + + *dest = pack_twops_2ph(v5, v6); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtw2_ph)(&exp, src3, NET_MASK, 0); + HF(res) = INTRINSIC (_cvtepi16_ph) (SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtepi16_ph); + + init_dest(&res, &exp); + EMULATE(cvtw2_ph)(&exp, src3, MASK_VALUE, 0); + HF(res) = INTRINSIC (_mask_cvtepi16_ph) (HF(res), MASK_VALUE, SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtepi16_ph); + + EMULATE(cvtw2_ph)(&exp, src3, ZMASK_VALUE, 1); + HF(res) = INTRINSIC (_maskz_cvtepi16_ph) (ZMASK_VALUE, SI(src3)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtepi16_ph); + +#if AVX512F_LEN == 512 + EMULATE(cvtw2_ph)(&exp, src3, NET_MASK, 0); + HF(res) = INTRINSIC (_cvt_roundepi16_ph) (SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvt_roundepi16_ph); + + init_dest(&res, &exp); + EMULATE(cvtw2_ph)(&exp, src3, MASK_VALUE, 0); + HF(res) = INTRINSIC (_mask_cvt_roundepi16_ph) (HF(res), MASK_VALUE, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvt_roundepi16_ph); + + EMULATE(cvtw2_ph)(&exp, src3, ZMASK_VALUE, 1); + HF(res) = INTRINSIC (_maskz_cvt_roundepi16_ph) (ZMASK_VALUE, SI(src3), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvt_roundepi16_ph); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtdq2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtdq2ph-1a.c new file mode 100644 index 00000000000..ab0541dce1a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtdq2ph-1a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtdq2phy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2phy\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2phy\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m128h res3; +volatile __m256i x2; +volatile __m128i x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res3 = _mm256_cvtepi32_ph (x2); + res3 = _mm256_mask_cvtepi32_ph (res3, m8, x2); + res3 = _mm256_maskz_cvtepi32_ph (m8, x2); + + res3 = _mm_cvtepi32_ph (x3); + res3 = _mm_mask_cvtepi32_ph (res3, m8, x3); + res3 = _mm_maskz_cvtepi32_ph (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtdq2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtdq2ph-1b.c new file mode 100644 index 00000000000..033587a6704 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtdq2ph-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtdq2ph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtdq2ph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtqq2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtqq2ph-1a.c new file mode 100644 index 00000000000..8e42a4b29f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtqq2ph-1a.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtqq2phy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2phy\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2phy\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m128h res3; +volatile __m256i x2; +volatile __m128i x3; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res3 = _mm256_cvtepi64_ph (x2); + res3 = _mm256_mask_cvtepi64_ph (res3, m16, x2); + res3 = _mm256_maskz_cvtepi64_ph (m16, x2); + + res3 = _mm_cvtepi64_ph (x3); + res3 = _mm_mask_cvtepi64_ph (res3, m8, x3); + res3 = _mm_maskz_cvtepi64_ph (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtqq2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtqq2ph-1b.c new file mode 100644 index 00000000000..6a4a329f368 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtqq2ph-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtqq2ph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtqq2ph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtudq2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtudq2ph-1a.c new file mode 100644 index 00000000000..4fa2ab92245 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtudq2ph-1a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtudq2phy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtudq2phy\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtudq2phy\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtudq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtudq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtudq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m128h res3; +volatile __m256i x2; +volatile __m128i x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res3 = _mm256_cvtepu32_ph (x2); + res3 = _mm256_mask_cvtepu32_ph (res3, m8, x2); + res3 = _mm256_maskz_cvtepu32_ph (m8, x2); + + res3 = _mm_cvtepu32_ph (x3); + res3 = _mm_mask_cvtepu32_ph (res3, m8, x3); + res3 = _mm_maskz_cvtepu32_ph (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtudq2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtudq2ph-1b.c new file mode 100644 index 00000000000..4ea2c268760 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtudq2ph-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtudq2ph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtudq2ph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1a.c new file mode 100644 index 00000000000..a3ee951d4c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1a.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtuqq2phy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuqq2phy\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuqq2phy\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuqq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuqq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuqq2phx\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m128h res3; +volatile __m256i x2; +volatile __m128i x3; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res3 = _mm256_cvtepu64_ph (x2); + res3 = _mm256_mask_cvtepu64_ph (res3, m16, x2); + res3 = _mm256_maskz_cvtepu64_ph (m16, x2); + + res3 = _mm_cvtepu64_ph (x3); + res3 = _mm_mask_cvtepu64_ph (res3, m8, x3); + res3 = _mm_maskz_cvtepu64_ph (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1b.c new file mode 100644 index 00000000000..c747e8de0dd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtuqq2ph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtuqq2ph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuw2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuw2ph-1a.c new file mode 100644 index 00000000000..59393dc01a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuw2ph-1a.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m256h res2; +volatile __m128h res3; +volatile __m256i x2; +volatile __m128i x3; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res2 = _mm256_cvtepu16_ph (x2); + res2 = _mm256_mask_cvtepu16_ph (res2, m16, x2); + res2 = _mm256_maskz_cvtepu16_ph (m16, x2); + + res3 = _mm_cvtepu16_ph (x3); + res3 = _mm_mask_cvtepu16_ph (res3, m8, x3); + res3 = _mm_maskz_cvtepu16_ph (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuw2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuw2ph-1b.c new file mode 100644 index 00000000000..89d94df57b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtuw2ph-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtuw2ph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtuw2ph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtw2ph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtw2ph-1a.c new file mode 100644 index 00000000000..ff5530f60a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtw2ph-1a.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m256h res2; +volatile __m128h res3; +volatile __m256i x2; +volatile __m128i x3; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res2 = _mm256_cvtepi16_ph (x2); + res2 = _mm256_mask_cvtepi16_ph (res2, m16, x2); + res2 = _mm256_maskz_cvtepi16_ph (m16, x2); + + res3 = _mm_cvtepi16_ph (x3); + res3 = _mm_mask_cvtepi16_ph (res3, m8, x3); + res3 = _mm_maskz_cvtepi16_ph (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtw2ph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtw2ph-1b.c new file mode 100644 index 00000000000..243e45bda62 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtw2ph-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtw2ph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtw2ph-1b.c" + -- 2.18.1