From: liuhongt <hongtao.liu@intel.com>
To: gcc-patches@gcc.gnu.org
Cc: crazylht@gmail.com, hjl.tools@gmail.com, ubizjak@gmail.com,
jakub@redhat.com
Subject: [PATCH 38/62] AVX512FP16: Add testcase for vcvtsh2sd/vcvtsh2ss/vcvtsd2sh/vcvtss2sh.
Date: Thu, 1 Jul 2021 14:16:24 +0800 [thread overview]
Message-ID: <20210701061648.9447-39-hongtao.liu@intel.com> (raw)
In-Reply-To: <20210701061648.9447-1-hongtao.liu@intel.com>
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx512fp16-vcvtsd2sh-1a.c: New test.
* gcc.target/i386/avx512fp16-vcvtsd2sh-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtsh2sd-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtsh2sd-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtsh2ss-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtsh2ss-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtss2sh-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vcvtss2sh-1b.c: Ditto.
---
.../gcc.target/i386/avx512fp16-vcvtsd2sh-1a.c | 25 ++++++++
.../gcc.target/i386/avx512fp16-vcvtsd2sh-1b.c | 60 +++++++++++++++++++
.../gcc.target/i386/avx512fp16-vcvtsh2sd-1a.c | 25 ++++++++
.../gcc.target/i386/avx512fp16-vcvtsh2sd-1b.c | 57 ++++++++++++++++++
.../gcc.target/i386/avx512fp16-vcvtsh2ss-1a.c | 25 ++++++++
.../gcc.target/i386/avx512fp16-vcvtsh2ss-1b.c | 59 ++++++++++++++++++
.../gcc.target/i386/avx512fp16-vcvtss2sh-1a.c | 25 ++++++++
.../gcc.target/i386/avx512fp16-vcvtss2sh-1b.c | 60 +++++++++++++++++++
8 files changed, 336 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsd2sh-1a.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsd2sh-1b.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2sd-1a.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2sd-1b.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2ss-1a.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2ss-1b.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtss2sh-1a.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtss2sh-1b.c
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsd2sh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsd2sh-1a.c
new file mode 100644
index 00000000000..b663ca507fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsd2sh-1a.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vcvtsd2sh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtsd2sh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtsd2sh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtsd2sh\[ \\t\]+\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtsd2sh\[ \\t\]+\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtsd2sh\[ \\t\]+\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128h res, x1;
+volatile __m128d x2;
+volatile __mmask8 m8;
+
+void extern
+avx512f_test (void)
+{
+ res = _mm_cvtsd_sh (x1, x2);
+ res = _mm_mask_cvtsd_sh (res, m8, x1, x2);
+ res = _mm_maskz_cvtsd_sh (m8, x1, x2);
+ res = _mm_cvt_roundsd_sh (x1, x2, 8);
+ res = _mm_mask_cvt_roundsd_sh (res, m8, x1, x2, 8);
+ res = _mm_maskz_cvt_roundsd_sh (m8, x1, x2, 11);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsd2sh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsd2sh-1b.c
new file mode 100644
index 00000000000..552362058c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsd2sh-1b.c
@@ -0,0 +1,60 @@
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */
+
+
+#define AVX512FP16
+#include "avx512fp16-helper.h"
+
+#define N_ELEMS 8
+
+void NOINLINE
+emulate_vcvtsd2sh(V512 * dest, V512 op1, V512 op2,
+ __mmask8 k, int zero_mask)
+{
+ V512 v1, v2, v5, v6, v7, v8;
+ int i;
+
+ unpack_ph_2twops(op1, &v1, &v2);
+ unpack_ph_2twops(*dest, &v7, &v8);
+
+ if ((k&1) || !k)
+ v5.f32[0] = (float)op2.f64[0];
+ else if (zero_mask)
+ v5.f32[0] = 0;
+ else
+ v5.f32[0] = v7.f32[0];
+
+ for (i = 1; i < 8; i++)
+ v5.f32[i] = v1.f32[i];
+
+ *dest = pack_twops_2ph(v5, v6);
+}
+
+void
+test_512 (void)
+{
+ V512 res;
+ V512 exp;
+
+ init_src();
+ emulate_vcvtsd2sh(&exp, src1, src2, 0x1, 0);
+ res.xmmh[0] = _mm_cvt_roundsd_sh(src1.xmmh[0], src2.xmmd[0],
+ _ROUND_NINT);
+ check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundsd_sh");
+
+ init_dest(&res, &exp);
+ emulate_vcvtsd2sh(&exp, src1, src2, 0x1, 0);
+ res.xmmh[0] = _mm_mask_cvt_roundsd_sh(res.xmmh[0], 0x1, src1.xmmh[0],
+ src2.xmmd[0], _ROUND_NINT);
+ check_results(&res, &exp, N_ELEMS, "mm_mask_cvt_roundsd_sh");
+
+ emulate_vcvtsd2sh(&exp, src1, src2, 0x2, 1);
+ res.xmmh[0] = _mm_maskz_cvt_roundsd_sh(0x2, src1.xmmh[0],
+ src2.xmmd[0], _ROUND_NINT);
+ check_results(&res, &exp, N_ELEMS, "mm_maskz_cvt_roundsd_sh");
+
+ if (n_errs != 0) {
+ abort ();
+ }
+}
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2sd-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2sd-1a.c
new file mode 100644
index 00000000000..59719ed18e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2sd-1a.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vcvtsh2sd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtsh2sd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtsh2sd\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtsh2sd\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtsh2sd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */
+
+#include <immintrin.h>
+
+volatile __m128d res;
+volatile __m128d x1;
+volatile __m128h x2;
+volatile __mmask8 m8;
+
+void extern
+avx512f_test (void)
+{
+ res = _mm_cvtsh_sd (x1, x2);
+ res = _mm_mask_cvtsh_sd (res, m8, x1, x2);
+ res = _mm_maskz_cvtsh_sd (m8, x1, x2);
+ res = _mm_cvt_roundsh_sd (x1, x2, 8);
+ res = _mm_mask_cvt_roundsh_sd (res, m8, x1, x2, 8);
+ res = _mm_maskz_cvt_roundsh_sd (m8, x1, x2, 4);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2sd-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2sd-1b.c
new file mode 100644
index 00000000000..e6bdc9580bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2sd-1b.c
@@ -0,0 +1,57 @@
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */
+
+
+#define AVX512FP16
+#include "avx512fp16-helper.h"
+
+#define N_ELEMS 8
+
+void NOINLINE
+emulate_vcvtsh2sd(V512 * dest, V512 op1, V512 op2,
+ __mmask8 k, int zero_mask)
+{
+ V512 v1, v2, v3, v4, v5, v6, v7, v8;
+
+ unpack_ph_2twops(op2, &v3, &v4);
+
+ if ((k&1) || !k)
+ v5.f64[0] = v3.f32[0];
+ else if (zero_mask)
+ v5.f64[0] = 0;
+ else
+ v5.f64[0] = dest->f64[0];
+
+ v5.f64[1] = op1.f64[1];
+
+ *dest = v5;
+}
+
+void
+test_512 (void)
+{
+ V512 res;
+ V512 exp;
+
+ init_src();
+ emulate_vcvtsh2sd(&exp, src1, src2, 0x1, 0);
+ res.xmmd[0] = _mm_cvt_roundsh_sd(src1.xmmd[0], src2.xmmh[0],
+ _ROUND_NINT);
+ check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundsh_sd");
+
+ init_dest(&res, &exp);
+ emulate_vcvtsh2sd(&exp, src1, src2, 0x1, 0);
+ res.xmmd[0] = _mm_mask_cvt_roundsh_sd(res.xmmd[0], 0x1, src1.xmmd[0],
+ src2.xmmh[0], _ROUND_NINT);
+ check_results(&res, &exp, N_ELEMS, "mm_mask_cvt_roundsh_sd");
+
+ emulate_vcvtsh2sd(&exp, src1, src2, 0x2, 1);
+ res.xmmd[0] = _mm_maskz_cvt_roundsh_sd(0x2, src1.xmmd[0],
+ src2.xmmh[0], _ROUND_NINT);
+ check_results(&res, &exp, N_ELEMS, "mm_maskz_cvt_roundsh_sd");
+
+ if (n_errs != 0) {
+ abort ();
+ }
+}
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2ss-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2ss-1a.c
new file mode 100644
index 00000000000..e6c369c067f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2ss-1a.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vcvtsh2ss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtsh2ss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtsh2ss\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtsh2ss\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtsh2ss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */
+
+#include <immintrin.h>
+
+volatile __m128 res;
+volatile __m128 x1;
+volatile __m128h x2;
+volatile __mmask8 m8;
+
+void extern
+avx512f_test (void)
+{
+ res = _mm_cvtsh_ss (x1, x2);
+ res = _mm_mask_cvtsh_ss (res, m8, x1, x2);
+ res = _mm_maskz_cvtsh_ss (m8, x1, x2);
+ res = _mm_cvt_roundsh_ss (x1, x2, 8);
+ res = _mm_mask_cvt_roundsh_ss (res, m8, x1, x2, 8);
+ res = _mm_maskz_cvt_roundsh_ss (m8, x1, x2, 4);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2ss-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2ss-1b.c
new file mode 100644
index 00000000000..319598341cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2ss-1b.c
@@ -0,0 +1,59 @@
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */
+
+
+#define AVX512FP16
+#include "avx512fp16-helper.h"
+
+#define N_ELEMS 8
+
+ void NOINLINE
+emulate_vcvtsh2ss(V512 * dest, V512 op1, V512 op2,
+ __mmask8 k, int zero_mask)
+{
+ V512 v1, v2, v3, v4, v5, v6, v7, v8;
+ int i;
+
+ unpack_ph_2twops(op2, &v3, &v4);
+ if ((k&1) || !k)
+ v5.f32[0] = v3.f32[0];
+ else if (zero_mask)
+ v5.f32[0] = 0;
+ else
+ v5.f32[0] = dest->f32[0];
+
+ for (i = 1; i < 4; i++)
+ v5.f32[i] = op1.f32[i];
+
+ *dest = v5;
+}
+
+void
+test_512 (void)
+{
+ V512 res;
+ V512 exp;
+
+ init_src();
+ emulate_vcvtsh2ss(&exp, src1, src2, 0x1, 0);
+ res.xmm[0] = _mm_cvt_roundsh_ss(src1.xmm[0], src2.xmmh[0],
+ _ROUND_NINT);
+ check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundsh_ss");
+
+ init_dest(&res, &exp);
+ emulate_vcvtsh2ss(&exp, src1, src2, 0x1, 0);
+ res.xmm[0] = _mm_mask_cvt_roundsh_ss(res.xmm[0], 0x1, src1.xmm[0],
+ src2.xmmh[0], _ROUND_NINT);
+ check_results(&res, &exp, N_ELEMS, "mm_mask_cvt_roundsh_ss");
+
+ emulate_vcvtsh2ss(&exp, src1, src2, 0x2, 1);
+ res.xmm[0] = _mm_maskz_cvt_roundsh_ss(0x2, src1.xmm[0],
+ src2.xmmh[0], _ROUND_NINT);
+ check_results(&res, &exp, N_ELEMS, "mm_maskz_cvt_roundsh_ss");
+
+ if (n_errs != 0) {
+ abort ();
+ }
+}
+
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtss2sh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtss2sh-1a.c
new file mode 100644
index 00000000000..63ad0906555
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtss2sh-1a.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vcvtss2sh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtss2sh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtss2sh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtss2sh\[ \\t\]+\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtss2sh\[ \\t\]+\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtss2sh\[ \\t\]+\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128h res, x1;
+volatile __m128 x2;
+volatile __mmask8 m8;
+
+void extern
+avx512f_test (void)
+{
+ res = _mm_cvtss_sh (x1, x2);
+ res = _mm_mask_cvtss_sh (res, m8, x1, x2);
+ res = _mm_maskz_cvtss_sh (m8, x1, x2);
+ res = _mm_cvt_roundss_sh (x1, x2, 8);
+ res = _mm_mask_cvt_roundss_sh (res, m8, x1, x2, 8);
+ res = _mm_maskz_cvt_roundss_sh (m8, x1, x2, 11);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtss2sh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtss2sh-1b.c
new file mode 100644
index 00000000000..94981bbb79f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtss2sh-1b.c
@@ -0,0 +1,60 @@
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */
+
+
+#define AVX512FP16
+#include "avx512fp16-helper.h"
+
+#define N_ELEMS 8
+
+void NOINLINE
+emulate_vcvtss2sh(V512 * dest, V512 op1, V512 op2,
+ __mmask8 k, int zero_mask)
+{
+ V512 v1, v2, v5, v6, v7, v8;
+ int i;
+
+ unpack_ph_2twops(op1, &v1, &v2);
+ unpack_ph_2twops(*dest, &v7, &v8);
+
+ if ((k&1) || !k)
+ v5.f32[0] = op2.f32[0];
+ else if (zero_mask)
+ v5.f32[0] = 0;
+ else
+ v5.f32[0] = v7.f32[0];
+
+ for (i = 1; i < 8; i++)
+ v5.f32[i] = v1.f32[i];
+
+ *dest = pack_twops_2ph(v5, v6);
+}
+
+void
+test_512 (void)
+{
+ V512 res;
+ V512 exp;
+
+ init_src();
+ emulate_vcvtss2sh(&exp, src1, src2, 0x1, 0);
+ res.xmmh[0] = _mm_cvt_roundss_sh(src1.xmmh[0], src2.xmm[0],
+ _ROUND_NINT);
+ check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundss_sh");
+
+ init_dest(&res, &exp);
+ emulate_vcvtss2sh(&exp, src1, src2, 0x1, 0);
+ res.xmmh[0] = _mm_mask_cvt_roundss_sh(res.xmmh[0], 0x1, src1.xmmh[0],
+ src2.xmm[0], _ROUND_NINT);
+ check_results(&res, &exp, N_ELEMS, "mm_mask_cvt_roundss_sh");
+
+ emulate_vcvtss2sh(&exp, src1, src2, 0x2, 1);
+ res.xmmh[0] = _mm_maskz_cvt_roundss_sh(0x2, src1.xmmh[0],
+ src2.xmm[0], _ROUND_NINT);
+ check_results(&res, &exp, N_ELEMS, "mm_maskz_cvt_roundss_sh");
+
+ if (n_errs != 0) {
+ abort ();
+ }
+}
+
--
2.18.1
next prev parent reply other threads:[~2021-07-01 6:17 UTC|newest]
Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-01 6:15 [PATCH 00/62] Support all AVX512FP16 intrinsics liuhongt
2021-07-01 6:15 ` [PATCH 01/62] AVX512FP16: Support vector init/broadcast for FP16 liuhongt
2021-07-01 6:15 ` [PATCH 02/62] AVX512FP16: Add testcase for vector init and broadcast intrinsics liuhongt
2021-07-01 6:15 ` [PATCH 03/62] AVX512FP16: Fix HF vector passing in variable arguments liuhongt
2021-07-01 6:15 ` [PATCH 04/62] AVX512FP16: Add ABI tests for xmm liuhongt
2021-07-01 6:15 ` [PATCH 05/62] AVX512FP16: Add ABI test for ymm liuhongt
2021-07-01 6:15 ` [PATCH 06/62] AVX512FP16: Add abi test for zmm liuhongt
2021-07-01 6:15 ` [PATCH 07/62] AVX512FP16: Add vaddph/vsubph/vdivph/vmulph liuhongt
2021-09-09 7:48 ` Hongtao Liu
2021-07-01 6:15 ` [PATCH 08/62] AVX512FP16: Add testcase for vaddph/vsubph/vmulph/vdivph liuhongt
2021-07-01 6:15 ` [PATCH 09/62] AVX512FP16: Enable _Float16 autovectorization liuhongt
2021-09-10 7:03 ` Hongtao Liu
2021-07-01 6:15 ` [PATCH 10/62] AVX512FP16: Add vaddsh/vsubsh/vmulsh/vdivsh liuhongt
2021-07-01 6:15 ` [PATCH 11/62] AVX512FP16: Add testcase for vaddsh/vsubsh/vmulsh/vdivsh liuhongt
2021-07-01 6:15 ` [PATCH 12/62] AVX512FP16: Add vmaxph/vminph/vmaxsh/vminsh liuhongt
2021-07-01 6:15 ` [PATCH 13/62] AVX512FP16: Add testcase for vmaxph/vmaxsh/vminph/vminsh liuhongt
2021-07-01 6:16 ` [PATCH 14/62] AVX512FP16: Add vcmpph/vcmpsh/vcomish/vucomish liuhongt
2021-07-01 6:16 ` [PATCH 15/62] AVX512FP16: Add testcase for vcmpph/vcmpsh/vcomish/vucomish liuhongt
2021-07-01 6:16 ` [PATCH 16/62] AVX512FP16: Add vsqrtph/vrsqrtph/vsqrtsh/vrsqrtsh liuhongt
2021-09-14 3:50 ` Hongtao Liu
2021-07-01 6:16 ` [PATCH 17/62] AVX512FP16: Add testcase for vsqrtph/vsqrtsh/vrsqrtph/vrsqrtsh liuhongt
2021-07-01 6:16 ` [PATCH 18/62] AVX512FP16: Add vrcpph/vrcpsh/vscalefph/vscalefsh liuhongt
2021-07-01 6:16 ` [PATCH 19/62] AVX512FP16: Add testcase for vrcpph/vrcpsh/vscalefph/vscalefsh liuhongt
2021-07-01 6:16 ` [PATCH 20/62] AVX512FP16: Add vreduceph/vreducesh/vrndscaleph/vrndscalesh liuhongt
2021-07-01 6:16 ` [PATCH 21/62] AVX512FP16: Add testcase for vreduceph/vreducesh/vrndscaleph/vrndscalesh liuhongt
2021-07-01 6:16 ` [PATCH 22/62] AVX512FP16: Add fpclass/getexp/getmant instructions liuhongt
2021-07-01 6:16 ` [PATCH 23/62] AVX512FP16: Add testcase for fpclass/getmant/getexp instructions liuhongt
2021-07-01 6:16 ` [PATCH 24/62] AVX512FP16: Add vmovw/vmovsh liuhongt
2021-09-16 5:08 ` Hongtao Liu
2021-07-01 6:16 ` [PATCH 25/62] AVX512FP16: Add testcase for vmovsh/vmovw liuhongt
2021-07-01 6:16 ` [PATCH 26/62] AVX512FP16: Add vcvtph2dq/vcvtph2qq/vcvtph2w/vcvtph2uw/vcvtph2uqq/vcvtph2udq liuhongt
2021-07-01 6:16 ` [PATCH 27/62] AVX512FP16: Add testcase for vcvtph2w/vcvtph2uw/vcvtph2dq/vcvtph2udq/vcvtph2qq/vcvtph2uqq liuhongt
2021-07-01 6:16 ` [PATCH 28/62] AVX512FP16: Add vcvtuw2ph/vcvtw2ph/vcvtdq2ph/vcvtudq2ph/vcvtqq2ph/vcvtuqq2ph liuhongt
2021-07-01 6:16 ` [PATCH 29/62] AVX512FP16: Add testcase for vcvtw2ph/vcvtuw2ph/vcvtdq2ph/vcvtudq2ph/vcvtqq2ph/vcvtuqq2ph liuhongt
2021-07-01 6:16 ` [PATCH 30/62] AVX512FP16: Add vcvtsh2si/vcvtsh2usi/vcvtsi2sh/vcvtusi2sh liuhongt
2021-09-17 8:07 ` Hongtao Liu
2021-07-01 6:16 ` [PATCH 31/62] AVX512FP16: Add testcase for vcvtsh2si/vcvtsh2usi/vcvtsi2sh/vcvtusi2sh liuhongt
2021-07-01 6:16 ` [PATCH 32/62] AVX512FP16: Add vcvttph2w/vcvttph2uw/vcvttph2dq/vcvttph2qq/vcvttph2udq/vcvttph2uqq liuhongt
2021-07-01 6:16 ` [PATCH 33/62] AVX512FP16: Add testcase for vcvttph2w/vcvttph2uw/vcvttph2dq/vcvttph2udq/vcvttph2qq/vcvttph2uqq liuhongt
2021-07-01 6:16 ` [PATCH 34/62] AVX512FP16: Add vcvttsh2si/vcvttsh2usi liuhongt
2021-07-01 6:16 ` [PATCH 35/62] AVX512FP16: Add vcvtph2pd/vcvtph2psx/vcvtpd2ph/vcvtps2phx liuhongt
2021-07-01 6:16 ` [PATCH 36/62] AVX512FP16: Add testcase for vcvtph2pd/vcvtph2psx/vcvtpd2ph/vcvtps2phx liuhongt
2021-07-01 6:16 ` [PATCH 37/62] AVX512FP16: Add vcvtsh2ss/vcvtsh2sd/vcvtss2sh/vcvtsd2sh liuhongt
2021-07-01 6:16 ` liuhongt [this message]
2021-07-01 6:16 ` [PATCH 39/62] AVX512FP16: Add intrinsics for casting between vector float16 and vector float32/float64/integer liuhongt
2021-07-01 6:16 ` [PATCH 40/62] AVX512FP16: Add vfmaddsub[132, 213, 231]ph/vfmsubadd[132, 213, 231]ph liuhongt
2021-09-18 7:04 ` Hongtao Liu
2021-07-01 6:16 ` [PATCH 41/62] AVX512FP16: Add testcase for " liuhongt
2021-07-01 6:16 ` [PATCH 42/62] AVX512FP16: Add FP16 fma instructions liuhongt
2021-07-01 6:16 ` [PATCH 43/62] AVX512FP16: Add testcase for " liuhongt
2021-07-01 6:16 ` [PATCH 44/62] AVX512FP16: Add scalar/vector bitwise operations, including liuhongt
2021-07-23 5:13 ` Hongtao Liu
2021-07-26 2:25 ` Hongtao Liu
2021-07-01 6:16 ` [PATCH 45/62] AVX512FP16: Add testcase for fp16 bitwise operations liuhongt
2021-07-01 6:16 ` [PATCH 46/62] AVX512FP16: Enable FP16 mask load/store liuhongt
2021-07-01 6:16 ` [PATCH 47/62] AVX512FP16: Add scalar fma instructions liuhongt
2021-07-01 6:16 ` [PATCH 48/62] AVX512FP16: Add testcase for scalar FMA instructions liuhongt
2021-07-01 6:16 ` [PATCH 49/62] AVX512FP16: Add vfcmaddcph/vfmaddcph/vfcmulcph/vfmulcph liuhongt
2021-09-22 4:38 ` Hongtao Liu
2021-07-01 6:16 ` [PATCH 50/62] AVX512FP16: Add testcases for vfcmaddcph/vfmaddcph/vfcmulcph/vfmulcph liuhongt
2021-07-01 6:16 ` [PATCH 51/62] AVX512FP16: Add vfcmaddcsh/vfmaddcsh/vfcmulcsh/vfmulcsh liuhongt
2021-07-01 6:16 ` [PATCH 52/62] AVX512FP16: Add testcases for vfcmaddcsh/vfmaddcsh/vfcmulcsh/vfmulcsh liuhongt
2021-07-01 6:16 ` [PATCH 53/62] AVX512FP16: Add expander for sqrthf2 liuhongt
2021-07-23 5:12 ` Hongtao Liu
2021-07-01 6:16 ` [PATCH 54/62] AVX512FP16: Add expander for ceil/floor/trunc/roundeven liuhongt
2021-07-01 6:16 ` [PATCH 55/62] AVX512FP16: Add expander for cstorehf4 liuhongt
2021-07-01 6:16 ` [PATCH 56/62] AVX512FP16: Optimize (_Float16) sqrtf ((float) f16) to sqrtf16 (f16) liuhongt
2021-07-01 9:50 ` Richard Biener
2021-07-01 10:23 ` Hongtao Liu
2021-07-01 12:43 ` Richard Biener
2021-07-01 21:48 ` Joseph Myers
2021-07-02 7:38 ` Richard Biener
2021-07-01 21:17 ` Joseph Myers
2021-07-01 6:16 ` [PATCH 57/62] AVX512FP16: Add expander for fmahf4 liuhongt
2021-07-01 6:16 ` [PATCH 58/62] AVX512FP16: Optimize for code like (_Float16) __builtin_ceif ((float) f16) liuhongt
2021-07-01 9:52 ` Richard Biener
2021-07-01 21:26 ` Joseph Myers
2021-07-02 7:36 ` Richard Biener
2021-07-02 11:46 ` Bernhard Reutner-Fischer
2021-07-04 5:17 ` Hongtao Liu
2021-07-01 6:16 ` [PATCH 59/62] AVX512FP16: Support load/store/abs intrinsics liuhongt
2021-09-22 10:30 ` Hongtao Liu
2021-07-01 6:16 ` [PATCH 60/62] AVX512FP16: Add reduce operators(add/mul/min/max) liuhongt
2021-07-01 6:16 ` [PATCH 61/62] AVX512FP16: Add complex conjugation intrinsic instructions liuhongt
2021-07-01 6:16 ` [PATCH 62/62] AVX512FP16: Add permutation and mask blend intrinsics liuhongt
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