From: "H.J. Lu" <hjl.tools@gmail.com>
To: gcc-patches@gcc.gnu.org
Cc: Richard Biener <richard.guenther@gmail.com>,
Richard Sandiford <richard.sandiford@arm.com>,
Uros Bizjak <ubizjak@gmail.com>,
Bernd Edlinger <bernd.edlinger@hotmail.de>
Subject: [PATCH v5 05/11] x86: Add AVX2 tests for PR middle-end/90773
Date: Thu, 1 Jul 2021 08:22:38 -0700 [thread overview]
Message-ID: <20210701152244.331984-6-hjl.tools@gmail.com> (raw)
In-Reply-To: <20210701152244.331984-1-hjl.tools@gmail.com>
PR middle-end/90773
* gcc.target/i386/pr90773-20.c: New test.
* gcc.target/i386/pr90773-21.c: Likewise.
* gcc.target/i386/pr90773-22.c: Likewise.
* gcc.target/i386/pr90773-23.c: Likewise.
* gcc.target/i386/pr90773-26.c: Likewise.
---
gcc/testsuite/gcc.target/i386/pr90773-20.c | 13 +++++++++++++
gcc/testsuite/gcc.target/i386/pr90773-21.c | 13 +++++++++++++
gcc/testsuite/gcc.target/i386/pr90773-22.c | 13 +++++++++++++
gcc/testsuite/gcc.target/i386/pr90773-23.c | 13 +++++++++++++
gcc/testsuite/gcc.target/i386/pr90773-26.c | 21 +++++++++++++++++++++
5 files changed, 73 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/i386/pr90773-20.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr90773-21.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr90773-22.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr90773-23.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr90773-26.c
diff --git a/gcc/testsuite/gcc.target/i386/pr90773-20.c b/gcc/testsuite/gcc.target/i386/pr90773-20.c
new file mode 100644
index 00000000000..e61e405f2b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr90773-20.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=skylake" } */
+
+extern char *dst;
+
+void
+foo (int c)
+{
+ __builtin_memset (dst, c, 33);
+}
+
+/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]%ymm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */
+/* { dg-final { scan-assembler-times "movb\[\\t \]+.+, 32\\(%\[\^,\]+\\)" 1 } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr90773-21.c b/gcc/testsuite/gcc.target/i386/pr90773-21.c
new file mode 100644
index 00000000000..16ad17f3cbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr90773-21.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=skylake" } */
+
+extern char *dst;
+
+void
+foo (int c)
+{
+ __builtin_memset (dst, c, 34);
+}
+
+/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]%ymm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */
+/* { dg-final { scan-assembler-times "movw\[\\t \]%.*, 32\\(%\[\^,\]+\\)" 1 } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr90773-22.c b/gcc/testsuite/gcc.target/i386/pr90773-22.c
new file mode 100644
index 00000000000..45a8ff65a84
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr90773-22.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=skylake" } */
+
+extern char *dst;
+
+void
+foo (void)
+{
+ __builtin_memset (dst, 0, 33);
+}
+
+/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]%ymm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */
+/* { dg-final { scan-assembler-times "movb\[\\t \]+.+, 32\\(%\[\^,\]+\\)" 1 } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr90773-23.c b/gcc/testsuite/gcc.target/i386/pr90773-23.c
new file mode 100644
index 00000000000..9256ce10ff0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr90773-23.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=skylake" } */
+
+extern char *dst;
+
+void
+foo (void)
+{
+ __builtin_memset (dst, 0, 34);
+}
+
+/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]%ymm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */
+/* { dg-final { scan-assembler-times "movw\[\\t \]+.+, 32\\(%\[\^,\]+\\)" 1 } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr90773-26.c b/gcc/testsuite/gcc.target/i386/pr90773-26.c
new file mode 100644
index 00000000000..b2513c3a9c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr90773-26.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=skylake" } */
+
+struct S
+{
+ long long s1 __attribute__ ((aligned (8)));
+ unsigned s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14;
+};
+
+const struct S array[] = {
+ { 0, 60, 640, 2112543726, 39682, 48, 16, 33, 10, 96, 2, 0, 0, 4 }
+};
+
+void
+foo (struct S *x)
+{
+ x[0] = array[0];
+}
+
+/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]%ymm\[0-9\]+, \\(%\[\^,\]+\\)" 1 } } */
+/* { dg-final { scan-assembler-times "vmovdqu\[\\t \]%ymm\[0-9\]+, 32\\(%\[\^,\]+\\)" 1 } } */
--
2.31.1
next prev parent reply other threads:[~2021-07-01 15:22 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-01 15:22 [PATCH v5 00/11] Allow TImode/OImode/XImode in op_by_pieces operations H.J. Lu
2021-07-01 15:22 ` [PATCH v5 01/11] Rewrite memset with TARGET_GEN_MEMSET_SCRATCH_RTX H.J. Lu
2021-07-01 15:22 ` [PATCH v5 02/11] x86: Add TARGET_GEN_MEMSET_SCRATCH_RTX H.J. Lu
2021-07-01 15:22 ` [PATCH v5 03/11] x86: Avoid stack realignment when copying data H.J. Lu
2021-07-01 15:22 ` [PATCH v5 04/11] x86: Update piecewise move and store H.J. Lu
2021-07-01 15:22 ` H.J. Lu [this message]
2021-07-01 15:22 ` [PATCH v5 06/11] x86: Add tests for " H.J. Lu
2021-07-01 15:22 ` [PATCH v5 07/11] x86: Also pass -mno-avx to pr72839.c H.J. Lu
2021-07-01 15:22 ` [PATCH v5 08/11] x86: Also pass -mno-avx to cold-attribute-1.c H.J. Lu
2021-07-01 15:22 ` [PATCH v5 09/11] x86: Also pass -mno-avx to sw-1.c for ia32 H.J. Lu
2021-07-01 15:22 ` [PATCH v5 10/11] x86: Update gcc.target/i386/incoming-11.c H.J. Lu
2021-07-01 15:22 ` [PATCH v5 11/11] x86: Also pass -mno-sse to vect8-ret.c H.J. Lu
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