From: Kito Cheng <kito.cheng@sifive.com>
To: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, jimw@sifive.com,
i@maskray.me
Cc: Kito Cheng <kito.cheng@sifive.com>
Subject: [PATCH] docs: Add 'S' to Machine Constraints for RISC-V
Date: Fri, 2 Jul 2021 10:30:10 +0800 [thread overview]
Message-ID: <20210702023010.53289-1-kito.cheng@sifive.com> (raw)
It was undocument before, but already used in linux kernel, so LLVM
community suggest we should document that, so that make it become
supported/documented/non-internal machine constraints.
gcc/ChangeLog:
PR target/101275
* doc/md.text (Machine Constraints): Document the 'S' constraints
for RISC-V.
---
gcc/doc/md.texi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 00caf3844cc..b776623e8a5 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3536,6 +3536,9 @@ A 5-bit unsigned immediate for CSR access instructions.
@item A
An address that is held in a general-purpose register.
+@item S
+A constant call address.
+
@end table
@item RX---@file{config/rx/constraints.md}
--
2.31.1
next reply other threads:[~2021-07-02 2:30 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-02 2:30 Kito Cheng [this message]
2021-07-02 3:15 ` Fangrui Song
2021-07-07 23:26 ` Fangrui Song
2021-07-08 1:02 ` Palmer Dabbelt
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