From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id C9A4E3855028 for ; Tue, 13 Jul 2021 19:01:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C9A4E3855028 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 16DIXQHm032982; Tue, 13 Jul 2021 15:01:22 -0400 Received: from ppma05wdc.us.ibm.com (1b.90.2fa9.ip4.static.sl-reverse.com [169.47.144.27]) by mx0a-001b2d01.pphosted.com with ESMTP id 39qrudwdx0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 13 Jul 2021 15:01:22 -0400 Received: from pps.filterd (ppma05wdc.us.ibm.com [127.0.0.1]) by ppma05wdc.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 16DIvYLC004740; Tue, 13 Jul 2021 19:01:21 GMT Received: from b01cxnp22036.gho.pok.ibm.com (b01cxnp22036.gho.pok.ibm.com [9.57.198.26]) by ppma05wdc.us.ibm.com with ESMTP id 39q36cd9kp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 13 Jul 2021 19:01:21 +0000 Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp22036.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 16DJ1Kp011600392 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 13 Jul 2021 19:01:21 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D80E312405E; Tue, 13 Jul 2021 19:01:20 +0000 (GMT) Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 81163124054; Tue, 13 Jul 2021 19:01:20 +0000 (GMT) Received: from li-24c3614c-2adc-11b2-a85c-85f334518bdb.ibm.com (unknown [9.65.90.8]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTPS; Tue, 13 Jul 2021 19:01:20 +0000 (GMT) Date: Tue, 13 Jul 2021 14:01:18 -0500 From: "Paul A. Clarke" To: gcc-patches@gcc.gnu.org Cc: Bill Schmidt , Segher Boessenkool Subject: Re: [PATCH 1/4 committed] rs6000: Add support for SSE4.1 "test" intrinsics Message-ID: <20210713190118.GB9282@li-24c3614c-2adc-11b2-a85c-85f334518bdb.ibm.com> References: <20210629180859.1235662-1-pc@us.ibm.com> <20210629180859.1235662-2-pc@us.ibm.com> <8f826ec8-fd50-5deb-49e1-d2891b867d91@linux.ibm.com> <20210712222407.GH1583@gate.crashing.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20210712222407.GH1583@gate.crashing.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-TM-AS-GCONF: 00 X-Proofpoint-GUID: zeVnTqToxcjhuUuJkb9ngvlwZSf-pr-Y X-Proofpoint-ORIG-GUID: zeVnTqToxcjhuUuJkb9ngvlwZSf-pr-Y X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-13_10:2021-07-13, 2021-07-13 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 suspectscore=0 phishscore=0 malwarescore=0 mlxscore=0 spamscore=0 mlxlogscore=999 impostorscore=0 bulkscore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2107130117 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 13 Jul 2021 19:01:24 -0000 On Mon, Jul 12, 2021 at 05:24:07PM -0500, Segher Boessenkool wrote: > On Sun, Jul 11, 2021 at 10:45:45AM -0500, Bill Schmidt wrote: > > On 6/29/21 1:08 PM, Paul A. Clarke via Gcc-patches wrote: > > >--- a/gcc/config/rs6000/smmintrin.h > > >+++ b/gcc/config/rs6000/smmintrin.h > > >@@ -116,4 +116,54 @@ _mm_blendv_epi8 (__m128i __A, __m128i __B, __m128i > > >__mask) > > > return (__m128i) vec_sel ((__v16qu) __A, (__v16qu) __B, __lmask); > > > } > > > > > >+extern __inline int __attribute__((__gnu_inline__, __always_inline__, > > >__artificial__)) > > Line too long, please fix here and below.  (Existing cases can be left.) > > I wouldn't bother in this case. There is no way to write these > attribute lines in a reasonable way, it doesn't overflow 80 char by that > much, and there isn't anything interesting at the end of line. I bothered. ;-) > You could put it on a line by itself, which helps for now because it > won't get too long until you add another attribute ;-) OK > There should be a space before (( though, and "extern" on definitions is > superfluous. But I do not care much about that either -- this isn't a > part of the compiler proper anyway :-) OK > It is okay for trunk with whatever changes you want to do. Thanks! This is what I committed: 2021-07-13 Paul A. Clarke gcc * config/rs6000/smmintrin.h (_mm_testz_si128, _mm_testc_si128, _mm_testnzc_si128, _mm_test_all_ones, _mm_test_all_zeros, _mm_test_mix_ones_zeros): New. --- gcc/config/rs6000/smmintrin.h | 56 +++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/gcc/config/rs6000/smmintrin.h b/gcc/config/rs6000/smmintrin.h index bdf6eb365d88..16fd34d836ff 100644 --- a/gcc/config/rs6000/smmintrin.h +++ b/gcc/config/rs6000/smmintrin.h @@ -116,4 +116,60 @@ _mm_blendv_epi8 (__m128i __A, __m128i __B, __m128i __mask) return (__m128i) vec_sel ((__v16qu) __A, (__v16qu) __B, __lmask); } +__inline int +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_testz_si128 (__m128i __A, __m128i __B) +{ + /* Note: This implementation does NOT set "zero" or "carry" flags. */ + const __v16qu __zero = {0}; + return vec_all_eq (vec_and ((__v16qu) __A, (__v16qu) __B), __zero); +} + +__inline int +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_testc_si128 (__m128i __A, __m128i __B) +{ + /* Note: This implementation does NOT set "zero" or "carry" flags. */ + const __v16qu __zero = {0}; + const __v16qu __notA = vec_nor ((__v16qu) __A, (__v16qu) __A); + return vec_all_eq (vec_and ((__v16qu) __notA, (__v16qu) __B), __zero); +} + +__inline int +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_testnzc_si128 (__m128i __A, __m128i __B) +{ + /* Note: This implementation does NOT set "zero" or "carry" flags. */ + return _mm_testz_si128 (__A, __B) == 0 && _mm_testc_si128 (__A, __B) == 0; +} + +__inline int +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_test_all_zeros (__m128i __A, __m128i __mask) +{ + const __v16qu __zero = {0}; + return vec_all_eq (vec_and ((__v16qu) __A, (__v16qu) __mask), __zero); +} + +__inline int +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_test_all_ones (__m128i __A) +{ + const __v16qu __ones = vec_splats ((unsigned char) 0xff); + return vec_all_eq ((__v16qu) __A, __ones); +} + +__inline int +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_test_mix_ones_zeros (__m128i __A, __m128i __mask) +{ + const __v16qu __zero = {0}; + const __v16qu __Amasked = vec_and ((__v16qu) __A, (__v16qu) __mask); + const int any_ones = vec_any_ne (__Amasked, __zero); + const __v16qu __notA = vec_nor ((__v16qu) __A, (__v16qu) __A); + const __v16qu __notAmasked = vec_and ((__v16qu) __notA, (__v16qu) __mask); + const int any_zeros = vec_any_ne (__notAmasked, __zero); + return any_ones * any_zeros; +} + #endif -- 2.27.0 PC