From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id 0913838515E0 for ; Wed, 4 Aug 2021 12:39:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0913838515E0 X-IronPort-AV: E=McAfee;i="6200,9189,10065"; a="299500017" X-IronPort-AV: E=Sophos;i="5.84,294,1620716400"; d="scan'208";a="299500017" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2021 05:39:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,294,1620716400"; d="scan'208";a="670936425" Received: from scymds01.sc.intel.com ([10.148.94.138]) by fmsmga005.fm.intel.com with ESMTP; 04 Aug 2021 05:39:29 -0700 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.236.50]) by scymds01.sc.intel.com with ESMTP id 174CdS83027267; Wed, 4 Aug 2021 05:39:29 -0700 From: liuhongt To: gcc-patches@gcc.gnu.org Subject: [PATCH 0/3] [i386] Support cond_{smax, smin, umax, umin, xor, ior, and} for vector modes under AVX512 Date: Wed, 4 Aug 2021 20:39:25 +0800 Message-Id: <20210804123928.90586-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=no autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Aug 2021 12:39:34 -0000 Hi: Together with the previous 3 patches, all cond_op expanders of vector modes are supported (if they have a corresponding avx512 mask instruction). Bootstrapped and regtested on x86_64-linux-gnu{-m32,}. liuhongt (3): [i386] Support cond_{smax,smin,umax,umin} for vector integer modes under AVX512. [i386] Support cond_{smax,smin} for vector float/double modes under AVX512. [i386] Support cond_{xor,ior,and} for vector integer mode under AVX512. gcc/config/i386/sse.md | 54 +++++++++++++ .../gcc.target/i386/cond_op_anylogic_d-1.c | 38 +++++++++ .../gcc.target/i386/cond_op_anylogic_d-2.c | 78 +++++++++++++++++++ .../gcc.target/i386/cond_op_anylogic_q-1.c | 10 +++ .../gcc.target/i386/cond_op_anylogic_q-2.c | 5 ++ .../gcc.target/i386/cond_op_maxmin_b-1.c | 8 ++ .../gcc.target/i386/cond_op_maxmin_b-2.c | 6 ++ .../gcc.target/i386/cond_op_maxmin_d-1.c | 41 ++++++++++ .../gcc.target/i386/cond_op_maxmin_d-2.c | 67 ++++++++++++++++ .../gcc.target/i386/cond_op_maxmin_double-1.c | 39 ++++++++++ .../gcc.target/i386/cond_op_maxmin_double-2.c | 67 ++++++++++++++++ .../gcc.target/i386/cond_op_maxmin_float-1.c | 8 ++ .../gcc.target/i386/cond_op_maxmin_float-2.c | 5 ++ .../gcc.target/i386/cond_op_maxmin_q-1.c | 8 ++ .../gcc.target/i386/cond_op_maxmin_q-2.c | 5 ++ .../gcc.target/i386/cond_op_maxmin_ub-1.c | 8 ++ .../gcc.target/i386/cond_op_maxmin_ub-2.c | 6 ++ .../gcc.target/i386/cond_op_maxmin_ud-1.c | 8 ++ .../gcc.target/i386/cond_op_maxmin_ud-2.c | 5 ++ .../gcc.target/i386/cond_op_maxmin_uq-1.c | 8 ++ .../gcc.target/i386/cond_op_maxmin_uq-2.c | 5 ++ .../gcc.target/i386/cond_op_maxmin_uw-1.c | 8 ++ .../gcc.target/i386/cond_op_maxmin_uw-2.c | 6 ++ .../gcc.target/i386/cond_op_maxmin_w-1.c | 8 ++ .../gcc.target/i386/cond_op_maxmin_w-2.c | 6 ++ 25 files changed, 507 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-1.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-2.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-1.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-2.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_b-1.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_b-2.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_d-1.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_d-2.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_double-1.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_double-2.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_float-1.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_float-2.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_q-1.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_q-2.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ub-1.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ub-2.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ud-1.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ud-2.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uq-1.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uq-2.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uw-1.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uw-2.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_w-1.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_w-2.c -- 2.18.1