From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by sourceware.org (Postfix) with ESMTPS id 6919738515E0 for ; Wed, 4 Aug 2021 12:39:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6919738515E0 X-IronPort-AV: E=McAfee;i="6200,9189,10065"; a="213893698" X-IronPort-AV: E=Sophos;i="5.84,294,1620716400"; d="scan'208";a="213893698" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2021 05:39:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,294,1620716400"; d="scan'208";a="420025112" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga003.jf.intel.com with ESMTP; 04 Aug 2021 05:39:33 -0700 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.236.50]) by scymds01.sc.intel.com with ESMTP id 174CdS86027267; Wed, 4 Aug 2021 05:39:32 -0700 From: liuhongt To: gcc-patches@gcc.gnu.org Subject: [PATCH 3/3] [i386] Support cond_{xor, ior, and} for vector integer mode under AVX512. Date: Wed, 4 Aug 2021 20:39:28 +0800 Message-Id: <20210804123928.90586-4-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20210804123928.90586-1-hongtao.liu@intel.com> References: <20210804123928.90586-1-hongtao.liu@intel.com> X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Aug 2021 12:39:36 -0000 gcc/ChangeLog: * config/i386/sse.md (cond_): New expander. gcc/testsuite/ChangeLog: * gcc.target/i386/cond_op_anylogic_d-1.c: New test. * gcc.target/i386/cond_op_anylogic_d-2.c: New test. * gcc.target/i386/cond_op_anylogic_q-1.c: New test. * gcc.target/i386/cond_op_anylogic_q-2.c: New test. --- gcc/config/i386/sse.md | 18 +++++ .../gcc.target/i386/cond_op_anylogic_d-1.c | 38 +++++++++ .../gcc.target/i386/cond_op_anylogic_d-2.c | 78 +++++++++++++++++++ .../gcc.target/i386/cond_op_anylogic_q-1.c | 10 +++ .../gcc.target/i386/cond_op_anylogic_q-2.c | 5 ++ 5 files changed, 149 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-1.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-2.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-1.c create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-2.c diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 51733a3849d..a46a2373547 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -14063,6 +14063,24 @@ (define_expand "3" DONE; }) +(define_expand "cond_" + [(set (match_operand:VI48_AVX512VL 0 "register_operand") + (vec_merge:VI48_AVX512VL + (any_logic:VI48_AVX512VL + (match_operand:VI48_AVX512VL 2 "vector_operand") + (match_operand:VI48_AVX512VL 3 "vector_operand")) + (match_operand:VI48_AVX512VL 4 "nonimm_or_0_operand") + (match_operand: 1 "register_operand")))] + "TARGET_AVX512F" +{ + emit_insn (gen_3_mask (operands[0], + operands[2], + operands[3], + operands[4], + operands[1])); + DONE; +}) + (define_insn "3" [(set (match_operand:VI48_AVX_AVX512F 0 "register_operand" "=x,x,v") (any_logic:VI48_AVX_AVX512F diff --git a/gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-1.c b/gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-1.c new file mode 100644 index 00000000000..8951f4a3a27 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-1.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=skylake-avx512 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump ".COND_AND" "optimized" } } */ +/* { dg-final { scan-tree-dump ".COND_XOR" "optimized" } } */ +/* { dg-final { scan-tree-dump ".COND_IOR" "optimized" } } */ +/* { dg-final { scan-assembler-times "vpxord" 1 } } */ +/* { dg-final { scan-assembler-times "vpord" 1 } } */ +/* { dg-final { scan-assembler-times "vpandd" 1 } } */ + +typedef int int32; +typedef unsigned int uint32; +typedef long long int64; +typedef unsigned long long uint64; + +#ifndef NUM +#define NUM 800 +#endif +#ifndef TYPE +#define TYPE int +#endif + +TYPE a[NUM], b[NUM], c[NUM], d[NUM], e[NUM], j[NUM]; + +#define BIN(OPNAME, OP) \ + void \ + __attribute__ ((noipa,optimize ("O3"))) \ + foo_##OPNAME () \ + { \ + for (int i = 0; i != NUM; i++) \ + if (b[i] < c[i]) \ + a[i] = d[i] OP e[i]; \ + else \ + a[i] = d[i] - e[i]; \ + } + +BIN (and, &); +BIN (ior, |); +BIN (xor, ^); diff --git a/gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-2.c b/gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-2.c new file mode 100644 index 00000000000..23ca4120cf2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-2.c @@ -0,0 +1,78 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512vl -mprefer-vector-width=256" } */ +/* { dg-require-effective-target avx512vl } */ + +#define AVX512VL +#ifndef CHECK +#define CHECK "avx512f-helper.h" +#endif + +#include CHECK + +#include "cond_op_anylogic_d-1.c" +#define BINO2(OPNAME, OP) \ + void \ + __attribute__ ((noipa,optimize ("O2"))) \ + foo_o2_##OPNAME () \ + { \ + for (int i = 0; i != NUM; i++) \ + if (b[i] < c[i]) \ + j[i] = d[i] OP e[i]; \ + else \ + j[i] = d[i] - e[i]; \ + } + +BINO2 (and, &); +BINO2 (ior, |); +BINO2 (xor, ^); + +static void +test_256 (void) +{ + int sign = -1; + for (int i = 0; i != NUM; i++) + { + a[i] = 0; + d[i] = i * 2; + e[i] = i * i * 3 - i * 9 + 153; + b[i] = i * 83; + c[i] = b[i] + sign; + sign *= -1; + j[i] = 1; + } + foo_and (); + foo_o2_and (); + for (int i = 0; i != NUM; i++) + { + if (a[i] != j[i]) + abort (); + a[i] = 0; + b[i] = 1; + } + + foo_xor (); + foo_o2_xor (); + for (int i = 0; i != NUM; i++) + { + if (a[i] != j[i]) + abort (); + a[i] = 0; + j[i] = 1; + } + + foo_ior (); + foo_o2_ior (); + for (int i = 0; i != NUM; i++) + { + if (a[i] != j[i]) + abort (); + a[i] = 0; + j[i] = 1; + } +} + +static void +test_128 () +{ + +} diff --git a/gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-1.c b/gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-1.c new file mode 100644 index 00000000000..cb4770113ad --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=skylake-avx512 -DTYPE=int64 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump ".COND_AND" "optimized" } } */ +/* { dg-final { scan-tree-dump ".COND_XOR" "optimized" } } */ +/* { dg-final { scan-tree-dump ".COND_IOR" "optimized" } } */ +/* { dg-final { scan-assembler-times "vpxorq" 1 } } */ +/* { dg-final { scan-assembler-times "vporq" 1 } } */ +/* { dg-final { scan-assembler-times "vpandq" 1 } } */ + +#include "cond_op_anylogic_d-1.c" diff --git a/gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-2.c b/gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-2.c new file mode 100644 index 00000000000..709babf271e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-2.c @@ -0,0 +1,5 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512vl -mprefer-vector-width=256 -DTYPE=int64" } */ +/* { dg-require-effective-target avx512vl } */ + +#include "cond_op_anylogic_d-2.c" -- 2.18.1