* [PATCH 0/6] rs6000: Support more SSE4.1 intrinsics
@ 2021-08-09 20:23 Paul A. Clarke
2021-08-09 20:23 ` [PATCH 1/6] rs6000: Support SSE4.1 "round" intrinsics Paul A. Clarke
` (5 more replies)
0 siblings, 6 replies; 17+ messages in thread
From: Paul A. Clarke @ 2021-08-09 20:23 UTC (permalink / raw)
To: gcc-patches; +Cc: segher
Paul A. Clarke (6):
rs6000: Support SSE4.1 "round" intrinsics
rs6000: Support SSE4.1 "min" and "max" intrinsics
rs6000: Simplify some SSE4.1 "test" intrinsics
rs6000: Support SSE4.1 "cvt" intrinsics
rs6000: Support more SSE4.1 "cmp", "mul", "pack" intrinsics
rs6000: Guard some x86 intrinsics implementations
gcc/config/rs6000/emmintrin.h | 12 +-
gcc/config/rs6000/pmmintrin.h | 2 +
gcc/config/rs6000/smmintrin.h | 431 ++++++++++++++++--
gcc/config/rs6000/tmmintrin.h | 2 +
gcc/testsuite/gcc.target/powerpc/pr78102.c | 23 +
.../gcc.target/powerpc/sse4_1-packusdw.c | 73 +++
.../gcc.target/powerpc/sse4_1-pcmpeqq.c | 46 ++
.../gcc.target/powerpc/sse4_1-pmaxsb.c | 46 ++
.../gcc.target/powerpc/sse4_1-pmaxsd.c | 46 ++
.../gcc.target/powerpc/sse4_1-pmaxud.c | 47 ++
.../gcc.target/powerpc/sse4_1-pmaxuw.c | 47 ++
.../gcc.target/powerpc/sse4_1-pminsb.c | 46 ++
.../gcc.target/powerpc/sse4_1-pminsd.c | 46 ++
.../gcc.target/powerpc/sse4_1-pminud.c | 47 ++
.../gcc.target/powerpc/sse4_1-pminuw.c | 47 ++
.../gcc.target/powerpc/sse4_1-pmovsxbd.c | 42 ++
.../gcc.target/powerpc/sse4_1-pmovsxbq.c | 42 ++
.../gcc.target/powerpc/sse4_1-pmovsxbw.c | 42 ++
.../gcc.target/powerpc/sse4_1-pmovsxdq.c | 42 ++
.../gcc.target/powerpc/sse4_1-pmovsxwd.c | 42 ++
.../gcc.target/powerpc/sse4_1-pmovsxwq.c | 42 ++
.../gcc.target/powerpc/sse4_1-pmovzxbd.c | 43 ++
.../gcc.target/powerpc/sse4_1-pmovzxbq.c | 43 ++
.../gcc.target/powerpc/sse4_1-pmovzxbw.c | 43 ++
.../gcc.target/powerpc/sse4_1-pmovzxdq.c | 43 ++
.../gcc.target/powerpc/sse4_1-pmovzxwd.c | 43 ++
.../gcc.target/powerpc/sse4_1-pmovzxwq.c | 43 ++
.../gcc.target/powerpc/sse4_1-pmuldq.c | 51 +++
.../gcc.target/powerpc/sse4_1-pmulld.c | 46 ++
.../gcc.target/powerpc/sse4_1-round3.h | 81 ++++
.../gcc.target/powerpc/sse4_1-roundpd.c | 143 ++++++
.../gcc.target/powerpc/sse4_1-roundps.c | 98 ++++
.../gcc.target/powerpc/sse4_1-roundsd.c | 256 +++++++++++
.../gcc.target/powerpc/sse4_1-roundss.c | 208 +++++++++
.../gcc.target/powerpc/sse4_2-pcmpgtq.c | 46 ++
35 files changed, 2341 insertions(+), 59 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/powerpc/pr78102.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-packusdw.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pcmpeqq.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxsb.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxsd.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxud.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxuw.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pminsb.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pminsd.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pminud.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pminuw.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbd.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbq.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbw.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxdq.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwd.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwq.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbd.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbq.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbw.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxdq.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxwd.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxwq.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmuldq.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmulld.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-round3.h
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-roundpd.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-roundps.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-roundsd.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-roundss.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_2-pcmpgtq.c
--
2.27.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/6] rs6000: Support SSE4.1 "round" intrinsics
2021-08-09 20:23 [PATCH 0/6] rs6000: Support more SSE4.1 intrinsics Paul A. Clarke
@ 2021-08-09 20:23 ` Paul A. Clarke
2021-08-18 19:01 ` Bill Schmidt
2021-08-18 22:46 ` Segher Boessenkool
2021-08-09 20:23 ` [PATCH 2/6] rs6000: Support SSE4.1 "min" and "max" intrinsics Paul A. Clarke
` (4 subsequent siblings)
5 siblings, 2 replies; 17+ messages in thread
From: Paul A. Clarke @ 2021-08-09 20:23 UTC (permalink / raw)
To: gcc-patches; +Cc: segher
Suppress exceptions (when specified), by saving, manipulating, and
restoring the FPSCR. Similarly, save, set, and restore the floating-point
rounding mode when required.
No attempt is made to optimize writing the FPSCR (by checking if the new
value would be the same), other than using lighter weight instructions
when possible.
The scalar versions naively use the parallel versions to compute the
single scalar result and then construct the remainder of the result.
Of minor note, the values of _MM_FROUND_TO_NEG_INF and _MM_FROUND_TO_ZERO
are swapped from the corresponding values on x86 so as to match the
corresponding rounding mode values in the Power ISA.
Move implementations of _mm_ceil* and _mm_floor* into _mm_round*, and
convert _mm_ceil* and _mm_floor* into macros. This matches the current
analogous implementations in config/i386/smmintrin.h.
Add tests for _mm_round_pd, _mm_round_ps, _mm_round_sd, _mm_round_ss,
modeled after the very similar "floor" and "ceil" tests.
Include basic tests, plus tests at the boundaries for floating-point
representation, positive and negative, test all of the parameterized
rounding modes as well as the C99 rounding modes and interactions
between the two.
Exceptions are not explicitly tested.
2021-08-09 Paul A. Clarke <pc@us.ibm.com>
gcc
* config/rs6000/smmintrin.h (_mm_round_pd, _mm_round_ps,
_mm_round_sd, _mm_round_ss, _MM_FROUND_TO_NEAREST_INT
_MM_FROUND_TO_ZERO, _MM_FROUND_TO_POS_INF, _MM_FROUND_TO_NEG_INF,
_MM_FROUND_CUR_DIRECTION, _MM_FROUND_RAISE_EXC, _MM_FROUND_NO_EXC
_MM_FROUND_NINT, _MM_FROUND_FLOOR, _MM_FROUND_CEIL, _MM_FROUND_TRUNC,
_MM_FROUND_RINT, _MM_FROUND_NEARBYINT): New.
* config/rs6000/smmintrin.h (_mm_ceil_pd, _mm_ceil_ps, _mm_ceil_sd,
_mm_ceil_ss, _mm_floor_pd, _mm_floor_ps, _mm_floor_sd, _mm_floor_ss):
Convert from function to macro.
gcc/testsuite
* gcc.target/powerpc/sse4_1-round3.h: New.
* gcc.target/powerpc/sse4_1-roundpd.c: New.
* gcc.target/powerpc/sse4_1-roundps.c: New.
* gcc.target/powerpc/sse4_1-roundsd.c: New.
* gcc.target/powerpc/sse4_1-roundss.c: New.
---
gcc/config/rs6000/smmintrin.h | 246 ++++++++++++-----
.../gcc.target/powerpc/sse4_1-round3.h | 81 ++++++
.../gcc.target/powerpc/sse4_1-roundpd.c | 143 ++++++++++
.../gcc.target/powerpc/sse4_1-roundps.c | 98 +++++++
.../gcc.target/powerpc/sse4_1-roundsd.c | 256 ++++++++++++++++++
.../gcc.target/powerpc/sse4_1-roundss.c | 208 ++++++++++++++
6 files changed, 968 insertions(+), 64 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-round3.h
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-roundpd.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-roundps.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-roundsd.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-roundss.c
diff --git a/gcc/config/rs6000/smmintrin.h b/gcc/config/rs6000/smmintrin.h
index 3767a67eada7..862e78ac7d60 100644
--- a/gcc/config/rs6000/smmintrin.h
+++ b/gcc/config/rs6000/smmintrin.h
@@ -42,6 +42,188 @@
#include <altivec.h>
#include <tmmintrin.h>
+/* Rounding mode macros. */
+#define _MM_FROUND_TO_NEAREST_INT 0x00
+#define _MM_FROUND_TO_ZERO 0x01
+#define _MM_FROUND_TO_POS_INF 0x02
+#define _MM_FROUND_TO_NEG_INF 0x03
+#define _MM_FROUND_CUR_DIRECTION 0x04
+
+#define _MM_FROUND_NINT \
+ (_MM_FROUND_TO_NEAREST_INT | _MM_FROUND_RAISE_EXC)
+#define _MM_FROUND_FLOOR \
+ (_MM_FROUND_TO_NEG_INF | _MM_FROUND_RAISE_EXC)
+#define _MM_FROUND_CEIL \
+ (_MM_FROUND_TO_POS_INF | _MM_FROUND_RAISE_EXC)
+#define _MM_FROUND_TRUNC \
+ (_MM_FROUND_TO_ZERO | _MM_FROUND_RAISE_EXC)
+#define _MM_FROUND_RINT \
+ (_MM_FROUND_CUR_DIRECTION | _MM_FROUND_RAISE_EXC)
+#define _MM_FROUND_NEARBYINT \
+ (_MM_FROUND_CUR_DIRECTION | _MM_FROUND_NO_EXC)
+
+#define _MM_FROUND_RAISE_EXC 0x00
+#define _MM_FROUND_NO_EXC 0x08
+
+__inline __m128d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_round_pd (__m128d __A, int __rounding)
+{
+ __v2df __r;
+ union {
+ double __fr;
+ long long __fpscr;
+ } __save, __tmp;
+
+ if (__rounding & _MM_FROUND_NO_EXC)
+ {
+ /* Save enabled exceptions, and disable all exceptions.
+ Pre-POWER9, mffsce decodes to mffs, requiring the additional
+ mtfsf, below, to disable exceptions. */
+ __asm__ __volatile__ (
+ ".machine push; .machine \"power9\"; mffsce %0; .machine pop"
+ : "=f" (__save.__fr));
+ __save.__fpscr &= 0xf8;
+ __tmp.__fpscr = __save.__fpscr;
+#ifndef _ARCH_PWR9
+ __tmp.__fpscr &= ~0xf8;
+ __builtin_mtfsf (0x01, __tmp.__fr);
+#endif
+ }
+
+ switch (__rounding)
+ {
+ case _MM_FROUND_TO_NEAREST_INT:
+ __tmp.__fr = __builtin_mffsl ();
+ __attribute__((fallthrough));
+ case _MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC:
+ {
+ __builtin_set_fpscr_rn (0b00);
+ __r = vec_rint ((__v2df) __A);
+ __builtin_set_fpscr_rn (__tmp.__fpscr);
+ }
+ break;
+ case _MM_FROUND_TO_NEG_INF:
+ case _MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC:
+ __r = vec_floor ((__v2df) __A);
+ break;
+ case _MM_FROUND_TO_POS_INF:
+ case _MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC:
+ __r = vec_ceil ((__v2df) __A);
+ break;
+ case _MM_FROUND_TO_ZERO:
+ case _MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC:
+ __r = vec_trunc ((__v2df) __A);
+ break;
+ case _MM_FROUND_CUR_DIRECTION:
+ __r = vec_rint ((__v2df) __A);
+ break;
+ }
+ if (__rounding & _MM_FROUND_NO_EXC)
+ {
+ /* Restore enabled exceptions. */
+ __tmp.__fr = __builtin_mffsl ();
+ __tmp.__fpscr |= __save.__fpscr & 0xf8;
+ __builtin_mtfsf (0x01, __tmp.__fr);
+ }
+ return (__m128d) __r;
+}
+
+__inline __m128d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_round_sd (__m128d __A, __m128d __B, int __rounding)
+{
+ __B = _mm_round_pd (__B, __rounding);
+ __v2df __r = { ((__v2df)__B)[0], ((__v2df) __A)[1] };
+ return (__m128d) __r;
+}
+
+__inline __m128
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_round_ps (__m128 __A, int __rounding)
+{
+ __v4sf __r;
+ union {
+ double __fr;
+ long long __fpscr;
+ } __save, __tmp;
+
+ if (__rounding & _MM_FROUND_NO_EXC)
+ {
+ /* Save enabled exceptions, and disable all exceptions.
+ Pre-POWER9, mffsce decodes to mffs, requiring the additional
+ mtfsf, below, to disable exceptions. */
+ __asm__ __volatile__ (
+ ".machine push; .machine \"power9\"; mffsce %0; .machine pop"
+ : "=f" (__save.__fr));
+ __save.__fpscr &= 0xf8;
+ __tmp.__fpscr = __save.__fpscr;
+#ifndef _ARCH_PWR9
+ __tmp.__fpscr &= ~0xf8;
+ __builtin_mtfsf (0x01, __tmp.__fr);
+#endif
+ }
+
+ switch (__rounding)
+ {
+ case _MM_FROUND_TO_NEAREST_INT:
+ __tmp.__fr = __builtin_mffsl ();
+ __attribute__((fallthrough));
+ case _MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC:
+ {
+ __builtin_set_fpscr_rn (0b00);
+ __r = vec_rint ((__v4sf) __A);
+ __builtin_set_fpscr_rn (__tmp.__fpscr);
+ }
+ break;
+ case _MM_FROUND_TO_NEG_INF:
+ case _MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC:
+ __r = vec_floor ((__v4sf) __A);
+ break;
+ case _MM_FROUND_TO_POS_INF:
+ case _MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC:
+ __r = vec_ceil ((__v4sf) __A);
+ break;
+ case _MM_FROUND_TO_ZERO:
+ case _MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC:
+ __r = vec_trunc ((__v4sf) __A);
+ break;
+ case _MM_FROUND_CUR_DIRECTION:
+ __r = vec_rint ((__v4sf) __A);
+ break;
+ }
+ if (__rounding & _MM_FROUND_NO_EXC)
+ {
+ /* Restore enabled exceptions. */
+ __tmp.__fr = __builtin_mffsl ();
+ __tmp.__fpscr |= __save.__fpscr & 0xf8;
+ __builtin_mtfsf (0x01, __tmp.__fr);
+ }
+ return (__m128) __r;
+}
+
+__inline __m128
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_round_ss (__m128 __A, __m128 __B, int __rounding)
+{
+ __B = _mm_round_ps (__B, __rounding);
+ __v4sf __r = (__v4sf) __A;
+ __r[0] = ((__v4sf)__B)[0];
+ return (__m128) __r;
+}
+
+#define _mm_ceil_pd(V) _mm_round_pd ((V), _MM_FROUND_CEIL)
+#define _mm_ceil_sd(D, V) _mm_round_sd ((D), (V), _MM_FROUND_CEIL)
+
+#define _mm_floor_pd(V) _mm_round_pd((V), _MM_FROUND_FLOOR)
+#define _mm_floor_sd(D, V) _mm_round_sd ((D), (V), _MM_FROUND_FLOOR)
+
+#define _mm_ceil_ps(V) _mm_round_ps ((V), _MM_FROUND_CEIL)
+#define _mm_ceil_ss(D, V) _mm_round_ss ((D), (V), _MM_FROUND_CEIL)
+
+#define _mm_floor_ps(V) _mm_round_ps ((V), _MM_FROUND_FLOOR)
+#define _mm_floor_ss(D, V) _mm_round_ss ((D), (V), _MM_FROUND_FLOOR)
+
extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_insert_epi8 (__m128i const __A, int const __D, int const __N)
{
@@ -232,70 +414,6 @@ _mm_test_mix_ones_zeros (__m128i __A, __m128i __mask)
return any_ones * any_zeros;
}
-__inline __m128d
-__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-_mm_ceil_pd (__m128d __A)
-{
- return (__m128d) vec_ceil ((__v2df) __A);
-}
-
-__inline __m128d
-__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-_mm_ceil_sd (__m128d __A, __m128d __B)
-{
- __v2df __r = vec_ceil ((__v2df) __B);
- __r[1] = ((__v2df) __A)[1];
- return (__m128d) __r;
-}
-
-__inline __m128d
-__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-_mm_floor_pd (__m128d __A)
-{
- return (__m128d) vec_floor ((__v2df) __A);
-}
-
-__inline __m128d
-__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-_mm_floor_sd (__m128d __A, __m128d __B)
-{
- __v2df __r = vec_floor ((__v2df) __B);
- __r[1] = ((__v2df) __A)[1];
- return (__m128d) __r;
-}
-
-__inline __m128
-__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-_mm_ceil_ps (__m128 __A)
-{
- return (__m128) vec_ceil ((__v4sf) __A);
-}
-
-__inline __m128
-__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-_mm_ceil_ss (__m128 __A, __m128 __B)
-{
- __v4sf __r = (__v4sf) __A;
- __r[0] = __builtin_ceil (((__v4sf) __B)[0]);
- return __r;
-}
-
-__inline __m128
-__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-_mm_floor_ps (__m128 __A)
-{
- return (__m128) vec_floor ((__v4sf) __A);
-}
-
-__inline __m128
-__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-_mm_floor_ss (__m128 __A, __m128 __B)
-{
- __v4sf __r = (__v4sf) __A;
- __r[0] = __builtin_floor (((__v4sf) __B)[0]);
- return __r;
-}
-
/* Return horizontal packed word minimum and its index in bits [15:0]
and bits [18:16] respectively. */
__inline __m128i
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-round3.h b/gcc/testsuite/gcc.target/powerpc/sse4_1-round3.h
new file mode 100644
index 000000000000..de6cbf7be438
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-round3.h
@@ -0,0 +1,81 @@
+#include <smmintrin.h>
+#include <fenv.h>
+#include "sse4_1-check.h"
+
+#define DIM(a) (sizeof (a) / sizeof (a)[0])
+
+static int roundings[] =
+ {
+ _MM_FROUND_TO_NEAREST_INT,
+ _MM_FROUND_TO_NEG_INF,
+ _MM_FROUND_TO_POS_INF,
+ _MM_FROUND_TO_ZERO,
+ _MM_FROUND_CUR_DIRECTION
+ };
+
+static int modes[] =
+ {
+ FE_TONEAREST,
+ FE_UPWARD,
+ FE_DOWNWARD,
+ FE_TOWARDZERO
+ };
+
+static void
+TEST (void)
+{
+ int i, j, ri, mi, round_save;
+
+ round_save = fegetround ();
+ for (mi = 0; mi < DIM (modes); mi++) {
+ fesetround (modes[mi]);
+ for (i = 0; i < DIM (data); i++) {
+ for (ri = 0; ri < DIM (roundings); ri++) {
+ union value guess;
+ union value *current_answers = answers[ri];
+ switch ( roundings[ri] ) {
+ case _MM_FROUND_TO_NEAREST_INT:
+ guess.x = ROUND_INTRIN (data[i].value1.x, data[i].value2.x,
+ _MM_FROUND_TO_NEAREST_INT);
+ break;
+ case _MM_FROUND_TO_NEG_INF:
+ guess.x = ROUND_INTRIN (data[i].value1.x, data[i].value2.x,
+ _MM_FROUND_TO_NEG_INF);
+ break;
+ case _MM_FROUND_TO_POS_INF:
+ guess.x = ROUND_INTRIN (data[i].value1.x, data[i].value2.x,
+ _MM_FROUND_TO_POS_INF);
+ break;
+ case _MM_FROUND_TO_ZERO:
+ guess.x = ROUND_INTRIN (data[i].value1.x, data[i].value2.x,
+ _MM_FROUND_TO_ZERO);
+ break;
+ case _MM_FROUND_CUR_DIRECTION:
+ guess.x = ROUND_INTRIN (data[i].value1.x, data[i].value2.x,
+ _MM_FROUND_CUR_DIRECTION);
+ switch ( modes[mi] ) {
+ case FE_TONEAREST:
+ current_answers = answers_NEAREST_INT;
+ break;
+ case FE_UPWARD:
+ current_answers = answers_POS_INF;
+ break;
+ case FE_DOWNWARD:
+ current_answers = answers_NEG_INF;
+ break;
+ case FE_TOWARDZERO:
+ current_answers = answers_ZERO;
+ break;
+ }
+ break;
+ default:
+ abort ();
+ }
+ for (j = 0; j < DIM (guess.f); j++)
+ if (guess.f[j] != current_answers[i].f[j])
+ abort ();
+ }
+ }
+ }
+ fesetround (round_save);
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-roundpd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-roundpd.c
new file mode 100644
index 000000000000..42fa453b9fd3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-roundpd.c
@@ -0,0 +1,143 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+
+#define NO_WARN_X86_INTRINSICS 1
+#include <smmintrin.h>
+
+#define VEC_T __m128d
+#define FP_T double
+
+#define ROUND_INTRIN(x, ignored, mode) _mm_round_pd (x, mode)
+
+#include "sse4_1-round-data.h"
+
+struct data2 data[] = {
+ { .value1 = { .f = { 0.00, 0.25 } } },
+ { .value1 = { .f = { 0.50, 0.75 } } },
+
+ { .value1 = { .f = { 0x1.ffffffffffffcp+50, 0x1.ffffffffffffdp+50 } } },
+ { .value1 = { .f = { 0x1.ffffffffffffep+50, 0x1.fffffffffffffp+50 } } },
+ { .value1 = { .f = { 0x1.0000000000000p+51, 0x1.0000000000001p+51 } } },
+ { .value1 = { .f = { 0x1.0000000000002p+51, 0x1.0000000000003p+51 } } },
+
+ { .value1 = { .f = { 0x1.ffffffffffffep+51, 0x1.fffffffffffffp+51 } } },
+ { .value1 = { .f = { 0x1.0000000000000p+52, 0x1.0000000000001p+52 } } },
+
+ { .value1 = { .f = { -0x1.0000000000001p+52, -0x1.0000000000000p+52 } } },
+ { .value1 = { .f = { -0x1.fffffffffffffp+51, -0x1.ffffffffffffep+51 } } },
+
+ { .value1 = { .f = { -0x1.0000000000004p+51, -0x1.0000000000002p+51 } } },
+ { .value1 = { .f = { -0x1.0000000000001p+51, -0x1.0000000000000p+51 } } },
+ { .value1 = { .f = { -0x1.ffffffffffffcp+50, -0x1.ffffffffffffep+50 } } },
+ { .value1 = { .f = { -0x1.ffffffffffffdp+50, -0x1.ffffffffffffcp+50 } } },
+
+ { .value1 = { .f = { -1.00, -0.75 } } },
+ { .value1 = { .f = { -0.50, -0.25 } } }
+};
+
+union value answers_NEAREST_INT[] = {
+ { .f = { 0.00, 0.00 } },
+ { .f = { 0.00, 1.00 } },
+
+ { .f = { 0x1.ffffffffffffcp+50, 0x1.ffffffffffffcp+50 } },
+ { .f = { 0x1.0000000000000p+51, 0x1.0000000000000p+51 } },
+ { .f = { 0x1.0000000000000p+51, 0x1.0000000000000p+51 } },
+ { .f = { 0x1.0000000000002p+51, 0x1.0000000000004p+51 } },
+
+ { .f = { 0x1.ffffffffffffep+51, 0x1.0000000000000p+52 } },
+ { .f = { 0x1.0000000000000p+52, 0x1.0000000000001p+52 } },
+
+ { .f = { -0x1.0000000000001p+52, -0x1.0000000000000p+52 } },
+ { .f = { -0x1.0000000000000p+52, -0x1.ffffffffffffep+51 } },
+
+ { .f = { -0x1.0000000000004p+51, -0x1.0000000000002p+51 } },
+ { .f = { -0x1.0000000000000p+51, -0x1.0000000000000p+51 } },
+ { .f = { -0x1.ffffffffffffcp+50, -0x1.0000000000000p+51 } },
+ { .f = { -0x1.ffffffffffffcp+50, -0x1.ffffffffffffcp+50 } },
+
+ { .f = { -1.00, -1.00 } },
+ { .f = { 0.00, 0.00 } }
+};
+
+union value answers_NEG_INF[] = {
+ { .f = { 0.00, 0.00 } },
+ { .f = { 0.00, 0.00 } },
+
+ { .f = { 0x1.ffffffffffffcp+50, 0x1.ffffffffffffcp+50 } },
+ { .f = { 0x1.ffffffffffffcp+50, 0x1.ffffffffffffcp+50 } },
+ { .f = { 0x1.0000000000000p+51, 0x1.0000000000000p+51 } },
+ { .f = { 0x1.0000000000002p+51, 0x1.0000000000002p+51 } },
+
+ { .f = { 0x1.ffffffffffffep+51, 0x1.ffffffffffffep+51 } },
+ { .f = { 0x1.0000000000000p+52, 0x1.0000000000001p+52 } },
+
+ { .f = { -0x1.0000000000001p+52, -0x1.0000000000000p+52 } },
+ { .f = { -0x1.0000000000000p+52, -0x1.ffffffffffffep+51 } },
+
+ { .f = { -0x1.0000000000004p+51, -0x1.0000000000002p+51 } },
+ { .f = { -0x1.0000000000002p+51, -0x1.0000000000000p+51 } },
+ { .f = { -0x1.ffffffffffffcp+50, -0x1.0000000000000p+51 } },
+ { .f = { -0x1.0000000000000p+51, -0x1.ffffffffffffcp+50 } },
+
+ { .f = { -1.00, -1.00 } },
+ { .f = { -1.00, -1.00 } }
+};
+
+union value answers_POS_INF[] = {
+ { .f = { 0.00, 1.00 } },
+ { .f = { 1.00, 1.00 } },
+
+ { .f = { 0x1.ffffffffffffcp+50, 0x1.0000000000000p+51 } },
+ { .f = { 0x1.0000000000000p+51, 0x1.0000000000000p+51 } },
+ { .f = { 0x1.0000000000000p+51, 0x1.0000000000002p+51 } },
+ { .f = { 0x1.0000000000002p+51, 0x1.0000000000004p+51 } },
+
+ { .f = { 0x1.ffffffffffffep+51, 0x1.0000000000000p+52 } },
+ { .f = { 0x1.0000000000000p+52, 0x1.0000000000001p+52 } },
+
+ { .f = { -0x1.0000000000001p+52, -0x1.0000000000000p+52 } },
+ { .f = { -0x1.ffffffffffffep+51, -0x1.ffffffffffffep+51 } },
+
+ { .f = { -0x1.0000000000004p+51, -0x1.0000000000002p+51 } },
+ { .f = { -0x1.0000000000000p+51, -0x1.0000000000000p+51 } },
+ { .f = { -0x1.ffffffffffffcp+50, -0x1.ffffffffffffcp+50 } },
+ { .f = { -0x1.ffffffffffffcp+50, -0x1.ffffffffffffcp+50 } },
+
+ { .f = { -1.00, 0.00 } },
+ { .f = { 0.00, 0.00 } }
+};
+
+union value answers_ZERO[] = {
+ { .f = { 0.00, 0.00 } },
+ { .f = { 0.00, 0.00 } },
+
+ { .f = { 0x1.ffffffffffffcp+50, 0x1.ffffffffffffcp+50 } },
+ { .f = { 0x1.ffffffffffffcp+50, 0x1.ffffffffffffcp+50 } },
+ { .f = { 0x1.0000000000000p+51, 0x1.0000000000000p+51 } },
+ { .f = { 0x1.0000000000002p+51, 0x1.0000000000002p+51 } },
+
+ { .f = { 0x1.ffffffffffffep+51, 0x1.ffffffffffffep+51 } },
+ { .f = { 0x1.0000000000000p+52, 0x1.0000000000001p+52 } },
+
+ { .f = { -0x1.0000000000001p+52, -0x1.0000000000000p+52 } },
+ { .f = { -0x1.ffffffffffffep+51, -0x1.ffffffffffffep+51 } },
+
+ { .f = { -0x1.0000000000004p+51, -0x1.0000000000002p+51 } },
+ { .f = { -0x1.0000000000000p+51, -0x1.0000000000000p+51 } },
+ { .f = { -0x1.ffffffffffffcp+50, -0x1.ffffffffffffcp+50 } },
+ { .f = { -0x1.ffffffffffffcp+50, -0x1.ffffffffffffcp+50 } },
+
+ { .f = { -1.00, 0.00 } },
+ { .f = { 0.00, 0.00 } }
+};
+
+union value *answers[] = {
+ answers_NEAREST_INT,
+ answers_NEG_INF,
+ answers_POS_INF,
+ answers_ZERO,
+ 0 /* CUR_DIRECTION answers depend on current rounding mode. */
+};
+
+#include "sse4_1-round3.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-roundps.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-roundps.c
new file mode 100644
index 000000000000..e36d325992db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-roundps.c
@@ -0,0 +1,98 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+
+#define NO_WARN_X86_INTRINSICS 1
+#include <smmintrin.h>
+
+#define VEC_T __m128
+#define FP_T float
+
+#define ROUND_INTRIN(x, ignored, mode) _mm_round_ps (x, mode)
+
+#include "sse4_1-round-data.h"
+
+struct data2 data[] = {
+ { .value1 = { .f = { 0.00, 0.25, 0.50, 0.75 } } },
+
+ { .value1 = { .f = { 0x1.fffff8p+21, 0x1.fffffap+21,
+ 0x1.fffffcp+21, 0x1.fffffep+21 } } },
+ { .value1 = { .f = { 0x1.fffffap+22, 0x1.fffffcp+22,
+ 0x1.fffffep+22, 0x1.fffffep+23 } } },
+ { .value1 = { .f = { -0x1.fffffep+23, -0x1.fffffep+22,
+ -0x1.fffffcp+22, -0x1.fffffap+22 } } },
+ { .value1 = { .f = { -0x1.fffffep+21, -0x1.fffffcp+21,
+ -0x1.fffffap+21, -0x1.fffff8p+21 } } },
+
+ { .value1 = { .f = { -1.00, -0.75, -0.50, -0.25 } } }
+};
+
+union value answers_NEAREST_INT[] = {
+ { .f = { 0.00, 0.00, 0.00, 1.00 } },
+
+ { .f = { 0x1.fffff8p+21, 0x1.fffff8p+21,
+ 0x1.000000p+22, 0x1.000000p+22 } },
+ { .f = { 0x1.fffff8p+22, 0x1.fffffcp+22,
+ 0x1.000000p+23, 0x1.fffffep+23 } },
+ { .f = { -0x1.fffffep+23, -0x1.000000p+23,
+ -0x1.fffffcp+22, -0x1.fffff8p+22 } },
+ { .f = { -0x1.000000p+22, -0x1.000000p+22,
+ -0x1.fffff8p+21, -0x1.fffff8p+21 } },
+
+ { .f = { -1.00, -1.00, 0.00, 0.00 } }
+};
+
+union value answers_NEG_INF[] = {
+ { .f = { 0.00, 0.00, 0.00, 0.00 } },
+
+ { .f = { 0x1.fffff8p+21, 0x1.fffff8p+21,
+ 0x1.fffff8p+21, 0x1.fffff8p+21 } },
+ { .f = { 0x1.fffff8p+22, 0x1.fffffcp+22,
+ 0x1.fffffcp+22, 0x1.fffffep+23 } },
+ { .f = { -0x1.fffffep+23, -0x1.000000p+23,
+ -0x1.fffffcp+22, -0x1.fffffcp+22 } },
+ { .f = { -0x1.000000p+22, -0x1.000000p+22,
+ -0x1.000000p+22, -0x1.fffff8p+21 } },
+
+ { .f = { -1.00, -1.00, -1.00, -1.00 } }
+};
+
+union value answers_POS_INF[] = {
+ { .f = { 0.00, 1.00, 1.00, 1.00 } },
+
+ { .f = { 0x1.fffff8p+21, 0x1.000000p+22,
+ 0x1.000000p+22, 0x1.000000p+22 } },
+ { .f = { 0x1.fffffcp+22, 0x1.fffffcp+22,
+ 0x1.000000p+23, 0x1.fffffep+23 } },
+ { .f = { -0x1.fffffep+23, -0x1.fffffcp+22,
+ -0x1.fffffcp+22, -0x1.fffff8p+22 } },
+ { .f = { -0x1.fffff8p+21, -0x1.fffff8p+21,
+ -0x1.fffff8p+21, -0x1.fffff8p+21 } },
+
+ { .f = { -1.00, 0.00, 0.00, 0.00 } }
+};
+
+union value answers_ZERO[] = {
+ { .f = { 0.00, 0.00, 0.00, 0.00 } },
+
+ { .f = { 0x1.fffff8p+21, 0x1.fffff8p+21,
+ 0x1.fffff8p+21, 0x1.fffff8p+21 } },
+ { .f = { 0x1.fffff8p+22, 0x1.fffffcp+22,
+ 0x1.fffffcp+22, 0x1.fffffep+23 } },
+ { .f = { -0x1.fffffep+23, -0x1.fffffcp+22,
+ -0x1.fffffcp+22, -0x1.fffff8p+22 } },
+ { .f = { -0x1.fffff8p+21, -0x1.fffff8p+21,
+ -0x1.fffff8p+21, -0x1.fffff8p+21 } },
+
+ { .f = { -1.00, 0.00, 0.00, 0.00 } }
+};
+
+union value *answers[] = {
+ answers_NEAREST_INT,
+ answers_NEG_INF,
+ answers_POS_INF,
+ answers_ZERO,
+ 0 /* CUR_DIRECTION answers depend on current rounding mode. */
+};
+
+#include "sse4_1-round3.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-roundsd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-roundsd.c
new file mode 100644
index 000000000000..00205dbd19bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-roundsd.c
@@ -0,0 +1,256 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+
+#include <stdio.h>
+#define NO_WARN_X86_INTRINSICS 1
+#include <smmintrin.h>
+
+#define VEC_T __m128d
+#define FP_T double
+
+#define ROUND_INTRIN(x, y, mode) _mm_round_sd (x, y, mode)
+
+#include "sse4_1-round-data.h"
+
+static struct data2 data[] = {
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { 0.00, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { 0.25, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { 0.50, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { 0.75, IGNORED } } },
+
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { 0x1.ffffffffffffcp+50, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { 0x1.ffffffffffffdp+50, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { 0x1.ffffffffffffep+50, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { 0x1.fffffffffffffp+50, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { 0x1.0000000000000p+51, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { 0x1.0000000000001p+51, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { 0x1.0000000000002p+51, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { 0x1.0000000000003p+51, IGNORED } } },
+
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { 0x1.ffffffffffffep+51, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { 0x1.fffffffffffffp+51, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { 0x1.0000000000000p+52, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { 0x1.0000000000001p+52, IGNORED } } },
+
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { -0x1.0000000000001p+52, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { -0x1.0000000000000p+52, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { -0x1.fffffffffffffp+51, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { -0x1.ffffffffffffep+51, IGNORED } } },
+
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { -0x1.0000000000004p+51, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { -0x1.0000000000002p+51, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { -0x1.0000000000001p+51, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { -0x1.0000000000000p+51, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { -0x1.ffffffffffffcp+50, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { -0x1.ffffffffffffep+50, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { -0x1.ffffffffffffdp+50, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { -0x1.ffffffffffffcp+50, IGNORED } } },
+
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { -1.00, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { -0.75, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { -0.50, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH } },
+ .value2 = { .f = { -0.25, IGNORED } } }
+};
+
+static union value answers_NEAREST_INT[] = {
+ { .f = { 0.00, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH } },
+ { .f = { 1.00, PASSTHROUGH } },
+
+ { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
+ { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
+ { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { 0x1.0000000000002p+51, PASSTHROUGH } },
+ { .f = { 0x1.0000000000004p+51, PASSTHROUGH } },
+
+ { .f = { 0x1.ffffffffffffep+51, PASSTHROUGH } },
+ { .f = { 0x1.0000000000000p+52, PASSTHROUGH } },
+ { .f = { 0x1.0000000000000p+52, PASSTHROUGH } },
+ { .f = { 0x1.0000000000001p+52, PASSTHROUGH } },
+
+ { .f = { -0x1.0000000000001p+52, PASSTHROUGH } },
+ { .f = { -0x1.0000000000000p+52, PASSTHROUGH } },
+ { .f = { -0x1.0000000000000p+52, PASSTHROUGH } },
+ { .f = { -0x1.ffffffffffffep+51, PASSTHROUGH } },
+
+ { .f = { -0x1.0000000000004p+51, PASSTHROUGH } },
+ { .f = { -0x1.0000000000002p+51, PASSTHROUGH } },
+ { .f = { -0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { -0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
+ { .f = { -0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
+ { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
+
+ { .f = { -1.00, PASSTHROUGH } },
+ { .f = { -1.00, PASSTHROUGH } },
+ { .f = { -0.00, PASSTHROUGH } },
+ { .f = { -0.00, PASSTHROUGH } }
+};
+
+static union value answers_NEG_INF[] = {
+ { .f = { 0.00, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH } },
+
+ { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
+ { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
+ { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
+ { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
+ { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { 0x1.0000000000002p+51, PASSTHROUGH } },
+ { .f = { 0x1.0000000000002p+51, PASSTHROUGH } },
+
+ { .f = { 0x1.ffffffffffffep+51, PASSTHROUGH } },
+ { .f = { 0x1.ffffffffffffep+51, PASSTHROUGH } },
+ { .f = { 0x1.0000000000000p+52, PASSTHROUGH } },
+ { .f = { 0x1.0000000000001p+52, PASSTHROUGH } },
+
+ { .f = { -0x1.0000000000001p+52, PASSTHROUGH } },
+ { .f = { -0x1.0000000000000p+52, PASSTHROUGH } },
+ { .f = { -0x1.0000000000000p+52, PASSTHROUGH } },
+ { .f = { -0x1.ffffffffffffep+51, PASSTHROUGH } },
+
+ { .f = { -0x1.0000000000004p+51, PASSTHROUGH } },
+ { .f = { -0x1.0000000000002p+51, PASSTHROUGH } },
+ { .f = { -0x1.0000000000002p+51, PASSTHROUGH } },
+ { .f = { -0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
+ { .f = { -0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { -0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
+
+ { .f = { -1.00, PASSTHROUGH } },
+ { .f = { -1.00, PASSTHROUGH } },
+ { .f = { -1.00, PASSTHROUGH } },
+ { .f = { -1.00, PASSTHROUGH } }
+};
+
+static union value answers_POS_INF[] = {
+ { .f = { 0.00, PASSTHROUGH } },
+ { .f = { 1.00, PASSTHROUGH } },
+ { .f = { 1.00, PASSTHROUGH } },
+ { .f = { 1.00, PASSTHROUGH } },
+
+ { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
+ { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { 0x1.0000000000002p+51, PASSTHROUGH } },
+ { .f = { 0x1.0000000000002p+51, PASSTHROUGH } },
+ { .f = { 0x1.0000000000004p+51, PASSTHROUGH } },
+
+ { .f = { 0x1.ffffffffffffep+51, PASSTHROUGH } },
+ { .f = { 0x1.0000000000000p+52, PASSTHROUGH } },
+ { .f = { 0x1.0000000000000p+52, PASSTHROUGH } },
+ { .f = { 0x1.0000000000001p+52, PASSTHROUGH } },
+
+ { .f = { -0x1.0000000000001p+52, PASSTHROUGH } },
+ { .f = { -0x1.0000000000000p+52, PASSTHROUGH } },
+ { .f = { -0x1.ffffffffffffep+51, PASSTHROUGH } },
+ { .f = { -0x1.ffffffffffffep+51, PASSTHROUGH } },
+
+ { .f = { -0x1.0000000000004p+51, PASSTHROUGH } },
+ { .f = { -0x1.0000000000002p+51, PASSTHROUGH } },
+ { .f = { -0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { -0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
+ { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
+ { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
+ { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
+
+ { .f = { -1.00, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH } }
+};
+
+static union value answers_ZERO[] = {
+ { .f = { 0.00, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH } },
+
+ { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
+ { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
+ { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
+ { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
+ { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { 0x1.0000000000002p+51, PASSTHROUGH } },
+ { .f = { 0x1.0000000000002p+51, PASSTHROUGH } },
+
+ { .f = { 0x1.ffffffffffffep+51, PASSTHROUGH } },
+ { .f = { 0x1.ffffffffffffep+51, PASSTHROUGH } },
+ { .f = { 0x1.0000000000000p+52, PASSTHROUGH } },
+ { .f = { 0x1.0000000000001p+52, PASSTHROUGH } },
+
+ { .f = { -0x1.0000000000001p+52, PASSTHROUGH } },
+ { .f = { -0x1.0000000000000p+52, PASSTHROUGH } },
+ { .f = { -0x1.ffffffffffffep+51, PASSTHROUGH } },
+ { .f = { -0x1.ffffffffffffep+51, PASSTHROUGH } },
+
+ { .f = { -0x1.0000000000004p+51, PASSTHROUGH } },
+ { .f = { -0x1.0000000000002p+51, PASSTHROUGH } },
+ { .f = { -0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { -0x1.0000000000000p+51, PASSTHROUGH } },
+ { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
+ { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
+ { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
+ { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
+
+ { .f = { -1.00, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH } }
+};
+
+union value *answers[] = {
+ answers_NEAREST_INT,
+ answers_NEG_INF,
+ answers_POS_INF,
+ answers_ZERO,
+ 0 /* CUR_DIRECTION answers depend on current rounding mode. */
+};
+
+#include "sse4_1-round3.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-roundss.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-roundss.c
new file mode 100644
index 000000000000..b9a8eae31f2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-roundss.c
@@ -0,0 +1,208 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+
+#include <stdio.h>
+#define NO_WARN_X86_INTRINSICS 1
+#include <smmintrin.h>
+
+#define VEC_T __m128
+#define FP_T float
+
+#define ROUND_INTRIN(x, y, mode) _mm_round_ss (x, y, mode)
+
+#include "sse4_1-round-data.h"
+
+static struct data2 data[] = {
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { 0.00, IGNORED, IGNORED, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { 0.25, IGNORED, IGNORED, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { 0.50, IGNORED, IGNORED, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { 0.75, IGNORED, IGNORED, IGNORED } } },
+
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { 0x1.fffff8p+21, IGNORED, IGNORED, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { 0x1.fffffap+21, IGNORED, IGNORED, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { 0x1.fffffcp+21, IGNORED, IGNORED, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { 0x1.fffffep+21, IGNORED, IGNORED, IGNORED } } },
+
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { 0x1.fffffap+22, IGNORED, IGNORED, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { 0x1.fffffcp+22, IGNORED, IGNORED, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { 0x1.fffffep+22, IGNORED, IGNORED, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { 0x1.fffffep+23, IGNORED, IGNORED, IGNORED } } },
+
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { -0x1.fffffep+23, IGNORED, IGNORED, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { -0x1.fffffep+22, IGNORED, IGNORED, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { -0x1.fffffcp+22, IGNORED, IGNORED, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { -0x1.fffffap+22, IGNORED, IGNORED, IGNORED } } },
+
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { -0x1.fffffep+21, IGNORED, IGNORED, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { -0x1.fffffcp+21, IGNORED, IGNORED, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { -0x1.fffffap+21, IGNORED, IGNORED, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { -0x1.fffff8p+21, IGNORED, IGNORED, IGNORED } } },
+
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { -1.00, IGNORED, IGNORED, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { -0.75, IGNORED, IGNORED, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { -0.50, IGNORED, IGNORED, IGNORED } } },
+ { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ .value2 = { .f = { -0.25, IGNORED, IGNORED, IGNORED } } }
+};
+
+static union value answers_NEAREST_INT[] = {
+ { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+
+ { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.000000p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.000000p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+
+ { .f = { 0x1.fffff8p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.000000p+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.fffffep+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+
+ { .f = { -0x1.fffffep+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.000000p+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.fffff8p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+
+ { .f = { -0x1.000000p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.000000p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+
+ { .f = { -1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } }
+};
+
+static union value answers_NEG_INF[] = {
+ { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+
+ { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+
+ { .f = { 0x1.fffff8p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.fffffep+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+
+ { .f = { -0x1.fffffep+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.000000p+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+
+ { .f = { -0x1.000000p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.000000p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.000000p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+
+ { .f = { -1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } }
+};
+
+static union value answers_POS_INF[] = {
+ { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+
+ { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.000000p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.000000p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.000000p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+
+ { .f = { 0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.000000p+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.fffffep+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+
+ { .f = { -0x1.fffffep+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.fffff8p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+
+ { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+
+ { .f = { -1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } }
+};
+
+static union value answers_ZERO[] = {
+ { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+
+ { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+
+ { .f = { 0x1.fffff8p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0x1.fffffep+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+
+ { .f = { -0x1.fffffep+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.fffff8p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+
+ { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+
+ { .f = { -1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
+ { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } }
+};
+
+union value *answers[] = {
+ answers_NEAREST_INT,
+ answers_NEG_INF,
+ answers_POS_INF,
+ answers_ZERO,
+ 0 /* CUR_DIRECTION answers depend on current rounding mode. */
+};
+
+#include "sse4_1-round3.h"
--
2.27.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/6] rs6000: Support SSE4.1 "min" and "max" intrinsics
2021-08-09 20:23 [PATCH 0/6] rs6000: Support more SSE4.1 intrinsics Paul A. Clarke
2021-08-09 20:23 ` [PATCH 1/6] rs6000: Support SSE4.1 "round" intrinsics Paul A. Clarke
@ 2021-08-09 20:23 ` Paul A. Clarke
2021-08-18 19:08 ` Bill Schmidt
2021-08-09 20:23 ` [PATCH 3/6] rs6000: Simplify some SSE4.1 "test" intrinsics Paul A. Clarke
` (3 subsequent siblings)
5 siblings, 1 reply; 17+ messages in thread
From: Paul A. Clarke @ 2021-08-09 20:23 UTC (permalink / raw)
To: gcc-patches; +Cc: segher
Also, copy tests for _mm_min_epi8, _mm_min_epu16, _mm_min_epi32,
_mm_min_epu32, _mm_max_epi8, _mm_max_epu16, _mm_max_epi32, _mm_max_epu32
from gcc/testsuite/gcc.target/i386.
sse4_1-pmaxsb.c and sse4_1-pminsb.c were modified from using
"char" types to "signed char" types, because the default is unsigned on
powerpc.
2021-08-09 Paul A. Clarke <pc@us.ibm.com>
gcc
* config/rs6000/smmintrin.h (_mm_min_epi8, _mm_min_epu16,
_mm_min_epi32, _mm_min_epu32, _mm_max_epi8, _mm_max_epu16,
_mm_max_epi32, _mm_max_epu32): New.
gcc/testsuite
* gcc.target/powerpc/sse4_1-pmaxsb.c: Copy from gcc.target/i386.
* gcc.target/powerpc/sse4_1-pmaxsd.c: Same.
* gcc.target/powerpc/sse4_1-pmaxud.c: Same.
* gcc.target/powerpc/sse4_1-pmaxuw.c: Same.
* gcc.target/powerpc/sse4_1-pminsb.c: Same.
* gcc.target/powerpc/sse4_1-pminsd.c: Same.
* gcc.target/powerpc/sse4_1-pminud.c: Same.
* gcc.target/powerpc/sse4_1-pminuw.c: Same.
---
gcc/config/rs6000/smmintrin.h | 56 +++++++++++++++++++
.../gcc.target/powerpc/sse4_1-pmaxsb.c | 46 +++++++++++++++
.../gcc.target/powerpc/sse4_1-pmaxsd.c | 46 +++++++++++++++
.../gcc.target/powerpc/sse4_1-pmaxud.c | 47 ++++++++++++++++
.../gcc.target/powerpc/sse4_1-pmaxuw.c | 47 ++++++++++++++++
.../gcc.target/powerpc/sse4_1-pminsb.c | 46 +++++++++++++++
.../gcc.target/powerpc/sse4_1-pminsd.c | 46 +++++++++++++++
.../gcc.target/powerpc/sse4_1-pminud.c | 47 ++++++++++++++++
.../gcc.target/powerpc/sse4_1-pminuw.c | 47 ++++++++++++++++
9 files changed, 428 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxsb.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxsd.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxud.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxuw.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pminsb.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pminsd.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pminud.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pminuw.c
diff --git a/gcc/config/rs6000/smmintrin.h b/gcc/config/rs6000/smmintrin.h
index 862e78ac7d60..f7f03d8d7782 100644
--- a/gcc/config/rs6000/smmintrin.h
+++ b/gcc/config/rs6000/smmintrin.h
@@ -414,6 +414,62 @@ _mm_test_mix_ones_zeros (__m128i __A, __m128i __mask)
return any_ones * any_zeros;
}
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_min_epi8 (__m128i __X, __m128i __Y)
+{
+ return (__m128i) vec_min ((__v16qi)__X, (__v16qi)__Y);
+}
+
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_min_epu16 (__m128i __X, __m128i __Y)
+{
+ return (__m128i) vec_min ((__v8hu)__X, (__v8hu)__Y);
+}
+
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_min_epi32 (__m128i __X, __m128i __Y)
+{
+ return (__m128i) vec_min ((__v4si)__X, (__v4si)__Y);
+}
+
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_min_epu32 (__m128i __X, __m128i __Y)
+{
+ return (__m128i) vec_min ((__v4su)__X, (__v4su)__Y);
+}
+
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_max_epi8 (__m128i __X, __m128i __Y)
+{
+ return (__m128i) vec_max ((__v16qi)__X, (__v16qi)__Y);
+}
+
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_max_epu16 (__m128i __X, __m128i __Y)
+{
+ return (__m128i) vec_max ((__v8hu)__X, (__v8hu)__Y);
+}
+
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_max_epi32 (__m128i __X, __m128i __Y)
+{
+ return (__m128i) vec_max ((__v4si)__X, (__v4si)__Y);
+}
+
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_max_epu32 (__m128i __X, __m128i __Y)
+{
+ return (__m128i) vec_max ((__v4su)__X, (__v4su)__Y);
+}
+
/* Return horizontal packed word minimum and its index in bits [15:0]
and bits [18:16] respectively. */
__inline __m128i
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxsb.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxsb.c
new file mode 100644
index 000000000000..24a74da309b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxsb.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 1024
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 16];
+ signed char i[NUM];
+ } dst, src1, src2;
+ int i, sign = 1;
+ signed char max;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src1.i[i] = i * i * sign;
+ src2.i[i] = (i + 20) * sign;
+ sign = -sign;
+ }
+
+ for (i = 0; i < NUM; i += 16)
+ dst.x[i / 16] = _mm_max_epi8 (src1.x[i / 16], src2.x[i / 16]);
+
+ for (i = 0; i < NUM; i++)
+ {
+ max = src1.i[i] <= src2.i[i] ? src2.i[i] : src1.i[i];
+ if (max != dst.i[i])
+ abort ();
+ }
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxsd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxsd.c
new file mode 100644
index 000000000000..87638457f883
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxsd.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 4];
+ int i[NUM];
+ } dst, src1, src2;
+ int i, sign = 1;
+ int max;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src1.i[i] = i * i * sign;
+ src2.i[i] = (i + 20) * sign;
+ sign = -sign;
+ }
+
+ for (i = 0; i < NUM; i += 4)
+ dst.x[i / 4] = _mm_max_epi32 (src1.x[i / 4], src2.x[i / 4]);
+
+ for (i = 0; i < NUM; i++)
+ {
+ max = src1.i[i] <= src2.i[i] ? src2.i[i] : src1.i[i];
+ if (max != dst.i[i])
+ abort ();
+ }
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxud.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxud.c
new file mode 100644
index 000000000000..a43728aef700
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxud.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 4];
+ unsigned int i[NUM];
+ } dst, src1, src2;
+ int i;
+ unsigned int max;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src1.i[i] = i * i;
+ src2.i[i] = i + 20;
+ if ((i % 4))
+ src2.i[i] |= 0x80000000;
+ }
+
+ for (i = 0; i < NUM; i += 4)
+ dst.x[i / 4] = _mm_max_epu32 (src1.x[i / 4], src2.x[i / 4]);
+
+ for (i = 0; i < NUM; i++)
+ {
+ max = src1.i[i] <= src2.i[i] ? src2.i[i] : src1.i[i];
+ if (max != dst.i[i])
+ abort ();
+ }
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxuw.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxuw.c
new file mode 100644
index 000000000000..2ceac84f6d8d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxuw.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 8];
+ unsigned short i[NUM];
+ } dst, src1, src2;
+ int i;
+ unsigned short max;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src1.i[i] = i * i;
+ src2.i[i] = i + 20;
+ if ((i % 8))
+ src2.i[i] |= 0x8000;
+ }
+
+ for (i = 0; i < NUM; i += 8)
+ dst.x[i / 8] = _mm_max_epu16 (src1.x[i / 8], src2.x[i / 8]);
+
+ for (i = 0; i < NUM; i++)
+ {
+ max = src1.i[i] <= src2.i[i] ? src2.i[i] : src1.i[i];
+ if (max != dst.i[i])
+ abort ();
+ }
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pminsb.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pminsb.c
new file mode 100644
index 000000000000..61aee9a8b4b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pminsb.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 1024
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 16];
+ signed char i[NUM];
+ } dst, src1, src2;
+ int i, sign = 1;
+ signed char min;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src1.i[i] = i * i * sign;
+ src2.i[i] = (i + 20) * sign;
+ sign = -sign;
+ }
+
+ for (i = 0; i < NUM; i += 16)
+ dst.x[i / 16] = _mm_min_epi8 (src1.x[i / 16], src2.x[i / 16]);
+
+ for (i = 0; i < NUM; i++)
+ {
+ min = src1.i[i] >= src2.i[i] ? src2.i[i] : src1.i[i];
+ if (min != dst.i[i])
+ abort ();
+ }
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pminsd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pminsd.c
new file mode 100644
index 000000000000..68d8a0a6c848
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pminsd.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 4];
+ int i[NUM];
+ } dst, src1, src2;
+ int i, sign = 1;
+ int min;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src1.i[i] = i * i * sign;
+ src2.i[i] = (i + 20) * sign;
+ sign = -sign;
+ }
+
+ for (i = 0; i < NUM; i += 4)
+ dst.x[i / 4] = _mm_min_epi32 (src1.x[i / 4], src2.x[i / 4]);
+
+ for (i = 0; i < NUM; i++)
+ {
+ min = src1.i[i] >= src2.i[i] ? src2.i[i] : src1.i[i];
+ if (min != dst.i[i])
+ abort ();
+ }
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pminud.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pminud.c
new file mode 100644
index 000000000000..8398e2231f29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pminud.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 4];
+ unsigned int i[NUM];
+ } dst, src1, src2;
+ int i;
+ unsigned int min;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src1.i[i] = i * i;
+ src2.i[i] = i + 20;
+ if ((i % 4))
+ src2.i[i] |= 0x80000000;
+ }
+
+ for (i = 0; i < NUM; i += 4)
+ dst.x[i / 4] = _mm_min_epu32 (src1.x[i / 4], src2.x[i / 4]);
+
+ for (i = 0; i < NUM; i++)
+ {
+ min = src1.i[i] >= src2.i[i] ? src2.i[i] : src1.i[i];
+ if (min != dst.i[i])
+ abort ();
+ }
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pminuw.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pminuw.c
new file mode 100644
index 000000000000..abbd7c07b3bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pminuw.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 8];
+ unsigned short i[NUM];
+ } dst, src1, src2;
+ int i;
+ unsigned short min;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src1.i[i] = i * i;
+ src2.i[i] = i + 20;
+ if ((i % 8))
+ src2.i[i] |= 0x8000;
+ }
+
+ for (i = 0; i < NUM; i += 8)
+ dst.x[i / 8] = _mm_min_epu16 (src1.x[i / 8], src2.x[i / 8]);
+
+ for (i = 0; i < NUM; i++)
+ {
+ min = src1.i[i] >= src2.i[i] ? src2.i[i] : src1.i[i];
+ if (min != dst.i[i])
+ abort ();
+ }
+}
--
2.27.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/6] rs6000: Simplify some SSE4.1 "test" intrinsics
2021-08-09 20:23 [PATCH 0/6] rs6000: Support more SSE4.1 intrinsics Paul A. Clarke
2021-08-09 20:23 ` [PATCH 1/6] rs6000: Support SSE4.1 "round" intrinsics Paul A. Clarke
2021-08-09 20:23 ` [PATCH 2/6] rs6000: Support SSE4.1 "min" and "max" intrinsics Paul A. Clarke
@ 2021-08-09 20:23 ` Paul A. Clarke
2021-08-18 19:10 ` Bill Schmidt
2021-08-09 20:23 ` [PATCH 4/6] rs6000: Support SSE4.1 "cvt" intrinsics Paul A. Clarke
` (2 subsequent siblings)
5 siblings, 1 reply; 17+ messages in thread
From: Paul A. Clarke @ 2021-08-09 20:23 UTC (permalink / raw)
To: gcc-patches; +Cc: segher
Copy some simple redirections from i386 <smmintrin.h>, for:
- _mm_test_all_zeros
- _mm_test_all_ones
- _mm_test_mix_ones_zeros
2021-08-09 Paul A. Clarke <pc@us.ibm.com>
gcc
* config/rs6000/smmintrin.h (_mm_test_all_zeros,
_mm_test_all_ones, _mm_test_mix_ones_zeros): Replace.
---
gcc/config/rs6000/smmintrin.h | 30 ++++--------------------------
1 file changed, 4 insertions(+), 26 deletions(-)
diff --git a/gcc/config/rs6000/smmintrin.h b/gcc/config/rs6000/smmintrin.h
index f7f03d8d7782..5d345e3fd56b 100644
--- a/gcc/config/rs6000/smmintrin.h
+++ b/gcc/config/rs6000/smmintrin.h
@@ -385,34 +385,12 @@ _mm_testnzc_si128 (__m128i __A, __m128i __B)
return _mm_testz_si128 (__A, __B) == 0 && _mm_testc_si128 (__A, __B) == 0;
}
-__inline int
-__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-_mm_test_all_zeros (__m128i __A, __m128i __mask)
-{
- const __v16qu __zero = {0};
- return vec_all_eq (vec_and ((__v16qu) __A, (__v16qu) __mask), __zero);
-}
+#define _mm_test_all_zeros(M, V) _mm_testz_si128 ((M), (V))
-__inline int
-__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-_mm_test_all_ones (__m128i __A)
-{
- const __v16qu __ones = vec_splats ((unsigned char) 0xff);
- return vec_all_eq ((__v16qu) __A, __ones);
-}
+#define _mm_test_all_ones(V) \
+ _mm_testc_si128 ((V), _mm_cmpeq_epi32 ((V), (V)))
-__inline int
-__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-_mm_test_mix_ones_zeros (__m128i __A, __m128i __mask)
-{
- const __v16qu __zero = {0};
- const __v16qu __Amasked = vec_and ((__v16qu) __A, (__v16qu) __mask);
- const int any_ones = vec_any_ne (__Amasked, __zero);
- const __v16qu __notA = vec_nor ((__v16qu) __A, (__v16qu) __A);
- const __v16qu __notAmasked = vec_and ((__v16qu) __notA, (__v16qu) __mask);
- const int any_zeros = vec_any_ne (__notAmasked, __zero);
- return any_ones * any_zeros;
-}
+#define _mm_test_mix_ones_zeros(M, V) _mm_testnzc_si128 ((M), (V))
__inline __m128i
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
--
2.27.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 4/6] rs6000: Support SSE4.1 "cvt" intrinsics
2021-08-09 20:23 [PATCH 0/6] rs6000: Support more SSE4.1 intrinsics Paul A. Clarke
` (2 preceding siblings ...)
2021-08-09 20:23 ` [PATCH 3/6] rs6000: Simplify some SSE4.1 "test" intrinsics Paul A. Clarke
@ 2021-08-09 20:23 ` Paul A. Clarke
2021-08-18 19:19 ` Bill Schmidt
2021-08-09 20:23 ` [PATCH 5/6] rs6000: Support more SSE4.1 "cmp", "mul", "pack" intrinsics Paul A. Clarke
2021-08-09 20:23 ` [PATCH 6/6] rs6000: Guard some x86 intrinsics implementations Paul A. Clarke
5 siblings, 1 reply; 17+ messages in thread
From: Paul A. Clarke @ 2021-08-09 20:23 UTC (permalink / raw)
To: gcc-patches; +Cc: segher
Also, copy tests for:
- _mm_cvtepi8_epi16, _mm_cvtepi8_epi32, _mm_cvtepi8_epi64
- _mm_cvtepi16_epi32, _mm_cvtepi16_epi64
- _mm_cvtepi32_epi64,
- _mm_cvtepu8_epi16, _mm_cvtepu8_epi32, _mm_cvtepu8_epi64
- _mm_cvtepu16_epi32, _mm_cvtepu16_epi64
- _mm_cvtepu32_epi64
from gcc/testsuite/gcc.target/i386.
sse4_1-pmovsxbd.c, sse4_1-pmovsxbq.c, and sse4_1-pmovsxbw.c were
modified from using "char" types to "signed char" types, because
the default is unsigned on powerpc.
2021-08-09 Paul A. Clarke <pc@us.ibm.com>
gcc
* config/rs6000/smmintrin.h (_mm_cvtepi8_epi16, _mm_cvtepi8_epi32,
_mm_cvtepi8_epi64, _mm_cvtepi16_epi32, _mm_cvtepi16_epi64,
_mm_cvtepi32_epi64, _mm_cvtepu8_epi16, _mm_cvtepu8_epi32,
_mm_cvtepu8_epi64, _mm_cvtepu16_epi32, _mm_cvtepu16_epi64,
_mm_cvtepu32_epi64): New.
gcc/testsuite
* gcc.target/powerpc/sse4_1-pmovsxbd.c: Copy from gcc.target/i386,
adjust dg directives to suit.
* gcc.target/powerpc/sse4_1-pmovsxbq.c: Same.
* gcc.target/powerpc/sse4_1-pmovsxbw.c: Same.
* gcc.target/powerpc/sse4_1-pmovsxdq.c: Same.
* gcc.target/powerpc/sse4_1-pmovsxwd.c: Same.
* gcc.target/powerpc/sse4_1-pmovsxwq.c: Same.
* gcc.target/powerpc/sse4_1-pmovzxbd.c: Same.
* gcc.target/powerpc/sse4_1-pmovzxbq.c: Same.
* gcc.target/powerpc/sse4_1-pmovzxbw.c: Same.
* gcc.target/powerpc/sse4_1-pmovzxdq.c: Same.
* gcc.target/powerpc/sse4_1-pmovzxwd.c: Same.
* gcc.target/powerpc/sse4_1-pmovzxwq.c: Same.
---
gcc/config/rs6000/smmintrin.h | 136 ++++++++++++++++++
.../gcc.target/powerpc/sse4_1-pmovsxbd.c | 42 ++++++
.../gcc.target/powerpc/sse4_1-pmovsxbq.c | 42 ++++++
.../gcc.target/powerpc/sse4_1-pmovsxbw.c | 42 ++++++
.../gcc.target/powerpc/sse4_1-pmovsxdq.c | 42 ++++++
.../gcc.target/powerpc/sse4_1-pmovsxwd.c | 42 ++++++
.../gcc.target/powerpc/sse4_1-pmovsxwq.c | 42 ++++++
.../gcc.target/powerpc/sse4_1-pmovzxbd.c | 43 ++++++
.../gcc.target/powerpc/sse4_1-pmovzxbq.c | 43 ++++++
.../gcc.target/powerpc/sse4_1-pmovzxbw.c | 43 ++++++
.../gcc.target/powerpc/sse4_1-pmovzxdq.c | 43 ++++++
.../gcc.target/powerpc/sse4_1-pmovzxwd.c | 43 ++++++
.../gcc.target/powerpc/sse4_1-pmovzxwq.c | 43 ++++++
13 files changed, 646 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbd.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbq.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbw.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxdq.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwd.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwq.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbd.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbq.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbw.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxdq.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxwd.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxwq.c
diff --git a/gcc/config/rs6000/smmintrin.h b/gcc/config/rs6000/smmintrin.h
index 5d345e3fd56b..7f6ff7baff50 100644
--- a/gcc/config/rs6000/smmintrin.h
+++ b/gcc/config/rs6000/smmintrin.h
@@ -448,6 +448,142 @@ _mm_max_epu32 (__m128i __X, __m128i __Y)
return (__m128i) vec_max ((__v4su)__X, (__v4su)__Y);
}
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtepi8_epi16 (__m128i __A)
+{
+ return (__m128i) vec_unpackh ((__v16qi)__A);
+}
+
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtepi8_epi32 (__m128i __A)
+{
+ __A = (__m128i) vec_unpackh ((__v16qi)__A);
+ return (__m128i) vec_unpackh ((__v8hi)__A);
+}
+
+#ifdef _ARCH_PWR8
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtepi8_epi64 (__m128i __A)
+{
+ __A = (__m128i) vec_unpackh ((__v16qi)__A);
+ __A = (__m128i) vec_unpackh ((__v8hi)__A);
+ return (__m128i) vec_unpackh ((__v4si)__A);
+}
+#endif
+
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtepi16_epi32 (__m128i __A)
+{
+ return (__m128i) vec_unpackh ((__v8hi)__A);
+}
+
+#ifdef _ARCH_PWR8
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtepi16_epi64 (__m128i __A)
+{
+ __A = (__m128i) vec_unpackh ((__v8hi)__A);
+ return (__m128i) vec_unpackh ((__v4si)__A);
+}
+
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtepi32_epi64 (__m128i __A)
+{
+ return (__m128i) vec_unpackh ((__v4si)__A);
+}
+#endif
+
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtepu8_epi16 (__m128i __A)
+{
+ const __v16qu __zero = {0};
+#ifdef __LITTLE_ENDIAN__
+ __A = (__m128i) vec_mergeh ((__v16qu)__A, __zero);
+#else /* __BIG_ENDIAN__. */
+ __A = (__m128i) vec_mergeh (__zero, (__v16qu)__A);
+#endif /* __BIG_ENDIAN__. */
+ return __A;
+}
+
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtepu8_epi32 (__m128i __A)
+{
+ const __v16qu __zero = {0};
+#ifdef __LITTLE_ENDIAN__
+ __A = (__m128i) vec_mergeh ((__v16qu)__A, __zero);
+ __A = (__m128i) vec_mergeh ((__v8hu)__A, (__v8hu)__zero);
+#else /* __BIG_ENDIAN__. */
+ __A = (__m128i) vec_mergeh (__zero, (__v16qu)__A);
+ __A = (__m128i) vec_mergeh ((__v8hu)__zero, (__v8hu)__A);
+#endif /* __BIG_ENDIAN__. */
+ return __A;
+}
+
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtepu8_epi64 (__m128i __A)
+{
+ const __v16qu __zero = {0};
+#ifdef __LITTLE_ENDIAN__
+ __A = (__m128i) vec_mergeh ((__v16qu)__A, __zero);
+ __A = (__m128i) vec_mergeh ((__v8hu)__A, (__v8hu)__zero);
+ __A = (__m128i) vec_mergeh ((__v4su)__A, (__v4su)__zero);
+#else /* __BIG_ENDIAN__. */
+ __A = (__m128i) vec_mergeh (__zero, (__v16qu)__A);
+ __A = (__m128i) vec_mergeh ((__v8hu)__zero, (__v8hu)__A);
+ __A = (__m128i) vec_mergeh ((__v4su)__zero, (__v4su)__A);
+#endif /* __BIG_ENDIAN__. */
+ return __A;
+}
+
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtepu16_epi32 (__m128i __A)
+{
+ const __v8hu __zero = {0};
+#ifdef __LITTLE_ENDIAN__
+ __A = (__m128i) vec_mergeh ((__v8hu)__A, __zero);
+#else /* __BIG_ENDIAN__. */
+ __A = (__m128i) vec_mergeh (__zero, (__v8hu)__A);
+#endif /* __BIG_ENDIAN__. */
+ return __A;
+}
+
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtepu16_epi64 (__m128i __A)
+{
+ const __v8hu __zero = {0};
+#ifdef __LITTLE_ENDIAN__
+ __A = (__m128i) vec_mergeh ((__v8hu)__A, __zero);
+ __A = (__m128i) vec_mergeh ((__v4su)__A, (__v4su)__zero);
+#else /* __BIG_ENDIAN__. */
+ __A = (__m128i) vec_mergeh (__zero, (__v8hu)__A);
+ __A = (__m128i) vec_mergeh ((__v4su)__zero, (__v4su)__A);
+#endif /* __BIG_ENDIAN__. */
+ return __A;
+}
+
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtepu32_epi64 (__m128i __A)
+{
+ const __v4su __zero = {0};
+#ifdef __LITTLE_ENDIAN__
+ __A = (__m128i) vec_mergeh ((__v4su)__A, __zero);
+#else /* __BIG_ENDIAN__. */
+ __A = (__m128i) vec_mergeh (__zero, (__v4su)__A);
+#endif /* __BIG_ENDIAN__. */
+ return __A;
+}
+
/* Return horizontal packed word minimum and its index in bits [15:0]
and bits [18:16] respectively. */
__inline __m128i
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbd.c
new file mode 100644
index 000000000000..ba8627489cfa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbd.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 4];
+ int i[NUM];
+ signed char c[NUM * 4];
+ } dst, src;
+ int i, sign = 1;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src.c[(i % 4) + (i / 4) * 16] = i * i * sign;
+ sign = -sign;
+ }
+
+ for (i = 0; i < NUM; i += 4)
+ dst.x [i / 4] = _mm_cvtepi8_epi32 (src.x [i / 4]);
+
+ for (i = 0; i < NUM; i++)
+ if (src.c[(i % 4) + (i / 4) * 16] != dst.i[i])
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbq.c
new file mode 100644
index 000000000000..57c61dddd13f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbq.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target p8vector_hw } */
+/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 2];
+ long long ll[NUM];
+ signed char c[NUM * 8];
+ } dst, src;
+ int i, sign = 1;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src.c[(i % 2) + (i / 2) * 16] = i * i * sign;
+ sign = -sign;
+ }
+
+ for (i = 0; i < NUM; i += 2)
+ dst.x [i / 2] = _mm_cvtepi8_epi64 (src.x [i / 2]);
+
+ for (i = 0; i < NUM; i++)
+ if (src.c[(i % 2) + (i / 2) * 16] != dst.ll[i])
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbw.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbw.c
new file mode 100644
index 000000000000..510b2e2ca03a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbw.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 8];
+ short s[NUM];
+ signed char c[NUM * 2];
+ } dst, src;
+ int i, sign = 1;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src.c[(i % 8) + (i / 8) * 16] = i * i * sign;
+ sign = -sign;
+ }
+
+ for (i = 0; i < NUM; i += 8)
+ dst.x [i / 8] = _mm_cvtepi8_epi16 (src.x [i / 8]);
+
+ for (i = 0; i < NUM; i++)
+ if (src.c[(i % 8) + (i / 8) * 16] != dst.s[i])
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxdq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxdq.c
new file mode 100644
index 000000000000..0126883b4368
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxdq.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target p8vector_hw } */
+/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 2];
+ long long ll[NUM];
+ int i[NUM * 2];
+ } dst, src;
+ int i, sign = 1;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src.i[(i % 2) + (i / 2) * 4] = i * i * sign;
+ sign = -sign;
+ }
+
+ for (i = 0; i < NUM; i += 2)
+ dst.x [i / 2] = _mm_cvtepi32_epi64 (src.x [i / 2]);
+
+ for (i = 0; i < NUM; i++)
+ if (src.i[(i % 2) + (i / 2) * 4] != dst.ll[i])
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwd.c
new file mode 100644
index 000000000000..8018d331be72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwd.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 4];
+ int i[NUM];
+ short s[NUM * 2];
+ } dst, src;
+ int i, sign = 1;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src.s[(i % 4) + (i / 4) * 8] = i * i * sign;
+ sign = -sign;
+ }
+
+ for (i = 0; i < NUM; i += 4)
+ dst.x [i / 4] = _mm_cvtepi16_epi32 (src.x [i / 4]);
+
+ for (i = 0; i < NUM; i++)
+ if (src.s[(i % 4) + (i / 4) * 8] != dst.i[i])
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwq.c
new file mode 100644
index 000000000000..c513b095fe55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwq.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target p8vector_hw } */
+/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 2];
+ long long ll[NUM];
+ short s[NUM * 4];
+ } dst, src;
+ int i, sign = 1;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src.s[(i % 2) + (i / 2) * 8] = i * i * sign;
+ sign = -sign;
+ }
+
+ for (i = 0; i < NUM; i += 2)
+ dst.x [i / 2] = _mm_cvtepi16_epi64 (src.x [i / 2]);
+
+ for (i = 0; i < NUM; i++)
+ if (src.s[(i % 2) + (i / 2) * 8] != dst.ll[i])
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbd.c
new file mode 100644
index 000000000000..65c42e58f8ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbd.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 4];
+ unsigned int i[NUM];
+ unsigned char c[NUM * 4];
+ } dst, src;
+ int i;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src.c[(i % 4) + (i / 4) * 16] = i * i;
+ if ((i % 4))
+ src.c[(i % 4) + (i / 4) * 16] |= 0x80;
+ }
+
+ for (i = 0; i < NUM; i += 4)
+ dst.x [i / 4] = _mm_cvtepu8_epi32 (src.x [i / 4]);
+
+ for (i = 0; i < NUM; i++)
+ if (src.c[(i % 4) + (i / 4) * 16] != dst.i[i])
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbq.c
new file mode 100644
index 000000000000..7d59300f820b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbq.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 2];
+ unsigned long long ll[NUM];
+ unsigned char c[NUM * 8];
+ } dst, src;
+ int i;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src.c[(i % 2) + (i / 2) * 16] = i * i;
+ if ((i % 2))
+ src.c[(i % 2) + (i / 2) * 16] |= 0x80;
+ }
+
+ for (i = 0; i < NUM; i += 2)
+ dst.x [i / 2] = _mm_cvtepu8_epi64 (src.x [i / 2]);
+
+ for (i = 0; i < NUM; i++)
+ if (src.c[(i % 2) + (i / 2) * 16] != dst.ll[i])
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbw.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbw.c
new file mode 100644
index 000000000000..c3963698db0b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbw.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 8];
+ unsigned short s[NUM];
+ unsigned char c[NUM * 2];
+ } dst, src;
+ int i;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src.c[(i % 8) + (i / 8) * 16] = i * i;
+ if ((i % 4))
+ src.c[(i % 8) + (i / 8) * 16] |= 0x80;
+ }
+
+ for (i = 0; i < NUM; i += 8)
+ dst.x [i / 8] = _mm_cvtepu8_epi16 (src.x [i / 8]);
+
+ for (i = 0; i < NUM; i++)
+ if (src.c[(i % 8) + (i / 8) * 16] != dst.s[i])
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxdq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxdq.c
new file mode 100644
index 000000000000..bc05089a7e1a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxdq.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 2];
+ unsigned long long ll[NUM];
+ unsigned int i[NUM * 2];
+ } dst, src;
+ int i;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src.i[(i % 2) + (i / 2) * 4] = i * i;
+ if ((i % 2))
+ src.i[(i % 2) + (i / 2) * 4] |= 0x80000000;
+ }
+
+ for (i = 0; i < NUM; i += 2)
+ dst.x [i / 2] = _mm_cvtepu32_epi64 (src.x [i / 2]);
+
+ for (i = 0; i < NUM; i++)
+ if (src.i[(i % 2) + (i / 2) * 4] != dst.ll[i])
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxwd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxwd.c
new file mode 100644
index 000000000000..a952d028e1e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxwd.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 4];
+ unsigned int i[NUM];
+ unsigned short s[NUM * 2];
+ } dst, src;
+ int i;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src.s[(i % 4) + (i / 4) * 8] = i * i;
+ if ((i % 4))
+ src.s[(i % 4) + (i / 4) * 8] |= 0x8000;
+ }
+
+ for (i = 0; i < NUM; i += 4)
+ dst.x [i / 4] = _mm_cvtepu16_epi32 (src.x [i / 4]);
+
+ for (i = 0; i < NUM; i++)
+ if (src.s[(i % 4) + (i / 4) * 8] != dst.i[i])
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxwq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxwq.c
new file mode 100644
index 000000000000..1ae5857fe0ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxwq.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 2];
+ unsigned long long ll[NUM];
+ unsigned short s[NUM * 4];
+ } dst, src;
+ int i;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src.s[(i % 2) + (i / 2) * 8] = i * i;
+ if ((i % 2))
+ src.s[(i % 2) + (i / 2) * 8] |= 0x8000;
+ }
+
+ for (i = 0; i < NUM; i += 2)
+ dst.x [i / 2] = _mm_cvtepu16_epi64 (src.x [i / 2]);
+
+ for (i = 0; i < NUM; i++)
+ if (src.s[(i % 2) + (i / 2) * 8] != dst.ll[i])
+ abort ();
+}
--
2.27.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 5/6] rs6000: Support more SSE4.1 "cmp", "mul", "pack" intrinsics
2021-08-09 20:23 [PATCH 0/6] rs6000: Support more SSE4.1 intrinsics Paul A. Clarke
` (3 preceding siblings ...)
2021-08-09 20:23 ` [PATCH 4/6] rs6000: Support SSE4.1 "cvt" intrinsics Paul A. Clarke
@ 2021-08-09 20:23 ` Paul A. Clarke
2021-08-18 19:21 ` Bill Schmidt
2021-08-09 20:23 ` [PATCH 6/6] rs6000: Guard some x86 intrinsics implementations Paul A. Clarke
5 siblings, 1 reply; 17+ messages in thread
From: Paul A. Clarke @ 2021-08-09 20:23 UTC (permalink / raw)
To: gcc-patches; +Cc: segher
Also, copy tests for:
- _mm_cmpeq_epi64, _mm_cmpgt_epi64
- _mm_mullo_epi32, _mm_mul_epi32
- _mm_packus_epi32
from gcc/testsuite/gcc.target/i386.
2021-08-09 Paul A. Clarke <pc@us.ibm.com>
gcc
* config/rs6000/smmintrin.h (_mm_cmpeq_epi64, _mm_cmpgt_epi64,
_mm_mullo_epi32, _mm_mul_epi32, _mm_packus_epi32): New.
gcc/testsuite
* gcc.target/powerpc/pr78102.c: Copy from gcc.target/i386,
adjust dg directives to suit.
* gcc.target/powerpc/sse4_1-packusdw.c: Same.
* gcc.target/powerpc/sse4_1-pcmpeqq.c: Same.
* gcc.target/powerpc/sse4_1-pmuldq.c: Same.
* gcc.target/powerpc/sse4_1-pmulld.c: Same.
* gcc.target/powerpc/sse4_2-pcmpgtq.c: Same.
---
gcc/config/rs6000/smmintrin.h | 41 +++++++++++
gcc/testsuite/gcc.target/powerpc/pr78102.c | 23 ++++++
.../gcc.target/powerpc/sse4_1-packusdw.c | 73 +++++++++++++++++++
.../gcc.target/powerpc/sse4_1-pcmpeqq.c | 46 ++++++++++++
.../gcc.target/powerpc/sse4_1-pmuldq.c | 51 +++++++++++++
.../gcc.target/powerpc/sse4_1-pmulld.c | 46 ++++++++++++
.../gcc.target/powerpc/sse4_2-pcmpgtq.c | 46 ++++++++++++
7 files changed, 326 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/powerpc/pr78102.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-packusdw.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pcmpeqq.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmuldq.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmulld.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_2-pcmpgtq.c
diff --git a/gcc/config/rs6000/smmintrin.h b/gcc/config/rs6000/smmintrin.h
index 7f6ff7baff50..8d6ae98c7ce3 100644
--- a/gcc/config/rs6000/smmintrin.h
+++ b/gcc/config/rs6000/smmintrin.h
@@ -392,6 +392,15 @@ _mm_testnzc_si128 (__m128i __A, __m128i __B)
#define _mm_test_mix_ones_zeros(M, V) _mm_testnzc_si128 ((M), (V))
+#ifdef _ARCH_PWR8
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cmpeq_epi64 (__m128i __X, __m128i __Y)
+{
+ return (__m128i) vec_cmpeq ((__v2di)__X, (__v2di)__Y);
+}
+#endif
+
__inline __m128i
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm_min_epi8 (__m128i __X, __m128i __Y)
@@ -448,6 +457,22 @@ _mm_max_epu32 (__m128i __X, __m128i __Y)
return (__m128i) vec_max ((__v4su)__X, (__v4su)__Y);
}
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mullo_epi32 (__m128i __X, __m128i __Y)
+{
+ return (__m128i) vec_mul ((__v4su)__X, (__v4su)__Y);
+}
+
+#ifdef _ARCH_PWR8
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mul_epi32 (__m128i __X, __m128i __Y)
+{
+ return (__m128i) vec_mule ((__v4si)__X, (__v4si)__Y);
+}
+#endif
+
__inline __m128i
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm_cvtepi8_epi16 (__m128i __A)
@@ -611,4 +636,20 @@ _mm_minpos_epu16 (__m128i __A)
return __r.__m;
}
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_packus_epi32 (__m128i __X, __m128i __Y)
+{
+ return (__m128i) vec_packsu ((__v4si)__X, (__v4si)__Y);
+}
+
+#ifdef _ARCH_PWR8
+__inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cmpgt_epi64 (__m128i __X, __m128i __Y)
+{
+ return (__m128i) vec_cmpgt ((__v2di)__X, (__v2di)__Y);
+}
+#endif
+
#endif
diff --git a/gcc/testsuite/gcc.target/powerpc/pr78102.c b/gcc/testsuite/gcc.target/powerpc/pr78102.c
new file mode 100644
index 000000000000..a9db140f7335
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr78102.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+#include <x86intrin.h>
+
+__m128i
+foo (const __m128i x, const __m128i y)
+{
+ return _mm_cmpeq_epi64 (x, y);
+}
+
+__v2di
+bar (const __v2di x, const __v2di y)
+{
+ return x == y;
+}
+
+__v2di
+baz (const __v2di x, const __v2di y)
+{
+ return x != y;
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-packusdw.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-packusdw.c
new file mode 100644
index 000000000000..2438a755cbe9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-packusdw.c
@@ -0,0 +1,73 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static unsigned short
+int_to_ushort (int iVal)
+{
+ unsigned short sVal;
+
+ if (iVal < 0)
+ sVal = 0;
+ else if (iVal > 0xffff)
+ sVal = 0xffff;
+ else sVal = iVal;
+
+ return sVal;
+}
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 4];
+ int i[NUM];
+ } src1, src2;
+ union
+ {
+ __m128i x[NUM / 4];
+ unsigned short s[NUM * 2];
+ } dst;
+ int i, sign = 1;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src1.i[i] = i * i * sign;
+ src2.i[i] = (i + 20) * sign;
+ sign = -sign;
+ }
+
+ for (i = 0; i < NUM; i += 4)
+ dst.x[i / 4] = _mm_packus_epi32 (src1.x [i / 4], src2.x [i / 4]);
+
+ for (i = 0; i < NUM; i ++)
+ {
+ int dstIndex;
+ unsigned short sVal;
+
+ sVal = int_to_ushort (src1.i[i]);
+ dstIndex = (i % 4) + (i / 4) * 8;
+ if (sVal != dst.s[dstIndex])
+ abort ();
+
+ sVal = int_to_ushort (src2.i[i]);
+ dstIndex += 4;
+ if (sVal != dst.s[dstIndex])
+ abort ();
+ }
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pcmpeqq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pcmpeqq.c
new file mode 100644
index 000000000000..ea3a83adf81c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pcmpeqq.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */
+/* { dg-require-effective-target p8vector_hw } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 2];
+ long long ll[NUM];
+ } dst, src1, src2;
+ int i, sign=1;
+ long long is_eq;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src1.ll[i] = i * i * sign;
+ src2.ll[i] = (i + 20) * sign;
+ sign = -sign;
+ }
+
+ for (i = 0; i < NUM; i += 2)
+ dst.x [i / 2] = _mm_cmpeq_epi64(src1.x [i / 2], src2.x [i / 2]);
+
+ for (i = 0; i < NUM; i++)
+ {
+ is_eq = src1.ll[i] == src2.ll[i] ? 0xffffffffffffffffLL : 0LL;
+ if (is_eq != dst.ll[i])
+ abort ();
+ }
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmuldq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmuldq.c
new file mode 100644
index 000000000000..f5ff27dc36c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmuldq.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */
+/* { dg-require-effective-target p8vector_hw } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 2];
+ long long ll[NUM];
+ } dst;
+ union
+ {
+ __m128i x[NUM / 2];
+ int i[NUM * 2];
+ } src1, src2;
+ int i, sign = 1;
+ long long value;
+
+ for (i = 0; i < NUM * 2; i += 2)
+ {
+ src1.i[i] = i * i * sign;
+ src2.i[i] = (i + 20) * sign;
+ sign = -sign;
+ }
+
+ for (i = 0; i < NUM; i += 2)
+ dst.x[i / 2] = _mm_mul_epi32 (src1.x[i / 2], src2.x[i / 2]);
+
+ for (i = 0; i < NUM; i++)
+ {
+ value = (long long) src1.i[i * 2] * (long long) src2.i[i * 2];
+ if (value != dst.ll[i])
+ abort ();
+ }
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmulld.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmulld.c
new file mode 100644
index 000000000000..32513edf21bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmulld.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 4];
+ int i[NUM];
+ } dst, src1, src2;
+ int i, sign = 1;
+ int value;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src1.i[i] = i * i * sign;
+ src2.i[i] = (i + 20) * sign;
+ sign = -sign;
+ }
+
+ for (i = 0; i < NUM; i += 4)
+ dst.x[i / 4] = _mm_mullo_epi32 (src1.x[i / 4], src2.x[i / 4]);
+
+ for (i = 0; i < NUM; i++)
+ {
+ value = src1.i[i] * src2.i[i];
+ if (value != dst.i[i])
+ abort ();
+ }
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_2-pcmpgtq.c b/gcc/testsuite/gcc.target/powerpc/sse4_2-pcmpgtq.c
new file mode 100644
index 000000000000..5cd88fd2ae19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_2-pcmpgtq.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mvsx -Wno-psabi" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_2_test
+#endif
+
+#include CHECK_H
+
+#include <nmmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+ union
+ {
+ __m128i x[NUM / 2];
+ long long ll[NUM];
+ } dst, src1, src2;
+ int i, sign = 1;
+ long long is_eq;
+
+ for (i = 0; i < NUM; i++)
+ {
+ src1.ll[i] = i * i * sign;
+ src2.ll[i] = (i + 20) * sign;
+ sign = -sign;
+ }
+
+ for (i = 0; i < NUM; i += 2)
+ dst.x[i / 2] = _mm_cmpgt_epi64 (src1.x[i / 2], src2.x[i / 2]);
+
+ for (i = 0; i < NUM; i++)
+ {
+ is_eq = src1.ll[i] > src2.ll[i] ? 0xFFFFFFFFFFFFFFFFLL : 0LL;
+ if (is_eq != dst.ll[i])
+ abort ();
+ }
+}
--
2.27.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 6/6] rs6000: Guard some x86 intrinsics implementations
2021-08-09 20:23 [PATCH 0/6] rs6000: Support more SSE4.1 intrinsics Paul A. Clarke
` (4 preceding siblings ...)
2021-08-09 20:23 ` [PATCH 5/6] rs6000: Support more SSE4.1 "cmp", "mul", "pack" intrinsics Paul A. Clarke
@ 2021-08-09 20:23 ` Paul A. Clarke
2021-08-18 19:27 ` Bill Schmidt
5 siblings, 1 reply; 17+ messages in thread
From: Paul A. Clarke @ 2021-08-09 20:23 UTC (permalink / raw)
To: gcc-patches; +Cc: segher
Some compatibility implementations of x86 intrinsics include
Power intrinsics which require POWER8. Guard them.
emmintrin.h:
- _mm_cmpord_pd: Remove code which was ostensibly for pre-POWER8,
but which indeed depended on POWER8 (vec_cmpgt(v2du)/vcmpgtud).
The "POWER8" version works fine on pre-POWER8.
- _mm_mul_epu32: vec_mule(v4su) uses vmuleuw.
pmmintrin.h:
- _mm_movehdup_ps: vec_mergeo(v4su) uses vmrgow.
- _mm_moveldup_ps: vec_mergee(v4su) uses vmrgew.
smmintrin.h:
- _mm_cmpeq_epi64: vec_cmpeq(v2di) uses vcmpequd.
- _mm_mul_epi32: vec_mule(v4si) uses vmuluwm.
- _mm_cmpgt_epi64: vec_cmpgt(v2di) uses vcmpgtsd.
tmmintrin.h:
- _mm_sign_epi8: vec_neg(v4si) uses vsububm.
- _mm_sign_epi16: vec_neg(v4si) uses vsubuhm.
- _mm_sign_epi32: vec_neg(v4si) uses vsubuwm.
Note that the above three could actually be supported pre-POWER8,
but current GCC does not support them before POWER8.
- _mm_sign_pi8: depends on _mm_sign_epi8.
- _mm_sign_pi16: depends on _mm_sign_epi16.
- _mm_sign_pi32: depends on _mm_sign_epi32.
2021-08-09 Paul A. Clarke <pc@us.ibm.com>
gcc
* config/rs6000/emmintrin.h: Guard POWER8 intrinsics.
* config/rs6000/pmmintrin.h: Same.
* config/rs6000/smmintrin.h: Same.
* config/rs6000/tmmintrin.h: Same.
---
gcc/config/rs6000/emmintrin.h | 12 ++----------
gcc/config/rs6000/pmmintrin.h | 2 ++
gcc/config/rs6000/smmintrin.h | 4 ++++
gcc/config/rs6000/tmmintrin.h | 2 ++
4 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/gcc/config/rs6000/emmintrin.h b/gcc/config/rs6000/emmintrin.h
index ce1287edf782..32ad72b4cc35 100644
--- a/gcc/config/rs6000/emmintrin.h
+++ b/gcc/config/rs6000/emmintrin.h
@@ -430,20 +430,10 @@ _mm_cmpnge_pd (__m128d __A, __m128d __B)
extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_cmpord_pd (__m128d __A, __m128d __B)
{
-#if _ARCH_PWR8
__v2du c, d;
/* Compare against self will return false (0's) if NAN. */
c = (__v2du)vec_cmpeq (__A, __A);
d = (__v2du)vec_cmpeq (__B, __B);
-#else
- __v2du a, b;
- __v2du c, d;
- const __v2du double_exp_mask = {0x7ff0000000000000, 0x7ff0000000000000};
- a = (__v2du)vec_abs ((__v2df)__A);
- b = (__v2du)vec_abs ((__v2df)__B);
- c = (__v2du)vec_cmpgt (double_exp_mask, a);
- d = (__v2du)vec_cmpgt (double_exp_mask, b);
-#endif
/* A != NAN and B != NAN. */
return ((__m128d)vec_and(c, d));
}
@@ -1472,6 +1462,7 @@ _mm_mul_su32 (__m64 __A, __m64 __B)
return ((__m64)a * (__m64)b);
}
+#ifdef _ARCH_PWR8
extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_mul_epu32 (__m128i __A, __m128i __B)
{
@@ -1498,6 +1489,7 @@ _mm_mul_epu32 (__m128i __A, __m128i __B)
return (__m128i) vec_mule ((__v4su)__A, (__v4su)__B);
#endif
}
+#endif
extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_slli_epi16 (__m128i __A, int __B)
diff --git a/gcc/config/rs6000/pmmintrin.h b/gcc/config/rs6000/pmmintrin.h
index eab712fdfa66..d5da1a6daa34 100644
--- a/gcc/config/rs6000/pmmintrin.h
+++ b/gcc/config/rs6000/pmmintrin.h
@@ -123,6 +123,7 @@ _mm_hsub_pd (__m128d __X, __m128d __Y)
vec_mergel ((__v2df) __X, (__v2df)__Y));
}
+#ifdef _ARCH_PWR8
extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_movehdup_ps (__m128 __X)
{
@@ -134,6 +135,7 @@ _mm_moveldup_ps (__m128 __X)
{
return (__m128)vec_mergee ((__v4su)__X, (__v4su)__X);
}
+#endif
extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_loaddup_pd (double const *__P)
diff --git a/gcc/config/rs6000/smmintrin.h b/gcc/config/rs6000/smmintrin.h
index 8d6ae98c7ce3..d2ba5f11de2e 100644
--- a/gcc/config/rs6000/smmintrin.h
+++ b/gcc/config/rs6000/smmintrin.h
@@ -278,6 +278,7 @@ _mm_extract_ps (__m128 __X, const int __N)
return ((__v4si)__X)[__N & 3];
}
+#ifdef _ARCH_PWR8
extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_blend_epi16 (__m128i __A, __m128i __B, const int __imm8)
{
@@ -289,6 +290,7 @@ _mm_blend_epi16 (__m128i __A, __m128i __B, const int __imm8)
#endif
return (__m128i) vec_sel ((__v8hu) __A, (__v8hu) __B, __shortmask);
}
+#endif
extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_blendv_epi8 (__m128i __A, __m128i __B, __m128i __mask)
@@ -349,6 +351,7 @@ _mm_blend_pd (__m128d __A, __m128d __B, const int __imm8)
return (__m128d) __r;
}
+#ifdef _ARCH_PWR8
__inline __m128d
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm_blendv_pd (__m128d __A, __m128d __B, __m128d __mask)
@@ -357,6 +360,7 @@ _mm_blendv_pd (__m128d __A, __m128d __B, __m128d __mask)
const __vector __bool long long __boolmask = vec_cmplt ((__v2di) __mask, __zero);
return (__m128d) vec_sel ((__v2du) __A, (__v2du) __B, (__v2du) __boolmask);
}
+#endif
__inline int
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
diff --git a/gcc/config/rs6000/tmmintrin.h b/gcc/config/rs6000/tmmintrin.h
index 971511260b78..4120cc1ea551 100644
--- a/gcc/config/rs6000/tmmintrin.h
+++ b/gcc/config/rs6000/tmmintrin.h
@@ -350,6 +350,7 @@ _mm_shuffle_pi8 (__m64 __A, __m64 __B)
return (__m64) ((__v2du) (__C))[0];
}
+#ifdef _ARCH_PWR8
extern __inline __m128i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_sign_epi8 (__m128i __A, __m128i __B)
@@ -418,6 +419,7 @@ _mm_sign_pi32 (__m64 __A, __m64 __B)
__C = (__v4si) _mm_sign_epi32 ((__m128i) __C, (__m128i) __D);
return (__m64) ((__v2du) (__C))[0];
}
+#endif
extern __inline __m128i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
--
2.27.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/6] rs6000: Support SSE4.1 "round" intrinsics
2021-08-09 20:23 ` [PATCH 1/6] rs6000: Support SSE4.1 "round" intrinsics Paul A. Clarke
@ 2021-08-18 19:01 ` Bill Schmidt
2021-08-18 22:22 ` Segher Boessenkool
2021-08-18 22:46 ` Segher Boessenkool
1 sibling, 1 reply; 17+ messages in thread
From: Bill Schmidt @ 2021-08-18 19:01 UTC (permalink / raw)
To: Paul A. Clarke, gcc-patches; +Cc: segher
Hi, Paul!
On 8/9/21 3:23 PM, Paul A. Clarke via Gcc-patches wrote:
> Suppress exceptions (when specified), by saving, manipulating, and
> restoring the FPSCR. Similarly, save, set, and restore the floating-point
> rounding mode when required.
>
> No attempt is made to optimize writing the FPSCR (by checking if the new
> value would be the same), other than using lighter weight instructions
> when possible.
>
> The scalar versions naively use the parallel versions to compute the
> single scalar result and then construct the remainder of the result.
>
> Of minor note, the values of _MM_FROUND_TO_NEG_INF and _MM_FROUND_TO_ZERO
> are swapped from the corresponding values on x86 so as to match the
> corresponding rounding mode values in the Power ISA.
>
> Move implementations of _mm_ceil* and _mm_floor* into _mm_round*, and
> convert _mm_ceil* and _mm_floor* into macros. This matches the current
> analogous implementations in config/i386/smmintrin.h.
>
> Add tests for _mm_round_pd, _mm_round_ps, _mm_round_sd, _mm_round_ss,
> modeled after the very similar "floor" and "ceil" tests.
>
> Include basic tests, plus tests at the boundaries for floating-point
> representation, positive and negative, test all of the parameterized
> rounding modes as well as the C99 rounding modes and interactions
> between the two.
>
> Exceptions are not explicitly tested.
Reminder: Please specify what testing you've done and on which
platforms, and where you want to apply the patches (i.e., do you want
backports?).
>
> 2021-08-09 Paul A. Clarke <pc@us.ibm.com>
>
> gcc
> * config/rs6000/smmintrin.h (_mm_round_pd, _mm_round_ps,
> _mm_round_sd, _mm_round_ss, _MM_FROUND_TO_NEAREST_INT
Missing comma
> _MM_FROUND_TO_ZERO, _MM_FROUND_TO_POS_INF, _MM_FROUND_TO_NEG_INF,
> _MM_FROUND_CUR_DIRECTION, _MM_FROUND_RAISE_EXC, _MM_FROUND_NO_EXC
Likewise
> _MM_FROUND_NINT, _MM_FROUND_FLOOR, _MM_FROUND_CEIL, _MM_FROUND_TRUNC,
> _MM_FROUND_RINT, _MM_FROUND_NEARBYINT): New.
> * config/rs6000/smmintrin.h (_mm_ceil_pd, _mm_ceil_ps, _mm_ceil_sd,
> _mm_ceil_ss, _mm_floor_pd, _mm_floor_ps, _mm_floor_sd, _mm_floor_ss):
> Convert from function to macro.
>
> gcc/testsuite
> * gcc.target/powerpc/sse4_1-round3.h: New.
> * gcc.target/powerpc/sse4_1-roundpd.c: New.
> * gcc.target/powerpc/sse4_1-roundps.c: New.
> * gcc.target/powerpc/sse4_1-roundsd.c: New.
> * gcc.target/powerpc/sse4_1-roundss.c: New.
> ---
> gcc/config/rs6000/smmintrin.h | 246 ++++++++++++-----
> .../gcc.target/powerpc/sse4_1-round3.h | 81 ++++++
> .../gcc.target/powerpc/sse4_1-roundpd.c | 143 ++++++++++
> .../gcc.target/powerpc/sse4_1-roundps.c | 98 +++++++
> .../gcc.target/powerpc/sse4_1-roundsd.c | 256 ++++++++++++++++++
> .../gcc.target/powerpc/sse4_1-roundss.c | 208 ++++++++++++++
> 6 files changed, 968 insertions(+), 64 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-round3.h
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-roundpd.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-roundps.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-roundsd.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-roundss.c
>
> diff --git a/gcc/config/rs6000/smmintrin.h b/gcc/config/rs6000/smmintrin.h
> index 3767a67eada7..862e78ac7d60 100644
> --- a/gcc/config/rs6000/smmintrin.h
> +++ b/gcc/config/rs6000/smmintrin.h
> @@ -42,6 +42,188 @@
> #include <altivec.h>
> #include <tmmintrin.h>
>
> +/* Rounding mode macros. */
> +#define _MM_FROUND_TO_NEAREST_INT 0x00
> +#define _MM_FROUND_TO_ZERO 0x01
> +#define _MM_FROUND_TO_POS_INF 0x02
> +#define _MM_FROUND_TO_NEG_INF 0x03
> +#define _MM_FROUND_CUR_DIRECTION 0x04
> +
> +#define _MM_FROUND_NINT \
> + (_MM_FROUND_TO_NEAREST_INT | _MM_FROUND_RAISE_EXC)
> +#define _MM_FROUND_FLOOR \
> + (_MM_FROUND_TO_NEG_INF | _MM_FROUND_RAISE_EXC)
> +#define _MM_FROUND_CEIL \
> + (_MM_FROUND_TO_POS_INF | _MM_FROUND_RAISE_EXC)
> +#define _MM_FROUND_TRUNC \
> + (_MM_FROUND_TO_ZERO | _MM_FROUND_RAISE_EXC)
> +#define _MM_FROUND_RINT \
> + (_MM_FROUND_CUR_DIRECTION | _MM_FROUND_RAISE_EXC)
> +#define _MM_FROUND_NEARBYINT \
> + (_MM_FROUND_CUR_DIRECTION | _MM_FROUND_NO_EXC)
> +
> +#define _MM_FROUND_RAISE_EXC 0x00
> +#define _MM_FROUND_NO_EXC 0x08
> +
> +__inline __m128d
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_round_pd (__m128d __A, int __rounding)
> +{
> + __v2df __r;
> + union {
> + double __fr;
> + long long __fpscr;
> + } __save, __tmp;
> +
> + if (__rounding & _MM_FROUND_NO_EXC)
> + {
> + /* Save enabled exceptions, and disable all exceptions.
> + Pre-POWER9, mffsce decodes to mffs, requiring the additional
> + mtfsf, below, to disable exceptions. */
> + __asm__ __volatile__ (
> + ".machine push; .machine \"power9\"; mffsce %0; .machine pop"
As we discussed, this cleverness causes trouble by introducing a
dependency on a binutils that recognizes .machine "power9". Better to
just #ifdef this and specify mffsce versus mffs.
> + : "=f" (__save.__fr));
> + __save.__fpscr &= 0xf8;
> + __tmp.__fpscr = __save.__fpscr;
> +#ifndef _ARCH_PWR9
> + __tmp.__fpscr &= ~0xf8;
Just __tmp.fpscr = 0, please, given the preceding code.
> + __builtin_mtfsf (0x01, __tmp.__fr);
> +#endif
> + }
> +
> + switch (__rounding)
> + {
> + case _MM_FROUND_TO_NEAREST_INT:
> + __tmp.__fr = __builtin_mffsl ();
Another clever encoding trick, but dangerous. __builtin_mffsl isn't
guaranteed to be recognized on P8 or earlier, even if it happens to work
today. Just use mffs and mffsl under #ifdef control.
> + __attribute__((fallthrough));
Well done. :-) A lot of people miss this.
> + case _MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC:
> + {
> + __builtin_set_fpscr_rn (0b00);
> + __r = vec_rint ((__v2df) __A);
> + __builtin_set_fpscr_rn (__tmp.__fpscr);
> + }
> + break;
> + case _MM_FROUND_TO_NEG_INF:
> + case _MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC:
> + __r = vec_floor ((__v2df) __A);
> + break;
> + case _MM_FROUND_TO_POS_INF:
> + case _MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC:
> + __r = vec_ceil ((__v2df) __A);
> + break;
> + case _MM_FROUND_TO_ZERO:
> + case _MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC:
> + __r = vec_trunc ((__v2df) __A);
> + break;
> + case _MM_FROUND_CUR_DIRECTION:
> + __r = vec_rint ((__v2df) __A);
> + break;
> + }
> + if (__rounding & _MM_FROUND_NO_EXC)
> + {
> + /* Restore enabled exceptions. */
> + __tmp.__fr = __builtin_mffsl ();
Same issue here.
> + __tmp.__fpscr |= __save.__fpscr & 0xf8;
> + __builtin_mtfsf (0x01, __tmp.__fr);
> + }
> + return (__m128d) __r;
> +}
> +
> +__inline __m128d
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_round_sd (__m128d __A, __m128d __B, int __rounding)
> +{
> + __B = _mm_round_pd (__B, __rounding);
> + __v2df __r = { ((__v2df)__B)[0], ((__v2df) __A)[1] };
> + return (__m128d) __r;
> +}
> +
> +__inline __m128
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_round_ps (__m128 __A, int __rounding)
> +{
> + __v4sf __r;
> + union {
> + double __fr;
> + long long __fpscr;
> + } __save, __tmp;
> +
> + if (__rounding & _MM_FROUND_NO_EXC)
> + {
> + /* Save enabled exceptions, and disable all exceptions.
> + Pre-POWER9, mffsce decodes to mffs, requiring the additional
> + mtfsf, below, to disable exceptions. */
> + __asm__ __volatile__ (
> + ".machine push; .machine \"power9\"; mffsce %0; .machine pop"
Same issues in this function as above, I won't repeat them all.
> + : "=f" (__save.__fr));
> + __save.__fpscr &= 0xf8;
> + __tmp.__fpscr = __save.__fpscr;
> +#ifndef _ARCH_PWR9
> + __tmp.__fpscr &= ~0xf8;
> + __builtin_mtfsf (0x01, __tmp.__fr);
> +#endif
> + }
> +
> + switch (__rounding)
> + {
> + case _MM_FROUND_TO_NEAREST_INT:
> + __tmp.__fr = __builtin_mffsl ();
> + __attribute__((fallthrough));
> + case _MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC:
> + {
> + __builtin_set_fpscr_rn (0b00);
> + __r = vec_rint ((__v4sf) __A);
> + __builtin_set_fpscr_rn (__tmp.__fpscr);
> + }
> + break;
> + case _MM_FROUND_TO_NEG_INF:
> + case _MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC:
> + __r = vec_floor ((__v4sf) __A);
> + break;
> + case _MM_FROUND_TO_POS_INF:
> + case _MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC:
> + __r = vec_ceil ((__v4sf) __A);
> + break;
> + case _MM_FROUND_TO_ZERO:
> + case _MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC:
> + __r = vec_trunc ((__v4sf) __A);
> + break;
> + case _MM_FROUND_CUR_DIRECTION:
> + __r = vec_rint ((__v4sf) __A);
> + break;
> + }
> + if (__rounding & _MM_FROUND_NO_EXC)
> + {
> + /* Restore enabled exceptions. */
> + __tmp.__fr = __builtin_mffsl ();
> + __tmp.__fpscr |= __save.__fpscr & 0xf8;
> + __builtin_mtfsf (0x01, __tmp.__fr);
> + }
> + return (__m128) __r;
> +}
> +
> +__inline __m128
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_round_ss (__m128 __A, __m128 __B, int __rounding)
> +{
> + __B = _mm_round_ps (__B, __rounding);
> + __v4sf __r = (__v4sf) __A;
> + __r[0] = ((__v4sf)__B)[0];
> + return (__m128) __r;
> +}
> +
> +#define _mm_ceil_pd(V) _mm_round_pd ((V), _MM_FROUND_CEIL)
> +#define _mm_ceil_sd(D, V) _mm_round_sd ((D), (V), _MM_FROUND_CEIL)
> +
> +#define _mm_floor_pd(V) _mm_round_pd((V), _MM_FROUND_FLOOR)
> +#define _mm_floor_sd(D, V) _mm_round_sd ((D), (V), _MM_FROUND_FLOOR)
> +
> +#define _mm_ceil_ps(V) _mm_round_ps ((V), _MM_FROUND_CEIL)
> +#define _mm_ceil_ss(D, V) _mm_round_ss ((D), (V), _MM_FROUND_CEIL)
> +
> +#define _mm_floor_ps(V) _mm_round_ps ((V), _MM_FROUND_FLOOR)
> +#define _mm_floor_ss(D, V) _mm_round_ss ((D), (V), _MM_FROUND_FLOOR)
> +
> extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
> _mm_insert_epi8 (__m128i const __A, int const __D, int const __N)
> {
> @@ -232,70 +414,6 @@ _mm_test_mix_ones_zeros (__m128i __A, __m128i __mask)
> return any_ones * any_zeros;
> }
>
> -__inline __m128d
> -__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> -_mm_ceil_pd (__m128d __A)
> -{
> - return (__m128d) vec_ceil ((__v2df) __A);
> -}
> -
> -__inline __m128d
> -__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> -_mm_ceil_sd (__m128d __A, __m128d __B)
> -{
> - __v2df __r = vec_ceil ((__v2df) __B);
> - __r[1] = ((__v2df) __A)[1];
> - return (__m128d) __r;
> -}
> -
> -__inline __m128d
> -__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> -_mm_floor_pd (__m128d __A)
> -{
> - return (__m128d) vec_floor ((__v2df) __A);
> -}
> -
> -__inline __m128d
> -__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> -_mm_floor_sd (__m128d __A, __m128d __B)
> -{
> - __v2df __r = vec_floor ((__v2df) __B);
> - __r[1] = ((__v2df) __A)[1];
> - return (__m128d) __r;
> -}
> -
> -__inline __m128
> -__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> -_mm_ceil_ps (__m128 __A)
> -{
> - return (__m128) vec_ceil ((__v4sf) __A);
> -}
> -
> -__inline __m128
> -__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> -_mm_ceil_ss (__m128 __A, __m128 __B)
> -{
> - __v4sf __r = (__v4sf) __A;
> - __r[0] = __builtin_ceil (((__v4sf) __B)[0]);
> - return __r;
> -}
> -
> -__inline __m128
> -__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> -_mm_floor_ps (__m128 __A)
> -{
> - return (__m128) vec_floor ((__v4sf) __A);
> -}
> -
> -__inline __m128
> -__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> -_mm_floor_ss (__m128 __A, __m128 __B)
> -{
> - __v4sf __r = (__v4sf) __A;
> - __r[0] = __builtin_floor (((__v4sf) __B)[0]);
> - return __r;
> -}
> -
> /* Return horizontal packed word minimum and its index in bits [15:0]
> and bits [18:16] respectively. */
> __inline __m128i
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-round3.h b/gcc/testsuite/gcc.target/powerpc/sse4_1-round3.h
> new file mode 100644
> index 000000000000..de6cbf7be438
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-round3.h
> @@ -0,0 +1,81 @@
> +#include <smmintrin.h>
> +#include <fenv.h>
> +#include "sse4_1-check.h"
> +
> +#define DIM(a) (sizeof (a) / sizeof (a)[0])
> +
> +static int roundings[] =
> + {
> + _MM_FROUND_TO_NEAREST_INT,
> + _MM_FROUND_TO_NEG_INF,
> + _MM_FROUND_TO_POS_INF,
> + _MM_FROUND_TO_ZERO,
> + _MM_FROUND_CUR_DIRECTION
> + };
> +
> +static int modes[] =
> + {
> + FE_TONEAREST,
> + FE_UPWARD,
> + FE_DOWNWARD,
> + FE_TOWARDZERO
> + };
> +
> +static void
> +TEST (void)
> +{
> + int i, j, ri, mi, round_save;
> +
> + round_save = fegetround ();
> + for (mi = 0; mi < DIM (modes); mi++) {
> + fesetround (modes[mi]);
> + for (i = 0; i < DIM (data); i++) {
> + for (ri = 0; ri < DIM (roundings); ri++) {
> + union value guess;
> + union value *current_answers = answers[ri];
> + switch ( roundings[ri] ) {
> + case _MM_FROUND_TO_NEAREST_INT:
> + guess.x = ROUND_INTRIN (data[i].value1.x, data[i].value2.x,
> + _MM_FROUND_TO_NEAREST_INT);
> + break;
> + case _MM_FROUND_TO_NEG_INF:
> + guess.x = ROUND_INTRIN (data[i].value1.x, data[i].value2.x,
> + _MM_FROUND_TO_NEG_INF);
> + break;
> + case _MM_FROUND_TO_POS_INF:
> + guess.x = ROUND_INTRIN (data[i].value1.x, data[i].value2.x,
> + _MM_FROUND_TO_POS_INF);
> + break;
> + case _MM_FROUND_TO_ZERO:
> + guess.x = ROUND_INTRIN (data[i].value1.x, data[i].value2.x,
> + _MM_FROUND_TO_ZERO);
> + break;
> + case _MM_FROUND_CUR_DIRECTION:
> + guess.x = ROUND_INTRIN (data[i].value1.x, data[i].value2.x,
> + _MM_FROUND_CUR_DIRECTION);
> + switch ( modes[mi] ) {
> + case FE_TONEAREST:
> + current_answers = answers_NEAREST_INT;
> + break;
> + case FE_UPWARD:
> + current_answers = answers_POS_INF;
> + break;
> + case FE_DOWNWARD:
> + current_answers = answers_NEG_INF;
> + break;
> + case FE_TOWARDZERO:
> + current_answers = answers_ZERO;
> + break;
> + }
> + break;
> + default:
> + abort ();
> + }
> + for (j = 0; j < DIM (guess.f); j++)
> + if (guess.f[j] != current_answers[i].f[j])
> + abort ();
> + }
> + }
> + }
> + fesetround (round_save);
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-roundpd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-roundpd.c
> new file mode 100644
> index 000000000000..42fa453b9fd3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-roundpd.c
> @@ -0,0 +1,143 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
Let's please be sure -Wno-psabi is needed. If so, please document the
warning you're avoiding. Thanks!
I won't claim I went through all the tests in gory detail, but otherwise
this patch LGTM with the indicated changes.
Thanks!
Bill
> +
> +#define NO_WARN_X86_INTRINSICS 1
> +#include <smmintrin.h>
> +
> +#define VEC_T __m128d
> +#define FP_T double
> +
> +#define ROUND_INTRIN(x, ignored, mode) _mm_round_pd (x, mode)
> +
> +#include "sse4_1-round-data.h"
> +
> +struct data2 data[] = {
> + { .value1 = { .f = { 0.00, 0.25 } } },
> + { .value1 = { .f = { 0.50, 0.75 } } },
> +
> + { .value1 = { .f = { 0x1.ffffffffffffcp+50, 0x1.ffffffffffffdp+50 } } },
> + { .value1 = { .f = { 0x1.ffffffffffffep+50, 0x1.fffffffffffffp+50 } } },
> + { .value1 = { .f = { 0x1.0000000000000p+51, 0x1.0000000000001p+51 } } },
> + { .value1 = { .f = { 0x1.0000000000002p+51, 0x1.0000000000003p+51 } } },
> +
> + { .value1 = { .f = { 0x1.ffffffffffffep+51, 0x1.fffffffffffffp+51 } } },
> + { .value1 = { .f = { 0x1.0000000000000p+52, 0x1.0000000000001p+52 } } },
> +
> + { .value1 = { .f = { -0x1.0000000000001p+52, -0x1.0000000000000p+52 } } },
> + { .value1 = { .f = { -0x1.fffffffffffffp+51, -0x1.ffffffffffffep+51 } } },
> +
> + { .value1 = { .f = { -0x1.0000000000004p+51, -0x1.0000000000002p+51 } } },
> + { .value1 = { .f = { -0x1.0000000000001p+51, -0x1.0000000000000p+51 } } },
> + { .value1 = { .f = { -0x1.ffffffffffffcp+50, -0x1.ffffffffffffep+50 } } },
> + { .value1 = { .f = { -0x1.ffffffffffffdp+50, -0x1.ffffffffffffcp+50 } } },
> +
> + { .value1 = { .f = { -1.00, -0.75 } } },
> + { .value1 = { .f = { -0.50, -0.25 } } }
> +};
> +
> +union value answers_NEAREST_INT[] = {
> + { .f = { 0.00, 0.00 } },
> + { .f = { 0.00, 1.00 } },
> +
> + { .f = { 0x1.ffffffffffffcp+50, 0x1.ffffffffffffcp+50 } },
> + { .f = { 0x1.0000000000000p+51, 0x1.0000000000000p+51 } },
> + { .f = { 0x1.0000000000000p+51, 0x1.0000000000000p+51 } },
> + { .f = { 0x1.0000000000002p+51, 0x1.0000000000004p+51 } },
> +
> + { .f = { 0x1.ffffffffffffep+51, 0x1.0000000000000p+52 } },
> + { .f = { 0x1.0000000000000p+52, 0x1.0000000000001p+52 } },
> +
> + { .f = { -0x1.0000000000001p+52, -0x1.0000000000000p+52 } },
> + { .f = { -0x1.0000000000000p+52, -0x1.ffffffffffffep+51 } },
> +
> + { .f = { -0x1.0000000000004p+51, -0x1.0000000000002p+51 } },
> + { .f = { -0x1.0000000000000p+51, -0x1.0000000000000p+51 } },
> + { .f = { -0x1.ffffffffffffcp+50, -0x1.0000000000000p+51 } },
> + { .f = { -0x1.ffffffffffffcp+50, -0x1.ffffffffffffcp+50 } },
> +
> + { .f = { -1.00, -1.00 } },
> + { .f = { 0.00, 0.00 } }
> +};
> +
> +union value answers_NEG_INF[] = {
> + { .f = { 0.00, 0.00 } },
> + { .f = { 0.00, 0.00 } },
> +
> + { .f = { 0x1.ffffffffffffcp+50, 0x1.ffffffffffffcp+50 } },
> + { .f = { 0x1.ffffffffffffcp+50, 0x1.ffffffffffffcp+50 } },
> + { .f = { 0x1.0000000000000p+51, 0x1.0000000000000p+51 } },
> + { .f = { 0x1.0000000000002p+51, 0x1.0000000000002p+51 } },
> +
> + { .f = { 0x1.ffffffffffffep+51, 0x1.ffffffffffffep+51 } },
> + { .f = { 0x1.0000000000000p+52, 0x1.0000000000001p+52 } },
> +
> + { .f = { -0x1.0000000000001p+52, -0x1.0000000000000p+52 } },
> + { .f = { -0x1.0000000000000p+52, -0x1.ffffffffffffep+51 } },
> +
> + { .f = { -0x1.0000000000004p+51, -0x1.0000000000002p+51 } },
> + { .f = { -0x1.0000000000002p+51, -0x1.0000000000000p+51 } },
> + { .f = { -0x1.ffffffffffffcp+50, -0x1.0000000000000p+51 } },
> + { .f = { -0x1.0000000000000p+51, -0x1.ffffffffffffcp+50 } },
> +
> + { .f = { -1.00, -1.00 } },
> + { .f = { -1.00, -1.00 } }
> +};
> +
> +union value answers_POS_INF[] = {
> + { .f = { 0.00, 1.00 } },
> + { .f = { 1.00, 1.00 } },
> +
> + { .f = { 0x1.ffffffffffffcp+50, 0x1.0000000000000p+51 } },
> + { .f = { 0x1.0000000000000p+51, 0x1.0000000000000p+51 } },
> + { .f = { 0x1.0000000000000p+51, 0x1.0000000000002p+51 } },
> + { .f = { 0x1.0000000000002p+51, 0x1.0000000000004p+51 } },
> +
> + { .f = { 0x1.ffffffffffffep+51, 0x1.0000000000000p+52 } },
> + { .f = { 0x1.0000000000000p+52, 0x1.0000000000001p+52 } },
> +
> + { .f = { -0x1.0000000000001p+52, -0x1.0000000000000p+52 } },
> + { .f = { -0x1.ffffffffffffep+51, -0x1.ffffffffffffep+51 } },
> +
> + { .f = { -0x1.0000000000004p+51, -0x1.0000000000002p+51 } },
> + { .f = { -0x1.0000000000000p+51, -0x1.0000000000000p+51 } },
> + { .f = { -0x1.ffffffffffffcp+50, -0x1.ffffffffffffcp+50 } },
> + { .f = { -0x1.ffffffffffffcp+50, -0x1.ffffffffffffcp+50 } },
> +
> + { .f = { -1.00, 0.00 } },
> + { .f = { 0.00, 0.00 } }
> +};
> +
> +union value answers_ZERO[] = {
> + { .f = { 0.00, 0.00 } },
> + { .f = { 0.00, 0.00 } },
> +
> + { .f = { 0x1.ffffffffffffcp+50, 0x1.ffffffffffffcp+50 } },
> + { .f = { 0x1.ffffffffffffcp+50, 0x1.ffffffffffffcp+50 } },
> + { .f = { 0x1.0000000000000p+51, 0x1.0000000000000p+51 } },
> + { .f = { 0x1.0000000000002p+51, 0x1.0000000000002p+51 } },
> +
> + { .f = { 0x1.ffffffffffffep+51, 0x1.ffffffffffffep+51 } },
> + { .f = { 0x1.0000000000000p+52, 0x1.0000000000001p+52 } },
> +
> + { .f = { -0x1.0000000000001p+52, -0x1.0000000000000p+52 } },
> + { .f = { -0x1.ffffffffffffep+51, -0x1.ffffffffffffep+51 } },
> +
> + { .f = { -0x1.0000000000004p+51, -0x1.0000000000002p+51 } },
> + { .f = { -0x1.0000000000000p+51, -0x1.0000000000000p+51 } },
> + { .f = { -0x1.ffffffffffffcp+50, -0x1.ffffffffffffcp+50 } },
> + { .f = { -0x1.ffffffffffffcp+50, -0x1.ffffffffffffcp+50 } },
> +
> + { .f = { -1.00, 0.00 } },
> + { .f = { 0.00, 0.00 } }
> +};
> +
> +union value *answers[] = {
> + answers_NEAREST_INT,
> + answers_NEG_INF,
> + answers_POS_INF,
> + answers_ZERO,
> + 0 /* CUR_DIRECTION answers depend on current rounding mode. */
> +};
> +
> +#include "sse4_1-round3.h"
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-roundps.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-roundps.c
> new file mode 100644
> index 000000000000..e36d325992db
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-roundps.c
> @@ -0,0 +1,98 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +
> +#define NO_WARN_X86_INTRINSICS 1
> +#include <smmintrin.h>
> +
> +#define VEC_T __m128
> +#define FP_T float
> +
> +#define ROUND_INTRIN(x, ignored, mode) _mm_round_ps (x, mode)
> +
> +#include "sse4_1-round-data.h"
> +
> +struct data2 data[] = {
> + { .value1 = { .f = { 0.00, 0.25, 0.50, 0.75 } } },
> +
> + { .value1 = { .f = { 0x1.fffff8p+21, 0x1.fffffap+21,
> + 0x1.fffffcp+21, 0x1.fffffep+21 } } },
> + { .value1 = { .f = { 0x1.fffffap+22, 0x1.fffffcp+22,
> + 0x1.fffffep+22, 0x1.fffffep+23 } } },
> + { .value1 = { .f = { -0x1.fffffep+23, -0x1.fffffep+22,
> + -0x1.fffffcp+22, -0x1.fffffap+22 } } },
> + { .value1 = { .f = { -0x1.fffffep+21, -0x1.fffffcp+21,
> + -0x1.fffffap+21, -0x1.fffff8p+21 } } },
> +
> + { .value1 = { .f = { -1.00, -0.75, -0.50, -0.25 } } }
> +};
> +
> +union value answers_NEAREST_INT[] = {
> + { .f = { 0.00, 0.00, 0.00, 1.00 } },
> +
> + { .f = { 0x1.fffff8p+21, 0x1.fffff8p+21,
> + 0x1.000000p+22, 0x1.000000p+22 } },
> + { .f = { 0x1.fffff8p+22, 0x1.fffffcp+22,
> + 0x1.000000p+23, 0x1.fffffep+23 } },
> + { .f = { -0x1.fffffep+23, -0x1.000000p+23,
> + -0x1.fffffcp+22, -0x1.fffff8p+22 } },
> + { .f = { -0x1.000000p+22, -0x1.000000p+22,
> + -0x1.fffff8p+21, -0x1.fffff8p+21 } },
> +
> + { .f = { -1.00, -1.00, 0.00, 0.00 } }
> +};
> +
> +union value answers_NEG_INF[] = {
> + { .f = { 0.00, 0.00, 0.00, 0.00 } },
> +
> + { .f = { 0x1.fffff8p+21, 0x1.fffff8p+21,
> + 0x1.fffff8p+21, 0x1.fffff8p+21 } },
> + { .f = { 0x1.fffff8p+22, 0x1.fffffcp+22,
> + 0x1.fffffcp+22, 0x1.fffffep+23 } },
> + { .f = { -0x1.fffffep+23, -0x1.000000p+23,
> + -0x1.fffffcp+22, -0x1.fffffcp+22 } },
> + { .f = { -0x1.000000p+22, -0x1.000000p+22,
> + -0x1.000000p+22, -0x1.fffff8p+21 } },
> +
> + { .f = { -1.00, -1.00, -1.00, -1.00 } }
> +};
> +
> +union value answers_POS_INF[] = {
> + { .f = { 0.00, 1.00, 1.00, 1.00 } },
> +
> + { .f = { 0x1.fffff8p+21, 0x1.000000p+22,
> + 0x1.000000p+22, 0x1.000000p+22 } },
> + { .f = { 0x1.fffffcp+22, 0x1.fffffcp+22,
> + 0x1.000000p+23, 0x1.fffffep+23 } },
> + { .f = { -0x1.fffffep+23, -0x1.fffffcp+22,
> + -0x1.fffffcp+22, -0x1.fffff8p+22 } },
> + { .f = { -0x1.fffff8p+21, -0x1.fffff8p+21,
> + -0x1.fffff8p+21, -0x1.fffff8p+21 } },
> +
> + { .f = { -1.00, 0.00, 0.00, 0.00 } }
> +};
> +
> +union value answers_ZERO[] = {
> + { .f = { 0.00, 0.00, 0.00, 0.00 } },
> +
> + { .f = { 0x1.fffff8p+21, 0x1.fffff8p+21,
> + 0x1.fffff8p+21, 0x1.fffff8p+21 } },
> + { .f = { 0x1.fffff8p+22, 0x1.fffffcp+22,
> + 0x1.fffffcp+22, 0x1.fffffep+23 } },
> + { .f = { -0x1.fffffep+23, -0x1.fffffcp+22,
> + -0x1.fffffcp+22, -0x1.fffff8p+22 } },
> + { .f = { -0x1.fffff8p+21, -0x1.fffff8p+21,
> + -0x1.fffff8p+21, -0x1.fffff8p+21 } },
> +
> + { .f = { -1.00, 0.00, 0.00, 0.00 } }
> +};
> +
> +union value *answers[] = {
> + answers_NEAREST_INT,
> + answers_NEG_INF,
> + answers_POS_INF,
> + answers_ZERO,
> + 0 /* CUR_DIRECTION answers depend on current rounding mode. */
> +};
> +
> +#include "sse4_1-round3.h"
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-roundsd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-roundsd.c
> new file mode 100644
> index 000000000000..00205dbd19bc
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-roundsd.c
> @@ -0,0 +1,256 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +
> +#include <stdio.h>
> +#define NO_WARN_X86_INTRINSICS 1
> +#include <smmintrin.h>
> +
> +#define VEC_T __m128d
> +#define FP_T double
> +
> +#define ROUND_INTRIN(x, y, mode) _mm_round_sd (x, y, mode)
> +
> +#include "sse4_1-round-data.h"
> +
> +static struct data2 data[] = {
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { 0.00, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { 0.25, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { 0.50, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { 0.75, IGNORED } } },
> +
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { 0x1.ffffffffffffcp+50, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { 0x1.ffffffffffffdp+50, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { 0x1.ffffffffffffep+50, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { 0x1.fffffffffffffp+50, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { 0x1.0000000000000p+51, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { 0x1.0000000000001p+51, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { 0x1.0000000000002p+51, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { 0x1.0000000000003p+51, IGNORED } } },
> +
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { 0x1.ffffffffffffep+51, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { 0x1.fffffffffffffp+51, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { 0x1.0000000000000p+52, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { 0x1.0000000000001p+52, IGNORED } } },
> +
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { -0x1.0000000000001p+52, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { -0x1.0000000000000p+52, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { -0x1.fffffffffffffp+51, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { -0x1.ffffffffffffep+51, IGNORED } } },
> +
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { -0x1.0000000000004p+51, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { -0x1.0000000000002p+51, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { -0x1.0000000000001p+51, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { -0x1.0000000000000p+51, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { -0x1.ffffffffffffcp+50, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { -0x1.ffffffffffffep+50, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { -0x1.ffffffffffffdp+50, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { -0x1.ffffffffffffcp+50, IGNORED } } },
> +
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { -1.00, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { -0.75, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { -0.50, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH } },
> + .value2 = { .f = { -0.25, IGNORED } } }
> +};
> +
> +static union value answers_NEAREST_INT[] = {
> + { .f = { 0.00, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH } },
> + { .f = { 1.00, PASSTHROUGH } },
> +
> + { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
> + { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
> + { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { 0x1.0000000000002p+51, PASSTHROUGH } },
> + { .f = { 0x1.0000000000004p+51, PASSTHROUGH } },
> +
> + { .f = { 0x1.ffffffffffffep+51, PASSTHROUGH } },
> + { .f = { 0x1.0000000000000p+52, PASSTHROUGH } },
> + { .f = { 0x1.0000000000000p+52, PASSTHROUGH } },
> + { .f = { 0x1.0000000000001p+52, PASSTHROUGH } },
> +
> + { .f = { -0x1.0000000000001p+52, PASSTHROUGH } },
> + { .f = { -0x1.0000000000000p+52, PASSTHROUGH } },
> + { .f = { -0x1.0000000000000p+52, PASSTHROUGH } },
> + { .f = { -0x1.ffffffffffffep+51, PASSTHROUGH } },
> +
> + { .f = { -0x1.0000000000004p+51, PASSTHROUGH } },
> + { .f = { -0x1.0000000000002p+51, PASSTHROUGH } },
> + { .f = { -0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { -0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
> + { .f = { -0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
> + { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
> +
> + { .f = { -1.00, PASSTHROUGH } },
> + { .f = { -1.00, PASSTHROUGH } },
> + { .f = { -0.00, PASSTHROUGH } },
> + { .f = { -0.00, PASSTHROUGH } }
> +};
> +
> +static union value answers_NEG_INF[] = {
> + { .f = { 0.00, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH } },
> +
> + { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
> + { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
> + { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
> + { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
> + { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { 0x1.0000000000002p+51, PASSTHROUGH } },
> + { .f = { 0x1.0000000000002p+51, PASSTHROUGH } },
> +
> + { .f = { 0x1.ffffffffffffep+51, PASSTHROUGH } },
> + { .f = { 0x1.ffffffffffffep+51, PASSTHROUGH } },
> + { .f = { 0x1.0000000000000p+52, PASSTHROUGH } },
> + { .f = { 0x1.0000000000001p+52, PASSTHROUGH } },
> +
> + { .f = { -0x1.0000000000001p+52, PASSTHROUGH } },
> + { .f = { -0x1.0000000000000p+52, PASSTHROUGH } },
> + { .f = { -0x1.0000000000000p+52, PASSTHROUGH } },
> + { .f = { -0x1.ffffffffffffep+51, PASSTHROUGH } },
> +
> + { .f = { -0x1.0000000000004p+51, PASSTHROUGH } },
> + { .f = { -0x1.0000000000002p+51, PASSTHROUGH } },
> + { .f = { -0x1.0000000000002p+51, PASSTHROUGH } },
> + { .f = { -0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
> + { .f = { -0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { -0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
> +
> + { .f = { -1.00, PASSTHROUGH } },
> + { .f = { -1.00, PASSTHROUGH } },
> + { .f = { -1.00, PASSTHROUGH } },
> + { .f = { -1.00, PASSTHROUGH } }
> +};
> +
> +static union value answers_POS_INF[] = {
> + { .f = { 0.00, PASSTHROUGH } },
> + { .f = { 1.00, PASSTHROUGH } },
> + { .f = { 1.00, PASSTHROUGH } },
> + { .f = { 1.00, PASSTHROUGH } },
> +
> + { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
> + { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { 0x1.0000000000002p+51, PASSTHROUGH } },
> + { .f = { 0x1.0000000000002p+51, PASSTHROUGH } },
> + { .f = { 0x1.0000000000004p+51, PASSTHROUGH } },
> +
> + { .f = { 0x1.ffffffffffffep+51, PASSTHROUGH } },
> + { .f = { 0x1.0000000000000p+52, PASSTHROUGH } },
> + { .f = { 0x1.0000000000000p+52, PASSTHROUGH } },
> + { .f = { 0x1.0000000000001p+52, PASSTHROUGH } },
> +
> + { .f = { -0x1.0000000000001p+52, PASSTHROUGH } },
> + { .f = { -0x1.0000000000000p+52, PASSTHROUGH } },
> + { .f = { -0x1.ffffffffffffep+51, PASSTHROUGH } },
> + { .f = { -0x1.ffffffffffffep+51, PASSTHROUGH } },
> +
> + { .f = { -0x1.0000000000004p+51, PASSTHROUGH } },
> + { .f = { -0x1.0000000000002p+51, PASSTHROUGH } },
> + { .f = { -0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { -0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
> + { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
> + { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
> + { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
> +
> + { .f = { -1.00, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH } }
> +};
> +
> +static union value answers_ZERO[] = {
> + { .f = { 0.00, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH } },
> +
> + { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
> + { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
> + { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
> + { .f = { 0x1.ffffffffffffcp+50, PASSTHROUGH } },
> + { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { 0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { 0x1.0000000000002p+51, PASSTHROUGH } },
> + { .f = { 0x1.0000000000002p+51, PASSTHROUGH } },
> +
> + { .f = { 0x1.ffffffffffffep+51, PASSTHROUGH } },
> + { .f = { 0x1.ffffffffffffep+51, PASSTHROUGH } },
> + { .f = { 0x1.0000000000000p+52, PASSTHROUGH } },
> + { .f = { 0x1.0000000000001p+52, PASSTHROUGH } },
> +
> + { .f = { -0x1.0000000000001p+52, PASSTHROUGH } },
> + { .f = { -0x1.0000000000000p+52, PASSTHROUGH } },
> + { .f = { -0x1.ffffffffffffep+51, PASSTHROUGH } },
> + { .f = { -0x1.ffffffffffffep+51, PASSTHROUGH } },
> +
> + { .f = { -0x1.0000000000004p+51, PASSTHROUGH } },
> + { .f = { -0x1.0000000000002p+51, PASSTHROUGH } },
> + { .f = { -0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { -0x1.0000000000000p+51, PASSTHROUGH } },
> + { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
> + { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
> + { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
> + { .f = { -0x1.ffffffffffffcp+50, PASSTHROUGH } },
> +
> + { .f = { -1.00, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH } }
> +};
> +
> +union value *answers[] = {
> + answers_NEAREST_INT,
> + answers_NEG_INF,
> + answers_POS_INF,
> + answers_ZERO,
> + 0 /* CUR_DIRECTION answers depend on current rounding mode. */
> +};
> +
> +#include "sse4_1-round3.h"
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-roundss.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-roundss.c
> new file mode 100644
> index 000000000000..b9a8eae31f2d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-roundss.c
> @@ -0,0 +1,208 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +
> +#include <stdio.h>
> +#define NO_WARN_X86_INTRINSICS 1
> +#include <smmintrin.h>
> +
> +#define VEC_T __m128
> +#define FP_T float
> +
> +#define ROUND_INTRIN(x, y, mode) _mm_round_ss (x, y, mode)
> +
> +#include "sse4_1-round-data.h"
> +
> +static struct data2 data[] = {
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { 0.00, IGNORED, IGNORED, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { 0.25, IGNORED, IGNORED, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { 0.50, IGNORED, IGNORED, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { 0.75, IGNORED, IGNORED, IGNORED } } },
> +
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { 0x1.fffff8p+21, IGNORED, IGNORED, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { 0x1.fffffap+21, IGNORED, IGNORED, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { 0x1.fffffcp+21, IGNORED, IGNORED, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { 0x1.fffffep+21, IGNORED, IGNORED, IGNORED } } },
> +
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { 0x1.fffffap+22, IGNORED, IGNORED, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { 0x1.fffffcp+22, IGNORED, IGNORED, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { 0x1.fffffep+22, IGNORED, IGNORED, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { 0x1.fffffep+23, IGNORED, IGNORED, IGNORED } } },
> +
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { -0x1.fffffep+23, IGNORED, IGNORED, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { -0x1.fffffep+22, IGNORED, IGNORED, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { -0x1.fffffcp+22, IGNORED, IGNORED, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { -0x1.fffffap+22, IGNORED, IGNORED, IGNORED } } },
> +
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { -0x1.fffffep+21, IGNORED, IGNORED, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { -0x1.fffffcp+21, IGNORED, IGNORED, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { -0x1.fffffap+21, IGNORED, IGNORED, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { -0x1.fffff8p+21, IGNORED, IGNORED, IGNORED } } },
> +
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { -1.00, IGNORED, IGNORED, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { -0.75, IGNORED, IGNORED, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { -0.50, IGNORED, IGNORED, IGNORED } } },
> + { .value1 = { .f = { IGNORED, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + .value2 = { .f = { -0.25, IGNORED, IGNORED, IGNORED } } }
> +};
> +
> +static union value answers_NEAREST_INT[] = {
> + { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> +
> + { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.000000p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.000000p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> +
> + { .f = { 0x1.fffff8p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.000000p+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.fffffep+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> +
> + { .f = { -0x1.fffffep+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.000000p+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.fffff8p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> +
> + { .f = { -0x1.000000p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.000000p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> +
> + { .f = { -1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } }
> +};
> +
> +static union value answers_NEG_INF[] = {
> + { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> +
> + { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> +
> + { .f = { 0x1.fffff8p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.fffffep+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> +
> + { .f = { -0x1.fffffep+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.000000p+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> +
> + { .f = { -0x1.000000p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.000000p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.000000p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> +
> + { .f = { -1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } }
> +};
> +
> +static union value answers_POS_INF[] = {
> + { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> +
> + { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.000000p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.000000p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.000000p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> +
> + { .f = { 0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.000000p+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.fffffep+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> +
> + { .f = { -0x1.fffffep+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.fffff8p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> +
> + { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> +
> + { .f = { -1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } }
> +};
> +
> +static union value answers_ZERO[] = {
> + { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> +
> + { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> +
> + { .f = { 0x1.fffff8p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0x1.fffffep+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> +
> + { .f = { -0x1.fffffep+23, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.fffffcp+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.fffff8p+22, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> +
> + { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { -0x1.fffff8p+21, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> +
> + { .f = { -1.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } },
> + { .f = { 0.00, PASSTHROUGH, PASSTHROUGH, PASSTHROUGH } }
> +};
> +
> +union value *answers[] = {
> + answers_NEAREST_INT,
> + answers_NEG_INF,
> + answers_POS_INF,
> + answers_ZERO,
> + 0 /* CUR_DIRECTION answers depend on current rounding mode. */
> +};
> +
> +#include "sse4_1-round3.h"
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/6] rs6000: Support SSE4.1 "min" and "max" intrinsics
2021-08-09 20:23 ` [PATCH 2/6] rs6000: Support SSE4.1 "min" and "max" intrinsics Paul A. Clarke
@ 2021-08-18 19:08 ` Bill Schmidt
0 siblings, 0 replies; 17+ messages in thread
From: Bill Schmidt @ 2021-08-18 19:08 UTC (permalink / raw)
To: Paul A. Clarke, gcc-patches; +Cc: segher
Hi Paul,
On 8/9/21 3:23 PM, Paul A. Clarke via Gcc-patches wrote:
> Also, copy tests for _mm_min_epi8, _mm_min_epu16, _mm_min_epi32,
> _mm_min_epu32, _mm_max_epi8, _mm_max_epu16, _mm_max_epi32, _mm_max_epu32
> from gcc/testsuite/gcc.target/i386.
>
> sse4_1-pmaxsb.c and sse4_1-pminsb.c were modified from using
> "char" types to "signed char" types, because the default is unsigned on
> powerpc.
Where tested, do you want backports, etc...
>
> 2021-08-09 Paul A. Clarke <pc@us.ibm.com>
>
> gcc
> * config/rs6000/smmintrin.h (_mm_min_epi8, _mm_min_epu16,
> _mm_min_epi32, _mm_min_epu32, _mm_max_epi8, _mm_max_epu16,
> _mm_max_epi32, _mm_max_epu32): New.
>
> gcc/testsuite
> * gcc.target/powerpc/sse4_1-pmaxsb.c: Copy from gcc.target/i386.
> * gcc.target/powerpc/sse4_1-pmaxsd.c: Same.
> * gcc.target/powerpc/sse4_1-pmaxud.c: Same.
> * gcc.target/powerpc/sse4_1-pmaxuw.c: Same.
> * gcc.target/powerpc/sse4_1-pminsb.c: Same.
> * gcc.target/powerpc/sse4_1-pminsd.c: Same.
> * gcc.target/powerpc/sse4_1-pminud.c: Same.
> * gcc.target/powerpc/sse4_1-pminuw.c: Same.
> ---
> gcc/config/rs6000/smmintrin.h | 56 +++++++++++++++++++
> .../gcc.target/powerpc/sse4_1-pmaxsb.c | 46 +++++++++++++++
> .../gcc.target/powerpc/sse4_1-pmaxsd.c | 46 +++++++++++++++
> .../gcc.target/powerpc/sse4_1-pmaxud.c | 47 ++++++++++++++++
> .../gcc.target/powerpc/sse4_1-pmaxuw.c | 47 ++++++++++++++++
> .../gcc.target/powerpc/sse4_1-pminsb.c | 46 +++++++++++++++
> .../gcc.target/powerpc/sse4_1-pminsd.c | 46 +++++++++++++++
> .../gcc.target/powerpc/sse4_1-pminud.c | 47 ++++++++++++++++
> .../gcc.target/powerpc/sse4_1-pminuw.c | 47 ++++++++++++++++
> 9 files changed, 428 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxsb.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxsd.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxud.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxuw.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pminsb.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pminsd.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pminud.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pminuw.c
>
> diff --git a/gcc/config/rs6000/smmintrin.h b/gcc/config/rs6000/smmintrin.h
> index 862e78ac7d60..f7f03d8d7782 100644
> --- a/gcc/config/rs6000/smmintrin.h
> +++ b/gcc/config/rs6000/smmintrin.h
> @@ -414,6 +414,62 @@ _mm_test_mix_ones_zeros (__m128i __A, __m128i __mask)
> return any_ones * any_zeros;
> }
>
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_min_epi8 (__m128i __X, __m128i __Y)
> +{
> + return (__m128i) vec_min ((__v16qi)__X, (__v16qi)__Y);
> +}
> +
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_min_epu16 (__m128i __X, __m128i __Y)
> +{
> + return (__m128i) vec_min ((__v8hu)__X, (__v8hu)__Y);
> +}
> +
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_min_epi32 (__m128i __X, __m128i __Y)
> +{
> + return (__m128i) vec_min ((__v4si)__X, (__v4si)__Y);
> +}
> +
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_min_epu32 (__m128i __X, __m128i __Y)
> +{
> + return (__m128i) vec_min ((__v4su)__X, (__v4su)__Y);
> +}
> +
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_max_epi8 (__m128i __X, __m128i __Y)
> +{
> + return (__m128i) vec_max ((__v16qi)__X, (__v16qi)__Y);
> +}
> +
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_max_epu16 (__m128i __X, __m128i __Y)
> +{
> + return (__m128i) vec_max ((__v8hu)__X, (__v8hu)__Y);
> +}
> +
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_max_epi32 (__m128i __X, __m128i __Y)
> +{
> + return (__m128i) vec_max ((__v4si)__X, (__v4si)__Y);
> +}
> +
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_max_epu32 (__m128i __X, __m128i __Y)
> +{
> + return (__m128i) vec_max ((__v4su)__X, (__v4su)__Y);
> +}
> +
I guess these are all integers, so we don't have to worry about
fast-math semantics. OK.
> /* Return horizontal packed word minimum and its index in bits [15:0]
> and bits [18:16] respectively. */
> __inline __m128i
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxsb.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxsb.c
> new file mode 100644
> index 000000000000..24a74da309b0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxsb.c
> @@ -0,0 +1,46 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
Please check/document -Wno-psabi. Otherwise the patch looks fine to
me. I won't hold you responsible for style issues in the x86 tests. :-)
Thanks!
Bill
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 1024
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 16];
> + signed char i[NUM];
> + } dst, src1, src2;
> + int i, sign = 1;
> + signed char max;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src1.i[i] = i * i * sign;
> + src2.i[i] = (i + 20) * sign;
> + sign = -sign;
> + }
> +
> + for (i = 0; i < NUM; i += 16)
> + dst.x[i / 16] = _mm_max_epi8 (src1.x[i / 16], src2.x[i / 16]);
> +
> + for (i = 0; i < NUM; i++)
> + {
> + max = src1.i[i] <= src2.i[i] ? src2.i[i] : src1.i[i];
> + if (max != dst.i[i])
> + abort ();
> + }
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxsd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxsd.c
> new file mode 100644
> index 000000000000..87638457f883
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxsd.c
> @@ -0,0 +1,46 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 64
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 4];
> + int i[NUM];
> + } dst, src1, src2;
> + int i, sign = 1;
> + int max;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src1.i[i] = i * i * sign;
> + src2.i[i] = (i + 20) * sign;
> + sign = -sign;
> + }
> +
> + for (i = 0; i < NUM; i += 4)
> + dst.x[i / 4] = _mm_max_epi32 (src1.x[i / 4], src2.x[i / 4]);
> +
> + for (i = 0; i < NUM; i++)
> + {
> + max = src1.i[i] <= src2.i[i] ? src2.i[i] : src1.i[i];
> + if (max != dst.i[i])
> + abort ();
> + }
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxud.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxud.c
> new file mode 100644
> index 000000000000..a43728aef700
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxud.c
> @@ -0,0 +1,47 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 64
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 4];
> + unsigned int i[NUM];
> + } dst, src1, src2;
> + int i;
> + unsigned int max;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src1.i[i] = i * i;
> + src2.i[i] = i + 20;
> + if ((i % 4))
> + src2.i[i] |= 0x80000000;
> + }
> +
> + for (i = 0; i < NUM; i += 4)
> + dst.x[i / 4] = _mm_max_epu32 (src1.x[i / 4], src2.x[i / 4]);
> +
> + for (i = 0; i < NUM; i++)
> + {
> + max = src1.i[i] <= src2.i[i] ? src2.i[i] : src1.i[i];
> + if (max != dst.i[i])
> + abort ();
> + }
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxuw.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxuw.c
> new file mode 100644
> index 000000000000..2ceac84f6d8d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmaxuw.c
> @@ -0,0 +1,47 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 64
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 8];
> + unsigned short i[NUM];
> + } dst, src1, src2;
> + int i;
> + unsigned short max;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src1.i[i] = i * i;
> + src2.i[i] = i + 20;
> + if ((i % 8))
> + src2.i[i] |= 0x8000;
> + }
> +
> + for (i = 0; i < NUM; i += 8)
> + dst.x[i / 8] = _mm_max_epu16 (src1.x[i / 8], src2.x[i / 8]);
> +
> + for (i = 0; i < NUM; i++)
> + {
> + max = src1.i[i] <= src2.i[i] ? src2.i[i] : src1.i[i];
> + if (max != dst.i[i])
> + abort ();
> + }
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pminsb.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pminsb.c
> new file mode 100644
> index 000000000000..61aee9a8b4b4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pminsb.c
> @@ -0,0 +1,46 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 1024
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 16];
> + signed char i[NUM];
> + } dst, src1, src2;
> + int i, sign = 1;
> + signed char min;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src1.i[i] = i * i * sign;
> + src2.i[i] = (i + 20) * sign;
> + sign = -sign;
> + }
> +
> + for (i = 0; i < NUM; i += 16)
> + dst.x[i / 16] = _mm_min_epi8 (src1.x[i / 16], src2.x[i / 16]);
> +
> + for (i = 0; i < NUM; i++)
> + {
> + min = src1.i[i] >= src2.i[i] ? src2.i[i] : src1.i[i];
> + if (min != dst.i[i])
> + abort ();
> + }
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pminsd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pminsd.c
> new file mode 100644
> index 000000000000..68d8a0a6c848
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pminsd.c
> @@ -0,0 +1,46 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 64
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 4];
> + int i[NUM];
> + } dst, src1, src2;
> + int i, sign = 1;
> + int min;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src1.i[i] = i * i * sign;
> + src2.i[i] = (i + 20) * sign;
> + sign = -sign;
> + }
> +
> + for (i = 0; i < NUM; i += 4)
> + dst.x[i / 4] = _mm_min_epi32 (src1.x[i / 4], src2.x[i / 4]);
> +
> + for (i = 0; i < NUM; i++)
> + {
> + min = src1.i[i] >= src2.i[i] ? src2.i[i] : src1.i[i];
> + if (min != dst.i[i])
> + abort ();
> + }
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pminud.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pminud.c
> new file mode 100644
> index 000000000000..8398e2231f29
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pminud.c
> @@ -0,0 +1,47 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 64
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 4];
> + unsigned int i[NUM];
> + } dst, src1, src2;
> + int i;
> + unsigned int min;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src1.i[i] = i * i;
> + src2.i[i] = i + 20;
> + if ((i % 4))
> + src2.i[i] |= 0x80000000;
> + }
> +
> + for (i = 0; i < NUM; i += 4)
> + dst.x[i / 4] = _mm_min_epu32 (src1.x[i / 4], src2.x[i / 4]);
> +
> + for (i = 0; i < NUM; i++)
> + {
> + min = src1.i[i] >= src2.i[i] ? src2.i[i] : src1.i[i];
> + if (min != dst.i[i])
> + abort ();
> + }
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pminuw.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pminuw.c
> new file mode 100644
> index 000000000000..abbd7c07b3bc
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pminuw.c
> @@ -0,0 +1,47 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 64
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 8];
> + unsigned short i[NUM];
> + } dst, src1, src2;
> + int i;
> + unsigned short min;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src1.i[i] = i * i;
> + src2.i[i] = i + 20;
> + if ((i % 8))
> + src2.i[i] |= 0x8000;
> + }
> +
> + for (i = 0; i < NUM; i += 8)
> + dst.x[i / 8] = _mm_min_epu16 (src1.x[i / 8], src2.x[i / 8]);
> +
> + for (i = 0; i < NUM; i++)
> + {
> + min = src1.i[i] >= src2.i[i] ? src2.i[i] : src1.i[i];
> + if (min != dst.i[i])
> + abort ();
> + }
> +}
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 3/6] rs6000: Simplify some SSE4.1 "test" intrinsics
2021-08-09 20:23 ` [PATCH 3/6] rs6000: Simplify some SSE4.1 "test" intrinsics Paul A. Clarke
@ 2021-08-18 19:10 ` Bill Schmidt
0 siblings, 0 replies; 17+ messages in thread
From: Bill Schmidt @ 2021-08-18 19:10 UTC (permalink / raw)
To: Paul A. Clarke, gcc-patches; +Cc: segher
Hi Paul,
On 8/9/21 3:23 PM, Paul A. Clarke via Gcc-patches wrote:
> Copy some simple redirections from i386 <smmintrin.h>, for:
> - _mm_test_all_zeros
> - _mm_test_all_ones
> - _mm_test_mix_ones_zeros
Testing, backports, etc.
Simple is good! LGTM.
Bill
>
> 2021-08-09 Paul A. Clarke <pc@us.ibm.com>
>
> gcc
> * config/rs6000/smmintrin.h (_mm_test_all_zeros,
> _mm_test_all_ones, _mm_test_mix_ones_zeros): Replace.
> ---
> gcc/config/rs6000/smmintrin.h | 30 ++++--------------------------
> 1 file changed, 4 insertions(+), 26 deletions(-)
>
> diff --git a/gcc/config/rs6000/smmintrin.h b/gcc/config/rs6000/smmintrin.h
> index f7f03d8d7782..5d345e3fd56b 100644
> --- a/gcc/config/rs6000/smmintrin.h
> +++ b/gcc/config/rs6000/smmintrin.h
> @@ -385,34 +385,12 @@ _mm_testnzc_si128 (__m128i __A, __m128i __B)
> return _mm_testz_si128 (__A, __B) == 0 && _mm_testc_si128 (__A, __B) == 0;
> }
>
> -__inline int
> -__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> -_mm_test_all_zeros (__m128i __A, __m128i __mask)
> -{
> - const __v16qu __zero = {0};
> - return vec_all_eq (vec_and ((__v16qu) __A, (__v16qu) __mask), __zero);
> -}
> +#define _mm_test_all_zeros(M, V) _mm_testz_si128 ((M), (V))
>
> -__inline int
> -__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> -_mm_test_all_ones (__m128i __A)
> -{
> - const __v16qu __ones = vec_splats ((unsigned char) 0xff);
> - return vec_all_eq ((__v16qu) __A, __ones);
> -}
> +#define _mm_test_all_ones(V) \
> + _mm_testc_si128 ((V), _mm_cmpeq_epi32 ((V), (V)))
>
> -__inline int
> -__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> -_mm_test_mix_ones_zeros (__m128i __A, __m128i __mask)
> -{
> - const __v16qu __zero = {0};
> - const __v16qu __Amasked = vec_and ((__v16qu) __A, (__v16qu) __mask);
> - const int any_ones = vec_any_ne (__Amasked, __zero);
> - const __v16qu __notA = vec_nor ((__v16qu) __A, (__v16qu) __A);
> - const __v16qu __notAmasked = vec_and ((__v16qu) __notA, (__v16qu) __mask);
> - const int any_zeros = vec_any_ne (__notAmasked, __zero);
> - return any_ones * any_zeros;
> -}
> +#define _mm_test_mix_ones_zeros(M, V) _mm_testnzc_si128 ((M), (V))
>
> __inline __m128i
> __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 4/6] rs6000: Support SSE4.1 "cvt" intrinsics
2021-08-09 20:23 ` [PATCH 4/6] rs6000: Support SSE4.1 "cvt" intrinsics Paul A. Clarke
@ 2021-08-18 19:19 ` Bill Schmidt
0 siblings, 0 replies; 17+ messages in thread
From: Bill Schmidt @ 2021-08-18 19:19 UTC (permalink / raw)
To: Paul A. Clarke, gcc-patches; +Cc: segher
Hi Paul,
On 8/9/21 3:23 PM, Paul A. Clarke via Gcc-patches wrote:
> Also, copy tests for:
> - _mm_cvtepi8_epi16, _mm_cvtepi8_epi32, _mm_cvtepi8_epi64
> - _mm_cvtepi16_epi32, _mm_cvtepi16_epi64
> - _mm_cvtepi32_epi64,
> - _mm_cvtepu8_epi16, _mm_cvtepu8_epi32, _mm_cvtepu8_epi64
> - _mm_cvtepu16_epi32, _mm_cvtepu16_epi64
> - _mm_cvtepu32_epi64
>
> from gcc/testsuite/gcc.target/i386.
>
> sse4_1-pmovsxbd.c, sse4_1-pmovsxbq.c, and sse4_1-pmovsxbw.c were
> modified from using "char" types to "signed char" types, because
> the default is unsigned on powerpc.
Testing, backports, etc.
This patch LGTM with the usual comment about documenting -Wno-psabi.
Thanks!
Bill
>
> 2021-08-09 Paul A. Clarke <pc@us.ibm.com>
>
> gcc
> * config/rs6000/smmintrin.h (_mm_cvtepi8_epi16, _mm_cvtepi8_epi32,
> _mm_cvtepi8_epi64, _mm_cvtepi16_epi32, _mm_cvtepi16_epi64,
> _mm_cvtepi32_epi64, _mm_cvtepu8_epi16, _mm_cvtepu8_epi32,
> _mm_cvtepu8_epi64, _mm_cvtepu16_epi32, _mm_cvtepu16_epi64,
> _mm_cvtepu32_epi64): New.
>
> gcc/testsuite
> * gcc.target/powerpc/sse4_1-pmovsxbd.c: Copy from gcc.target/i386,
> adjust dg directives to suit.
> * gcc.target/powerpc/sse4_1-pmovsxbq.c: Same.
> * gcc.target/powerpc/sse4_1-pmovsxbw.c: Same.
> * gcc.target/powerpc/sse4_1-pmovsxdq.c: Same.
> * gcc.target/powerpc/sse4_1-pmovsxwd.c: Same.
> * gcc.target/powerpc/sse4_1-pmovsxwq.c: Same.
> * gcc.target/powerpc/sse4_1-pmovzxbd.c: Same.
> * gcc.target/powerpc/sse4_1-pmovzxbq.c: Same.
> * gcc.target/powerpc/sse4_1-pmovzxbw.c: Same.
> * gcc.target/powerpc/sse4_1-pmovzxdq.c: Same.
> * gcc.target/powerpc/sse4_1-pmovzxwd.c: Same.
> * gcc.target/powerpc/sse4_1-pmovzxwq.c: Same.
> ---
> gcc/config/rs6000/smmintrin.h | 136 ++++++++++++++++++
> .../gcc.target/powerpc/sse4_1-pmovsxbd.c | 42 ++++++
> .../gcc.target/powerpc/sse4_1-pmovsxbq.c | 42 ++++++
> .../gcc.target/powerpc/sse4_1-pmovsxbw.c | 42 ++++++
> .../gcc.target/powerpc/sse4_1-pmovsxdq.c | 42 ++++++
> .../gcc.target/powerpc/sse4_1-pmovsxwd.c | 42 ++++++
> .../gcc.target/powerpc/sse4_1-pmovsxwq.c | 42 ++++++
> .../gcc.target/powerpc/sse4_1-pmovzxbd.c | 43 ++++++
> .../gcc.target/powerpc/sse4_1-pmovzxbq.c | 43 ++++++
> .../gcc.target/powerpc/sse4_1-pmovzxbw.c | 43 ++++++
> .../gcc.target/powerpc/sse4_1-pmovzxdq.c | 43 ++++++
> .../gcc.target/powerpc/sse4_1-pmovzxwd.c | 43 ++++++
> .../gcc.target/powerpc/sse4_1-pmovzxwq.c | 43 ++++++
> 13 files changed, 646 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbd.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbq.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbw.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxdq.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwd.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwq.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbd.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbq.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbw.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxdq.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxwd.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxwq.c
>
> diff --git a/gcc/config/rs6000/smmintrin.h b/gcc/config/rs6000/smmintrin.h
> index 5d345e3fd56b..7f6ff7baff50 100644
> --- a/gcc/config/rs6000/smmintrin.h
> +++ b/gcc/config/rs6000/smmintrin.h
> @@ -448,6 +448,142 @@ _mm_max_epu32 (__m128i __X, __m128i __Y)
> return (__m128i) vec_max ((__v4su)__X, (__v4su)__Y);
> }
>
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_cvtepi8_epi16 (__m128i __A)
> +{
> + return (__m128i) vec_unpackh ((__v16qi)__A);
> +}
> +
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_cvtepi8_epi32 (__m128i __A)
> +{
> + __A = (__m128i) vec_unpackh ((__v16qi)__A);
> + return (__m128i) vec_unpackh ((__v8hi)__A);
> +}
> +
> +#ifdef _ARCH_PWR8
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_cvtepi8_epi64 (__m128i __A)
> +{
> + __A = (__m128i) vec_unpackh ((__v16qi)__A);
> + __A = (__m128i) vec_unpackh ((__v8hi)__A);
> + return (__m128i) vec_unpackh ((__v4si)__A);
> +}
> +#endif
> +
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_cvtepi16_epi32 (__m128i __A)
> +{
> + return (__m128i) vec_unpackh ((__v8hi)__A);
> +}
> +
> +#ifdef _ARCH_PWR8
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_cvtepi16_epi64 (__m128i __A)
> +{
> + __A = (__m128i) vec_unpackh ((__v8hi)__A);
> + return (__m128i) vec_unpackh ((__v4si)__A);
> +}
> +
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_cvtepi32_epi64 (__m128i __A)
> +{
> + return (__m128i) vec_unpackh ((__v4si)__A);
> +}
> +#endif
> +
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_cvtepu8_epi16 (__m128i __A)
> +{
> + const __v16qu __zero = {0};
> +#ifdef __LITTLE_ENDIAN__
> + __A = (__m128i) vec_mergeh ((__v16qu)__A, __zero);
> +#else /* __BIG_ENDIAN__. */
> + __A = (__m128i) vec_mergeh (__zero, (__v16qu)__A);
> +#endif /* __BIG_ENDIAN__. */
> + return __A;
> +}
> +
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_cvtepu8_epi32 (__m128i __A)
> +{
> + const __v16qu __zero = {0};
> +#ifdef __LITTLE_ENDIAN__
> + __A = (__m128i) vec_mergeh ((__v16qu)__A, __zero);
> + __A = (__m128i) vec_mergeh ((__v8hu)__A, (__v8hu)__zero);
> +#else /* __BIG_ENDIAN__. */
> + __A = (__m128i) vec_mergeh (__zero, (__v16qu)__A);
> + __A = (__m128i) vec_mergeh ((__v8hu)__zero, (__v8hu)__A);
> +#endif /* __BIG_ENDIAN__. */
> + return __A;
> +}
> +
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_cvtepu8_epi64 (__m128i __A)
> +{
> + const __v16qu __zero = {0};
> +#ifdef __LITTLE_ENDIAN__
> + __A = (__m128i) vec_mergeh ((__v16qu)__A, __zero);
> + __A = (__m128i) vec_mergeh ((__v8hu)__A, (__v8hu)__zero);
> + __A = (__m128i) vec_mergeh ((__v4su)__A, (__v4su)__zero);
> +#else /* __BIG_ENDIAN__. */
> + __A = (__m128i) vec_mergeh (__zero, (__v16qu)__A);
> + __A = (__m128i) vec_mergeh ((__v8hu)__zero, (__v8hu)__A);
> + __A = (__m128i) vec_mergeh ((__v4su)__zero, (__v4su)__A);
> +#endif /* __BIG_ENDIAN__. */
> + return __A;
> +}
> +
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_cvtepu16_epi32 (__m128i __A)
> +{
> + const __v8hu __zero = {0};
> +#ifdef __LITTLE_ENDIAN__
> + __A = (__m128i) vec_mergeh ((__v8hu)__A, __zero);
> +#else /* __BIG_ENDIAN__. */
> + __A = (__m128i) vec_mergeh (__zero, (__v8hu)__A);
> +#endif /* __BIG_ENDIAN__. */
> + return __A;
> +}
> +
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_cvtepu16_epi64 (__m128i __A)
> +{
> + const __v8hu __zero = {0};
> +#ifdef __LITTLE_ENDIAN__
> + __A = (__m128i) vec_mergeh ((__v8hu)__A, __zero);
> + __A = (__m128i) vec_mergeh ((__v4su)__A, (__v4su)__zero);
> +#else /* __BIG_ENDIAN__. */
> + __A = (__m128i) vec_mergeh (__zero, (__v8hu)__A);
> + __A = (__m128i) vec_mergeh ((__v4su)__zero, (__v4su)__A);
> +#endif /* __BIG_ENDIAN__. */
> + return __A;
> +}
> +
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_cvtepu32_epi64 (__m128i __A)
> +{
> + const __v4su __zero = {0};
> +#ifdef __LITTLE_ENDIAN__
> + __A = (__m128i) vec_mergeh ((__v4su)__A, __zero);
> +#else /* __BIG_ENDIAN__. */
> + __A = (__m128i) vec_mergeh (__zero, (__v4su)__A);
> +#endif /* __BIG_ENDIAN__. */
> + return __A;
> +}
> +
> /* Return horizontal packed word minimum and its index in bits [15:0]
> and bits [18:16] respectively. */
> __inline __m128i
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbd.c
> new file mode 100644
> index 000000000000..ba8627489cfa
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbd.c
> @@ -0,0 +1,42 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 128
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 4];
> + int i[NUM];
> + signed char c[NUM * 4];
> + } dst, src;
> + int i, sign = 1;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src.c[(i % 4) + (i / 4) * 16] = i * i * sign;
> + sign = -sign;
> + }
> +
> + for (i = 0; i < NUM; i += 4)
> + dst.x [i / 4] = _mm_cvtepi8_epi32 (src.x [i / 4]);
> +
> + for (i = 0; i < NUM; i++)
> + if (src.c[(i % 4) + (i / 4) * 16] != dst.i[i])
> + abort ();
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbq.c
> new file mode 100644
> index 000000000000..57c61dddd13f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbq.c
> @@ -0,0 +1,42 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target p8vector_hw } */
> +/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 128
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 2];
> + long long ll[NUM];
> + signed char c[NUM * 8];
> + } dst, src;
> + int i, sign = 1;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src.c[(i % 2) + (i / 2) * 16] = i * i * sign;
> + sign = -sign;
> + }
> +
> + for (i = 0; i < NUM; i += 2)
> + dst.x [i / 2] = _mm_cvtepi8_epi64 (src.x [i / 2]);
> +
> + for (i = 0; i < NUM; i++)
> + if (src.c[(i % 2) + (i / 2) * 16] != dst.ll[i])
> + abort ();
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbw.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbw.c
> new file mode 100644
> index 000000000000..510b2e2ca03a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbw.c
> @@ -0,0 +1,42 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 128
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 8];
> + short s[NUM];
> + signed char c[NUM * 2];
> + } dst, src;
> + int i, sign = 1;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src.c[(i % 8) + (i / 8) * 16] = i * i * sign;
> + sign = -sign;
> + }
> +
> + for (i = 0; i < NUM; i += 8)
> + dst.x [i / 8] = _mm_cvtepi8_epi16 (src.x [i / 8]);
> +
> + for (i = 0; i < NUM; i++)
> + if (src.c[(i % 8) + (i / 8) * 16] != dst.s[i])
> + abort ();
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxdq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxdq.c
> new file mode 100644
> index 000000000000..0126883b4368
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxdq.c
> @@ -0,0 +1,42 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target p8vector_hw } */
> +/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 128
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 2];
> + long long ll[NUM];
> + int i[NUM * 2];
> + } dst, src;
> + int i, sign = 1;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src.i[(i % 2) + (i / 2) * 4] = i * i * sign;
> + sign = -sign;
> + }
> +
> + for (i = 0; i < NUM; i += 2)
> + dst.x [i / 2] = _mm_cvtepi32_epi64 (src.x [i / 2]);
> +
> + for (i = 0; i < NUM; i++)
> + if (src.i[(i % 2) + (i / 2) * 4] != dst.ll[i])
> + abort ();
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwd.c
> new file mode 100644
> index 000000000000..8018d331be72
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwd.c
> @@ -0,0 +1,42 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 128
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 4];
> + int i[NUM];
> + short s[NUM * 2];
> + } dst, src;
> + int i, sign = 1;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src.s[(i % 4) + (i / 4) * 8] = i * i * sign;
> + sign = -sign;
> + }
> +
> + for (i = 0; i < NUM; i += 4)
> + dst.x [i / 4] = _mm_cvtepi16_epi32 (src.x [i / 4]);
> +
> + for (i = 0; i < NUM; i++)
> + if (src.s[(i % 4) + (i / 4) * 8] != dst.i[i])
> + abort ();
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwq.c
> new file mode 100644
> index 000000000000..c513b095fe55
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwq.c
> @@ -0,0 +1,42 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target p8vector_hw } */
> +/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 128
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 2];
> + long long ll[NUM];
> + short s[NUM * 4];
> + } dst, src;
> + int i, sign = 1;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src.s[(i % 2) + (i / 2) * 8] = i * i * sign;
> + sign = -sign;
> + }
> +
> + for (i = 0; i < NUM; i += 2)
> + dst.x [i / 2] = _mm_cvtepi16_epi64 (src.x [i / 2]);
> +
> + for (i = 0; i < NUM; i++)
> + if (src.s[(i % 2) + (i / 2) * 8] != dst.ll[i])
> + abort ();
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbd.c
> new file mode 100644
> index 000000000000..65c42e58f8ef
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbd.c
> @@ -0,0 +1,43 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 128
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 4];
> + unsigned int i[NUM];
> + unsigned char c[NUM * 4];
> + } dst, src;
> + int i;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src.c[(i % 4) + (i / 4) * 16] = i * i;
> + if ((i % 4))
> + src.c[(i % 4) + (i / 4) * 16] |= 0x80;
> + }
> +
> + for (i = 0; i < NUM; i += 4)
> + dst.x [i / 4] = _mm_cvtepu8_epi32 (src.x [i / 4]);
> +
> + for (i = 0; i < NUM; i++)
> + if (src.c[(i % 4) + (i / 4) * 16] != dst.i[i])
> + abort ();
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbq.c
> new file mode 100644
> index 000000000000..7d59300f820b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbq.c
> @@ -0,0 +1,43 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 128
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 2];
> + unsigned long long ll[NUM];
> + unsigned char c[NUM * 8];
> + } dst, src;
> + int i;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src.c[(i % 2) + (i / 2) * 16] = i * i;
> + if ((i % 2))
> + src.c[(i % 2) + (i / 2) * 16] |= 0x80;
> + }
> +
> + for (i = 0; i < NUM; i += 2)
> + dst.x [i / 2] = _mm_cvtepu8_epi64 (src.x [i / 2]);
> +
> + for (i = 0; i < NUM; i++)
> + if (src.c[(i % 2) + (i / 2) * 16] != dst.ll[i])
> + abort ();
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbw.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbw.c
> new file mode 100644
> index 000000000000..c3963698db0b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxbw.c
> @@ -0,0 +1,43 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 128
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 8];
> + unsigned short s[NUM];
> + unsigned char c[NUM * 2];
> + } dst, src;
> + int i;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src.c[(i % 8) + (i / 8) * 16] = i * i;
> + if ((i % 4))
> + src.c[(i % 8) + (i / 8) * 16] |= 0x80;
> + }
> +
> + for (i = 0; i < NUM; i += 8)
> + dst.x [i / 8] = _mm_cvtepu8_epi16 (src.x [i / 8]);
> +
> + for (i = 0; i < NUM; i++)
> + if (src.c[(i % 8) + (i / 8) * 16] != dst.s[i])
> + abort ();
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxdq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxdq.c
> new file mode 100644
> index 000000000000..bc05089a7e1a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxdq.c
> @@ -0,0 +1,43 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 128
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 2];
> + unsigned long long ll[NUM];
> + unsigned int i[NUM * 2];
> + } dst, src;
> + int i;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src.i[(i % 2) + (i / 2) * 4] = i * i;
> + if ((i % 2))
> + src.i[(i % 2) + (i / 2) * 4] |= 0x80000000;
> + }
> +
> + for (i = 0; i < NUM; i += 2)
> + dst.x [i / 2] = _mm_cvtepu32_epi64 (src.x [i / 2]);
> +
> + for (i = 0; i < NUM; i++)
> + if (src.i[(i % 2) + (i / 2) * 4] != dst.ll[i])
> + abort ();
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxwd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxwd.c
> new file mode 100644
> index 000000000000..a952d028e1e0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxwd.c
> @@ -0,0 +1,43 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 128
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 4];
> + unsigned int i[NUM];
> + unsigned short s[NUM * 2];
> + } dst, src;
> + int i;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src.s[(i % 4) + (i / 4) * 8] = i * i;
> + if ((i % 4))
> + src.s[(i % 4) + (i / 4) * 8] |= 0x8000;
> + }
> +
> + for (i = 0; i < NUM; i += 4)
> + dst.x [i / 4] = _mm_cvtepu16_epi32 (src.x [i / 4]);
> +
> + for (i = 0; i < NUM; i++)
> + if (src.s[(i % 4) + (i / 4) * 8] != dst.i[i])
> + abort ();
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxwq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxwq.c
> new file mode 100644
> index 000000000000..1ae5857fe0ad
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovzxwq.c
> @@ -0,0 +1,43 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 128
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 2];
> + unsigned long long ll[NUM];
> + unsigned short s[NUM * 4];
> + } dst, src;
> + int i;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src.s[(i % 2) + (i / 2) * 8] = i * i;
> + if ((i % 2))
> + src.s[(i % 2) + (i / 2) * 8] |= 0x8000;
> + }
> +
> + for (i = 0; i < NUM; i += 2)
> + dst.x [i / 2] = _mm_cvtepu16_epi64 (src.x [i / 2]);
> +
> + for (i = 0; i < NUM; i++)
> + if (src.s[(i % 2) + (i / 2) * 8] != dst.ll[i])
> + abort ();
> +}
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 5/6] rs6000: Support more SSE4.1 "cmp", "mul", "pack" intrinsics
2021-08-09 20:23 ` [PATCH 5/6] rs6000: Support more SSE4.1 "cmp", "mul", "pack" intrinsics Paul A. Clarke
@ 2021-08-18 19:21 ` Bill Schmidt
0 siblings, 0 replies; 17+ messages in thread
From: Bill Schmidt @ 2021-08-18 19:21 UTC (permalink / raw)
To: Paul A. Clarke, gcc-patches; +Cc: segher
Hi Paul,
On 8/9/21 3:23 PM, Paul A. Clarke via Gcc-patches wrote:
> Also, copy tests for:
> - _mm_cmpeq_epi64, _mm_cmpgt_epi64
> - _mm_mullo_epi32, _mm_mul_epi32
> - _mm_packus_epi32
>
> from gcc/testsuite/gcc.target/i386.
Testing, backports, etc.
This patch LGTM with the usual comment about documenting -Wno-psabi.
Thanks!
Bill
>
> 2021-08-09 Paul A. Clarke <pc@us.ibm.com>
>
> gcc
> * config/rs6000/smmintrin.h (_mm_cmpeq_epi64, _mm_cmpgt_epi64,
> _mm_mullo_epi32, _mm_mul_epi32, _mm_packus_epi32): New.
>
> gcc/testsuite
> * gcc.target/powerpc/pr78102.c: Copy from gcc.target/i386,
> adjust dg directives to suit.
> * gcc.target/powerpc/sse4_1-packusdw.c: Same.
> * gcc.target/powerpc/sse4_1-pcmpeqq.c: Same.
> * gcc.target/powerpc/sse4_1-pmuldq.c: Same.
> * gcc.target/powerpc/sse4_1-pmulld.c: Same.
> * gcc.target/powerpc/sse4_2-pcmpgtq.c: Same.
> ---
> gcc/config/rs6000/smmintrin.h | 41 +++++++++++
> gcc/testsuite/gcc.target/powerpc/pr78102.c | 23 ++++++
> .../gcc.target/powerpc/sse4_1-packusdw.c | 73 +++++++++++++++++++
> .../gcc.target/powerpc/sse4_1-pcmpeqq.c | 46 ++++++++++++
> .../gcc.target/powerpc/sse4_1-pmuldq.c | 51 +++++++++++++
> .../gcc.target/powerpc/sse4_1-pmulld.c | 46 ++++++++++++
> .../gcc.target/powerpc/sse4_2-pcmpgtq.c | 46 ++++++++++++
> 7 files changed, 326 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/powerpc/pr78102.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-packusdw.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pcmpeqq.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmuldq.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pmulld.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_2-pcmpgtq.c
>
> diff --git a/gcc/config/rs6000/smmintrin.h b/gcc/config/rs6000/smmintrin.h
> index 7f6ff7baff50..8d6ae98c7ce3 100644
> --- a/gcc/config/rs6000/smmintrin.h
> +++ b/gcc/config/rs6000/smmintrin.h
> @@ -392,6 +392,15 @@ _mm_testnzc_si128 (__m128i __A, __m128i __B)
>
> #define _mm_test_mix_ones_zeros(M, V) _mm_testnzc_si128 ((M), (V))
>
> +#ifdef _ARCH_PWR8
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_cmpeq_epi64 (__m128i __X, __m128i __Y)
> +{
> + return (__m128i) vec_cmpeq ((__v2di)__X, (__v2di)__Y);
> +}
> +#endif
> +
> __inline __m128i
> __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> _mm_min_epi8 (__m128i __X, __m128i __Y)
> @@ -448,6 +457,22 @@ _mm_max_epu32 (__m128i __X, __m128i __Y)
> return (__m128i) vec_max ((__v4su)__X, (__v4su)__Y);
> }
>
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_mullo_epi32 (__m128i __X, __m128i __Y)
> +{
> + return (__m128i) vec_mul ((__v4su)__X, (__v4su)__Y);
> +}
> +
> +#ifdef _ARCH_PWR8
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_mul_epi32 (__m128i __X, __m128i __Y)
> +{
> + return (__m128i) vec_mule ((__v4si)__X, (__v4si)__Y);
> +}
> +#endif
> +
> __inline __m128i
> __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> _mm_cvtepi8_epi16 (__m128i __A)
> @@ -611,4 +636,20 @@ _mm_minpos_epu16 (__m128i __A)
> return __r.__m;
> }
>
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_packus_epi32 (__m128i __X, __m128i __Y)
> +{
> + return (__m128i) vec_packsu ((__v4si)__X, (__v4si)__Y);
> +}
> +
> +#ifdef _ARCH_PWR8
> +__inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_cmpgt_epi64 (__m128i __X, __m128i __Y)
> +{
> + return (__m128i) vec_cmpgt ((__v2di)__X, (__v2di)__Y);
> +}
> +#endif
> +
> #endif
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr78102.c b/gcc/testsuite/gcc.target/powerpc/pr78102.c
> new file mode 100644
> index 000000000000..a9db140f7335
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr78102.c
> @@ -0,0 +1,23 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +
> +#include <x86intrin.h>
> +
> +__m128i
> +foo (const __m128i x, const __m128i y)
> +{
> + return _mm_cmpeq_epi64 (x, y);
> +}
> +
> +__v2di
> +bar (const __v2di x, const __v2di y)
> +{
> + return x == y;
> +}
> +
> +__v2di
> +baz (const __v2di x, const __v2di y)
> +{
> + return x != y;
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-packusdw.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-packusdw.c
> new file mode 100644
> index 000000000000..2438a755cbe9
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-packusdw.c
> @@ -0,0 +1,73 @@
> +/* { dg-do run } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 64
> +
> +static unsigned short
> +int_to_ushort (int iVal)
> +{
> + unsigned short sVal;
> +
> + if (iVal < 0)
> + sVal = 0;
> + else if (iVal > 0xffff)
> + sVal = 0xffff;
> + else sVal = iVal;
> +
> + return sVal;
> +}
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 4];
> + int i[NUM];
> + } src1, src2;
> + union
> + {
> + __m128i x[NUM / 4];
> + unsigned short s[NUM * 2];
> + } dst;
> + int i, sign = 1;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src1.i[i] = i * i * sign;
> + src2.i[i] = (i + 20) * sign;
> + sign = -sign;
> + }
> +
> + for (i = 0; i < NUM; i += 4)
> + dst.x[i / 4] = _mm_packus_epi32 (src1.x [i / 4], src2.x [i / 4]);
> +
> + for (i = 0; i < NUM; i ++)
> + {
> + int dstIndex;
> + unsigned short sVal;
> +
> + sVal = int_to_ushort (src1.i[i]);
> + dstIndex = (i % 4) + (i / 4) * 8;
> + if (sVal != dst.s[dstIndex])
> + abort ();
> +
> + sVal = int_to_ushort (src2.i[i]);
> + dstIndex += 4;
> + if (sVal != dst.s[dstIndex])
> + abort ();
> + }
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pcmpeqq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pcmpeqq.c
> new file mode 100644
> index 000000000000..ea3a83adf81c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pcmpeqq.c
> @@ -0,0 +1,46 @@
> +/* { dg-do run } */
> +/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */
> +/* { dg-require-effective-target p8vector_hw } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 64
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 2];
> + long long ll[NUM];
> + } dst, src1, src2;
> + int i, sign=1;
> + long long is_eq;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src1.ll[i] = i * i * sign;
> + src2.ll[i] = (i + 20) * sign;
> + sign = -sign;
> + }
> +
> + for (i = 0; i < NUM; i += 2)
> + dst.x [i / 2] = _mm_cmpeq_epi64(src1.x [i / 2], src2.x [i / 2]);
> +
> + for (i = 0; i < NUM; i++)
> + {
> + is_eq = src1.ll[i] == src2.ll[i] ? 0xffffffffffffffffLL : 0LL;
> + if (is_eq != dst.ll[i])
> + abort ();
> + }
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmuldq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmuldq.c
> new file mode 100644
> index 000000000000..f5ff27dc36c3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmuldq.c
> @@ -0,0 +1,51 @@
> +/* { dg-do run } */
> +/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */
> +/* { dg-require-effective-target p8vector_hw } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 64
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 2];
> + long long ll[NUM];
> + } dst;
> + union
> + {
> + __m128i x[NUM / 2];
> + int i[NUM * 2];
> + } src1, src2;
> + int i, sign = 1;
> + long long value;
> +
> + for (i = 0; i < NUM * 2; i += 2)
> + {
> + src1.i[i] = i * i * sign;
> + src2.i[i] = (i + 20) * sign;
> + sign = -sign;
> + }
> +
> + for (i = 0; i < NUM; i += 2)
> + dst.x[i / 2] = _mm_mul_epi32 (src1.x[i / 2], src2.x[i / 2]);
> +
> + for (i = 0; i < NUM; i++)
> + {
> + value = (long long) src1.i[i * 2] * (long long) src2.i[i * 2];
> + if (value != dst.ll[i])
> + abort ();
> + }
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmulld.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmulld.c
> new file mode 100644
> index 000000000000..32513edf21bf
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmulld.c
> @@ -0,0 +1,46 @@
> +/* { dg-do run } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_1-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_1_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <smmintrin.h>
> +
> +#define NUM 64
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 4];
> + int i[NUM];
> + } dst, src1, src2;
> + int i, sign = 1;
> + int value;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src1.i[i] = i * i * sign;
> + src2.i[i] = (i + 20) * sign;
> + sign = -sign;
> + }
> +
> + for (i = 0; i < NUM; i += 4)
> + dst.x[i / 4] = _mm_mullo_epi32 (src1.x[i / 4], src2.x[i / 4]);
> +
> + for (i = 0; i < NUM; i++)
> + {
> + value = src1.i[i] * src2.i[i];
> + if (value != dst.i[i])
> + abort ();
> + }
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_2-pcmpgtq.c b/gcc/testsuite/gcc.target/powerpc/sse4_2-pcmpgtq.c
> new file mode 100644
> index 000000000000..5cd88fd2ae19
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/sse4_2-pcmpgtq.c
> @@ -0,0 +1,46 @@
> +/* { dg-do run } */
> +/* { dg-options "-O2 -mvsx -Wno-psabi" } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +
> +#ifndef CHECK_H
> +#define CHECK_H "sse4_2-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST sse4_2_test
> +#endif
> +
> +#include CHECK_H
> +
> +#include <nmmintrin.h>
> +
> +#define NUM 64
> +
> +static void
> +TEST (void)
> +{
> + union
> + {
> + __m128i x[NUM / 2];
> + long long ll[NUM];
> + } dst, src1, src2;
> + int i, sign = 1;
> + long long is_eq;
> +
> + for (i = 0; i < NUM; i++)
> + {
> + src1.ll[i] = i * i * sign;
> + src2.ll[i] = (i + 20) * sign;
> + sign = -sign;
> + }
> +
> + for (i = 0; i < NUM; i += 2)
> + dst.x[i / 2] = _mm_cmpgt_epi64 (src1.x[i / 2], src2.x[i / 2]);
> +
> + for (i = 0; i < NUM; i++)
> + {
> + is_eq = src1.ll[i] > src2.ll[i] ? 0xFFFFFFFFFFFFFFFFLL : 0LL;
> + if (is_eq != dst.ll[i])
> + abort ();
> + }
> +}
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 6/6] rs6000: Guard some x86 intrinsics implementations
2021-08-09 20:23 ` [PATCH 6/6] rs6000: Guard some x86 intrinsics implementations Paul A. Clarke
@ 2021-08-18 19:27 ` Bill Schmidt
0 siblings, 0 replies; 17+ messages in thread
From: Bill Schmidt @ 2021-08-18 19:27 UTC (permalink / raw)
To: Paul A. Clarke, gcc-patches; +Cc: segher
Hi Paul,
On 8/9/21 3:23 PM, Paul A. Clarke via Gcc-patches wrote:
> Some compatibility implementations of x86 intrinsics include
> Power intrinsics which require POWER8. Guard them.
>
> emmintrin.h:
> - _mm_cmpord_pd: Remove code which was ostensibly for pre-POWER8,
> but which indeed depended on POWER8 (vec_cmpgt(v2du)/vcmpgtud).
> The "POWER8" version works fine on pre-POWER8.
> - _mm_mul_epu32: vec_mule(v4su) uses vmuleuw.
> pmmintrin.h:
> - _mm_movehdup_ps: vec_mergeo(v4su) uses vmrgow.
> - _mm_moveldup_ps: vec_mergee(v4su) uses vmrgew.
> smmintrin.h:
> - _mm_cmpeq_epi64: vec_cmpeq(v2di) uses vcmpequd.
> - _mm_mul_epi32: vec_mule(v4si) uses vmuluwm.
> - _mm_cmpgt_epi64: vec_cmpgt(v2di) uses vcmpgtsd.
> tmmintrin.h:
> - _mm_sign_epi8: vec_neg(v4si) uses vsububm.
> - _mm_sign_epi16: vec_neg(v4si) uses vsubuhm.
> - _mm_sign_epi32: vec_neg(v4si) uses vsubuwm.
> Note that the above three could actually be supported pre-POWER8,
> but current GCC does not support them before POWER8.
> - _mm_sign_pi8: depends on _mm_sign_epi8.
> - _mm_sign_pi16: depends on _mm_sign_epi16.
> - _mm_sign_pi32: depends on _mm_sign_epi32.
Testing, backports, etc.
>
> 2021-08-09 Paul A. Clarke <pc@us.ibm.com>
>
> gcc
I think you mentioned there's a PR open for this.
> * config/rs6000/emmintrin.h: Guard POWER8 intrinsics.
> * config/rs6000/pmmintrin.h: Same.
> * config/rs6000/smmintrin.h: Same.
> * config/rs6000/tmmintrin.h: Same.
> ---
> gcc/config/rs6000/emmintrin.h | 12 ++----------
> gcc/config/rs6000/pmmintrin.h | 2 ++
> gcc/config/rs6000/smmintrin.h | 4 ++++
> gcc/config/rs6000/tmmintrin.h | 2 ++
> 4 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/gcc/config/rs6000/emmintrin.h b/gcc/config/rs6000/emmintrin.h
> index ce1287edf782..32ad72b4cc35 100644
> --- a/gcc/config/rs6000/emmintrin.h
> +++ b/gcc/config/rs6000/emmintrin.h
> @@ -430,20 +430,10 @@ _mm_cmpnge_pd (__m128d __A, __m128d __B)
> extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
> _mm_cmpord_pd (__m128d __A, __m128d __B)
> {
> -#if _ARCH_PWR8
> __v2du c, d;
> /* Compare against self will return false (0's) if NAN. */
> c = (__v2du)vec_cmpeq (__A, __A);
> d = (__v2du)vec_cmpeq (__B, __B);
> -#else
> - __v2du a, b;
> - __v2du c, d;
> - const __v2du double_exp_mask = {0x7ff0000000000000, 0x7ff0000000000000};
> - a = (__v2du)vec_abs ((__v2df)__A);
> - b = (__v2du)vec_abs ((__v2df)__B);
> - c = (__v2du)vec_cmpgt (double_exp_mask, a);
> - d = (__v2du)vec_cmpgt (double_exp_mask, b);
> -#endif
> /* A != NAN and B != NAN. */
> return ((__m128d)vec_and(c, d));
> }
> @@ -1472,6 +1462,7 @@ _mm_mul_su32 (__m64 __A, __m64 __B)
> return ((__m64)a * (__m64)b);
> }
>
> +#ifdef _ARCH_PWR8
> extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
> _mm_mul_epu32 (__m128i __A, __m128i __B)
> {
> @@ -1498,6 +1489,7 @@ _mm_mul_epu32 (__m128i __A, __m128i __B)
> return (__m128i) vec_mule ((__v4su)__A, (__v4su)__B);
> #endif
> }
> +#endif
>
> extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
> _mm_slli_epi16 (__m128i __A, int __B)
> diff --git a/gcc/config/rs6000/pmmintrin.h b/gcc/config/rs6000/pmmintrin.h
> index eab712fdfa66..d5da1a6daa34 100644
> --- a/gcc/config/rs6000/pmmintrin.h
> +++ b/gcc/config/rs6000/pmmintrin.h
> @@ -123,6 +123,7 @@ _mm_hsub_pd (__m128d __X, __m128d __Y)
> vec_mergel ((__v2df) __X, (__v2df)__Y));
> }
>
> +#ifdef _ARCH_PWR8
> extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
> _mm_movehdup_ps (__m128 __X)
> {
> @@ -134,6 +135,7 @@ _mm_moveldup_ps (__m128 __X)
> {
> return (__m128)vec_mergee ((__v4su)__X, (__v4su)__X);
> }
> +#endif
Up to you and the maintainers, but I would have a slight preference for
putting the #ifdef/#endif around each individual function, rather than
groups of functions. It's more maintainable that way.
Otherwise LGTM.
Thanks!
Bill
>
> extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
> _mm_loaddup_pd (double const *__P)
> diff --git a/gcc/config/rs6000/smmintrin.h b/gcc/config/rs6000/smmintrin.h
> index 8d6ae98c7ce3..d2ba5f11de2e 100644
> --- a/gcc/config/rs6000/smmintrin.h
> +++ b/gcc/config/rs6000/smmintrin.h
> @@ -278,6 +278,7 @@ _mm_extract_ps (__m128 __X, const int __N)
> return ((__v4si)__X)[__N & 3];
> }
>
> +#ifdef _ARCH_PWR8
> extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
> _mm_blend_epi16 (__m128i __A, __m128i __B, const int __imm8)
> {
> @@ -289,6 +290,7 @@ _mm_blend_epi16 (__m128i __A, __m128i __B, const int __imm8)
> #endif
> return (__m128i) vec_sel ((__v8hu) __A, (__v8hu) __B, __shortmask);
> }
> +#endif
>
> extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
> _mm_blendv_epi8 (__m128i __A, __m128i __B, __m128i __mask)
> @@ -349,6 +351,7 @@ _mm_blend_pd (__m128d __A, __m128d __B, const int __imm8)
> return (__m128d) __r;
> }
>
> +#ifdef _ARCH_PWR8
> __inline __m128d
> __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> _mm_blendv_pd (__m128d __A, __m128d __B, __m128d __mask)
> @@ -357,6 +360,7 @@ _mm_blendv_pd (__m128d __A, __m128d __B, __m128d __mask)
> const __vector __bool long long __boolmask = vec_cmplt ((__v2di) __mask, __zero);
> return (__m128d) vec_sel ((__v2du) __A, (__v2du) __B, (__v2du) __boolmask);
> }
> +#endif
>
> __inline int
> __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> diff --git a/gcc/config/rs6000/tmmintrin.h b/gcc/config/rs6000/tmmintrin.h
> index 971511260b78..4120cc1ea551 100644
> --- a/gcc/config/rs6000/tmmintrin.h
> +++ b/gcc/config/rs6000/tmmintrin.h
> @@ -350,6 +350,7 @@ _mm_shuffle_pi8 (__m64 __A, __m64 __B)
> return (__m64) ((__v2du) (__C))[0];
> }
>
> +#ifdef _ARCH_PWR8
> extern __inline __m128i
> __attribute__((__gnu_inline__, __always_inline__, __artificial__))
> _mm_sign_epi8 (__m128i __A, __m128i __B)
> @@ -418,6 +419,7 @@ _mm_sign_pi32 (__m64 __A, __m64 __B)
> __C = (__v4si) _mm_sign_epi32 ((__m128i) __C, (__m128i) __D);
> return (__m64) ((__v2du) (__C))[0];
> }
> +#endif
>
> extern __inline __m128i
> __attribute__((__gnu_inline__, __always_inline__, __artificial__))
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/6] rs6000: Support SSE4.1 "round" intrinsics
2021-08-18 19:01 ` Bill Schmidt
@ 2021-08-18 22:22 ` Segher Boessenkool
0 siblings, 0 replies; 17+ messages in thread
From: Segher Boessenkool @ 2021-08-18 22:22 UTC (permalink / raw)
To: Bill Schmidt; +Cc: Paul A. Clarke, gcc-patches
On Wed, Aug 18, 2021 at 02:01:33PM -0500, Bill Schmidt wrote:
> On 8/9/21 3:23 PM, Paul A. Clarke via Gcc-patches wrote:
> Reminder: Please specify what testing you've done and on which
> platforms,
Yes please.
> and where you want to apply the patches (i.e., do you want
> backports?).
Backports are not suitable for features, in general. If nothing is said
I assume no backports (for any patch).
> >+ if (__rounding & _MM_FROUND_NO_EXC)
> >+ {
> >+ /* Save enabled exceptions, and disable all exceptions.
> >+ Pre-POWER9, mffsce decodes to mffs, requiring the additional
> >+ mtfsf, below, to disable exceptions. */
> >+ __asm__ __volatile__ (
> >+ ".machine push; .machine \"power9\"; mffsce %0; .machine pop"
>
>
> As we discussed, this cleverness causes trouble by introducing a
> dependency on a binutils that recognizes .machine "power9". Better to
> just #ifdef this and specify mffsce versus mffs.
It needs testing on all possible pre-p9 systems, because of this
cleverness, too.
( at the end of a line is always wrong btw.
> >+ switch (__rounding)
> >+ {
> >+ case _MM_FROUND_TO_NEAREST_INT:
> >+ __tmp.__fr = __builtin_mffsl ();
>
> Another clever encoding trick, but dangerous. __builtin_mffsl isn't
> guaranteed to be recognized on P8 or earlier, even if it happens to work
> today. Just use mffs and mffsl under #ifdef control.
Yeah. It isn't mentioned in the architecture that this is safe to use,
so if you really have to, it has to be tested everywhere. But better is
to just avoid it.
There are various builtins that automatically create backwards-compatible
code when needed. One of those is __builtin_mffsl. Please use it :-)
> >+ __attribute__((fallthrough));
>
> Well done. :-) A lot of people miss this.
The compiler is supposed to warn whenever you do forget it :-)
> >+ case _MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC:
> >+ {
> >+ __builtin_set_fpscr_rn (0b00);
> >+ __r = vec_rint ((__v2df) __A);
> >+ __builtin_set_fpscr_rn (__tmp.__fpscr);
> >+ }
> >+ break;
That layout isn't right. You probably want the break inside the block?
Why do you want a block at all, anyway?
> >+ __asm__ __volatile__ (
> >+ ".machine push; .machine \"power9\"; mffsce %0; .machine pop"
>
> Same issues in this function as above, I won't repeat them all.
You need no quotes either, so you don't need to quote the quotes, fwiw.
Segher
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/6] rs6000: Support SSE4.1 "round" intrinsics
2021-08-09 20:23 ` [PATCH 1/6] rs6000: Support SSE4.1 "round" intrinsics Paul A. Clarke
2021-08-18 19:01 ` Bill Schmidt
@ 2021-08-18 22:46 ` Segher Boessenkool
2021-08-19 18:16 ` Paul A. Clarke
1 sibling, 1 reply; 17+ messages in thread
From: Segher Boessenkool @ 2021-08-18 22:46 UTC (permalink / raw)
To: Paul A. Clarke; +Cc: gcc-patches
On Mon, Aug 09, 2021 at 03:23:50PM -0500, Paul A. Clarke wrote:
> Suppress exceptions (when specified), by saving, manipulating, and
> restoring the FPSCR. Similarly, save, set, and restore the floating-point
> rounding mode when required.
>
> No attempt is made to optimize writing the FPSCR (by checking if the new
> value would be the same), other than using lighter weight instructions
> when possible.
There are __builtin_set_fpscr_rn and friends, please use those, those
are optimised for any platform.
> * config/rs6000/smmintrin.h (_mm_ceil_pd, _mm_ceil_ps, _mm_ceil_sd,
> _mm_ceil_ss, _mm_floor_pd, _mm_floor_ps, _mm_floor_sd, _mm_floor_ss):
> Convert from function to macro.
Please explain why you regress this (not in the changelog of course).
> +/* Rounding mode macros. */
> +#define _MM_FROUND_TO_NEAREST_INT 0x00
> +#define _MM_FROUND_TO_ZERO 0x01
> +#define _MM_FROUND_TO_POS_INF 0x02
> +#define _MM_FROUND_TO_NEG_INF 0x03
> +#define _MM_FROUND_CUR_DIRECTION 0x04
You can just write "0" .. "4", heh.
> +
> +#define _MM_FROUND_NINT \
> + (_MM_FROUND_TO_NEAREST_INT | _MM_FROUND_RAISE_EXC)
> +#define _MM_FROUND_FLOOR \
> + (_MM_FROUND_TO_NEG_INF | _MM_FROUND_RAISE_EXC)
> +#define _MM_FROUND_CEIL \
> + (_MM_FROUND_TO_POS_INF | _MM_FROUND_RAISE_EXC)
> +#define _MM_FROUND_TRUNC \
> + (_MM_FROUND_TO_ZERO | _MM_FROUND_RAISE_EXC)
> +#define _MM_FROUND_RINT \
> + (_MM_FROUND_CUR_DIRECTION | _MM_FROUND_RAISE_EXC)
> +#define _MM_FROUND_NEARBYINT \
> + (_MM_FROUND_CUR_DIRECTION | _MM_FROUND_NO_EXC)
All these macro definitions will comfortably fit on one line.
> +__inline __m128d
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_round_pd (__m128d __A, int __rounding)
> +{
Non-static inline is not what you want, esp. with gnu-inline? Or, what
is the goal, and why can you not do it with modern inline?
> + __v2df __r;
> + union {
> + double __fr;
> + long long __fpscr;
> + } __save, __tmp;
> +
> + if (__rounding & _MM_FROUND_NO_EXC)
> + {
Wrong indent. This code is very hard to read because of that.
If you figure that gee, it would be a nice if we had a builtin for
mffsce, then please make one? :-)
> + case _MM_FROUND_TO_NEAREST_INT:
> + __tmp.__fr = __builtin_mffsl ();
> + __attribute__((fallthrough));
Space before (.
> + case _MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC:
Space after |.
Please fix these things and resend.
Segher
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/6] rs6000: Support SSE4.1 "round" intrinsics
2021-08-18 22:46 ` Segher Boessenkool
@ 2021-08-19 18:16 ` Paul A. Clarke
2021-08-19 19:47 ` Segher Boessenkool
0 siblings, 1 reply; 17+ messages in thread
From: Paul A. Clarke @ 2021-08-19 18:16 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: gcc-patches
On Wed, Aug 18, 2021 at 05:46:58PM -0500, Segher Boessenkool wrote:
> On Mon, Aug 09, 2021 at 03:23:50PM -0500, Paul A. Clarke wrote:
> > Suppress exceptions (when specified), by saving, manipulating, and
> > restoring the FPSCR. Similarly, save, set, and restore the floating-point
> > rounding mode when required.
> >
> > No attempt is made to optimize writing the FPSCR (by checking if the new
> > value would be the same), other than using lighter weight instructions
> > when possible.
>
> There are __builtin_set_fpscr_rn and friends, please use those, those
> are optimised for any platform.
I do. (Unless I missed an opportunity somewhere?)
The "optimize" comment refers to, for example, not checking the current
rounding mode before setting and restoring it.
> > * config/rs6000/smmintrin.h (_mm_ceil_pd, _mm_ceil_ps, _mm_ceil_sd,
> > _mm_ceil_ss, _mm_floor_pd, _mm_floor_ps, _mm_floor_sd, _mm_floor_ss):
> > Convert from function to macro.
>
> Please explain why you regress this (not in the changelog of course).
I'm not sure what "regress" means here?
I should've said that these are now identical implementations to those
found in config/i386/smmintrin.h. I'll add that to the commit message
in v2.
> > +/* Rounding mode macros. */
> > +#define _MM_FROUND_TO_NEAREST_INT 0x00
> > +#define _MM_FROUND_TO_ZERO 0x01
> > +#define _MM_FROUND_TO_POS_INF 0x02
> > +#define _MM_FROUND_TO_NEG_INF 0x03
> > +#define _MM_FROUND_CUR_DIRECTION 0x04
>
> You can just write "0" .. "4", heh.
Copied from config/i386/smmintrin.h.
> > +#define _MM_FROUND_NINT \
> > + (_MM_FROUND_TO_NEAREST_INT | _MM_FROUND_RAISE_EXC)
> > +#define _MM_FROUND_FLOOR \
> > + (_MM_FROUND_TO_NEG_INF | _MM_FROUND_RAISE_EXC)
> > +#define _MM_FROUND_CEIL \
> > + (_MM_FROUND_TO_POS_INF | _MM_FROUND_RAISE_EXC)
> > +#define _MM_FROUND_TRUNC \
> > + (_MM_FROUND_TO_ZERO | _MM_FROUND_RAISE_EXC)
> > +#define _MM_FROUND_RINT \
> > + (_MM_FROUND_CUR_DIRECTION | _MM_FROUND_RAISE_EXC)
> > +#define _MM_FROUND_NEARBYINT \
> > + (_MM_FROUND_CUR_DIRECTION | _MM_FROUND_NO_EXC)
>
> All these macro definitions will comfortably fit on one line.
Copied from config/i386/smmintrin.h.
> > +__inline __m128d
> > +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> > +_mm_round_pd (__m128d __A, int __rounding)
> > +{
>
> Non-static inline is not what you want, esp. with gnu-inline? Or, what
> is the goal, and why can you not do it with modern inline?
This is the same basic signature as the other 600+ intrinsics.
Actually, they were all described as "extern", but in a previous
review, you said:
> "extern" on definitions is superfluous
So, I've dropped that for newer ones.
Should they all instead be "static"?
The goal is to be compatible with the i386 implementations.
Those typically use something like:
extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
(which kinda makes me want to put "extern" back, now that I think
about it).
I'm not sure what you mean by "modern inline".
> > + __v2df __r;
> > + union {
> > + double __fr;
> > + long long __fpscr;
> > + } __save, __tmp;
> > +
> > + if (__rounding & _MM_FROUND_NO_EXC)
> > + {
>
> Wrong indent. This code is very hard to read because of that.
OK, will fix in v2.
> If you figure that gee, it would be a nice if we had a builtin for
> mffsce, then please make one? :-)
Is one use-case sufficient grounds? I can give it a shot if so.
> > + case _MM_FROUND_TO_NEAREST_INT:
> > + __tmp.__fr = __builtin_mffsl ();
> > + __attribute__((fallthrough));
>
> Space before (.
OK
> > + case _MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC:
>
> Space after |.
OK
> Please fix these things and resend.
Will do. Thanks!
PC
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/6] rs6000: Support SSE4.1 "round" intrinsics
2021-08-19 18:16 ` Paul A. Clarke
@ 2021-08-19 19:47 ` Segher Boessenkool
0 siblings, 0 replies; 17+ messages in thread
From: Segher Boessenkool @ 2021-08-19 19:47 UTC (permalink / raw)
To: Paul A. Clarke; +Cc: gcc-patches
Hi!
On Thu, Aug 19, 2021 at 01:16:16PM -0500, Paul A. Clarke wrote:
> On Wed, Aug 18, 2021 at 05:46:58PM -0500, Segher Boessenkool wrote:
> > There are __builtin_set_fpscr_rn and friends, please use those, those
> > are optimised for any platform.
>
> I do. (Unless I missed an opportunity somewhere?)
It looked to me like you do a lot of unnecessary asm.
> > > * config/rs6000/smmintrin.h (_mm_ceil_pd, _mm_ceil_ps, _mm_ceil_sd,
> > > _mm_ceil_ss, _mm_floor_pd, _mm_floor_ps, _mm_floor_sd, _mm_floor_ss):
> > > Convert from function to macro.
> >
> > Please explain why you regress this (not in the changelog of course).
>
> I'm not sure what "regress" means here?
Macros are from the 1970's, inline functions are the new hot. Why do
you need macros here? The patch should say (the patch message likely).
> > > +#define _MM_FROUND_TO_NEAREST_INT 0x00
> > > +#define _MM_FROUND_TO_ZERO 0x01
> > > +#define _MM_FROUND_TO_POS_INF 0x02
> > > +#define _MM_FROUND_TO_NEG_INF 0x03
> > > +#define _MM_FROUND_CUR_DIRECTION 0x04
> >
> > You can just write "0" .. "4", heh.
>
> Copied from config/i386/smmintrin.h.
That doesn't make it less silly :-)
> > > +__inline __m128d
> > > +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> > > +_mm_round_pd (__m128d __A, int __rounding)
> > > +{
> >
> > Non-static inline is not what you want, esp. with gnu-inline? Or, what
> > is the goal, and why can you not do it with modern inline?
>
> This is the same basic signature as the other 600+ intrinsics.
> Actually, they were all described as "extern", but in a previous
> review, you said:
> > "extern" on definitions is superfluous
> So, I've dropped that for newer ones.
> Should they all instead be "static"?
>
> The goal is to be compatible with the i386 implementations.
> Those typically use something like:
>
> extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
>
> (which kinda makes me want to put "extern" back, now that I think
> about it).
"extern" is not redundant for inline functions. Since you have
always_inline here, gnu_inline extern inline has the same meaning as
static inline in portable C.
> I'm not sure what you mean by "modern inline".
Not using the long deprecated gnu_inline.
> > Wrong indent. This code is very hard to read because of that.
>
> OK, will fix in v2.
Thanks!
> > If you figure that gee, it would be a nice if we had a builtin for
> > mffsce, then please make one? :-)
>
> Is one use-case sufficient grounds? I can give it a shot if so.
If it is useful for others, then yes please! Ideally you can make a
builtin that we can also reasonably implement without support for the
new insns, so we can use the builtin whenever the builtin exists.
Thanks,
Segher
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2021-08-19 19:48 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-09 20:23 [PATCH 0/6] rs6000: Support more SSE4.1 intrinsics Paul A. Clarke
2021-08-09 20:23 ` [PATCH 1/6] rs6000: Support SSE4.1 "round" intrinsics Paul A. Clarke
2021-08-18 19:01 ` Bill Schmidt
2021-08-18 22:22 ` Segher Boessenkool
2021-08-18 22:46 ` Segher Boessenkool
2021-08-19 18:16 ` Paul A. Clarke
2021-08-19 19:47 ` Segher Boessenkool
2021-08-09 20:23 ` [PATCH 2/6] rs6000: Support SSE4.1 "min" and "max" intrinsics Paul A. Clarke
2021-08-18 19:08 ` Bill Schmidt
2021-08-09 20:23 ` [PATCH 3/6] rs6000: Simplify some SSE4.1 "test" intrinsics Paul A. Clarke
2021-08-18 19:10 ` Bill Schmidt
2021-08-09 20:23 ` [PATCH 4/6] rs6000: Support SSE4.1 "cvt" intrinsics Paul A. Clarke
2021-08-18 19:19 ` Bill Schmidt
2021-08-09 20:23 ` [PATCH 5/6] rs6000: Support more SSE4.1 "cmp", "mul", "pack" intrinsics Paul A. Clarke
2021-08-18 19:21 ` Bill Schmidt
2021-08-09 20:23 ` [PATCH 6/6] rs6000: Guard some x86 intrinsics implementations Paul A. Clarke
2021-08-18 19:27 ` Bill Schmidt
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).