From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by sourceware.org (Postfix) with ESMTPS id 1CC993858C39 for ; Fri, 10 Sep 2021 04:36:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1CC993858C39 X-IronPort-AV: E=McAfee;i="6200,9189,10102"; a="284692555" X-IronPort-AV: E=Sophos;i="5.85,282,1624345200"; d="scan'208";a="284692555" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2021 21:36:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,282,1624345200"; d="scan'208";a="479991864" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga008.jf.intel.com with ESMTP; 09 Sep 2021 21:36:35 -0700 Received: from shliclel219.sh.intel.com (shliclel219.sh.intel.com [10.239.236.219]) by scymds01.sc.intel.com with ESMTP id 18A4aXgm018271; Thu, 9 Sep 2021 21:36:33 -0700 From: liuhongt To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, rdsandiford@googlemail.com, crazylht@gmail.com, hjl.tools@gmail.com Subject: [PATCH] Relax condition of (vec_concat:M(vec_select op0 idx0)(vec_select op0 idx1)) to allow different modes between op0 and M, but have same inner mode. Date: Fri, 10 Sep 2021 12:36:32 +0800 Message-Id: <20210910043632.1087666-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 10 Sep 2021 04:36:41 -0000 Currently for (vec_concat:M (vec_select op0 idx1)(vec_select op0 idx2)), optimizer wouldn't simplify if op0 has different mode with M, but that's too restrict which will prevent below optimization, the condition can be relaxed to op0 must have same inner mode with M. (set (reg:V2DF 87 [ xx ]) (vec_concat:V2DF (vec_select:DF (reg:V4DF 92) (parallel [ (const_int 2 [0x2]) ])) (vec_select:DF (reg:V4DF 92) (parallel [ (const_int 3 [0x3]) ])))) Bootsrapped and regtested on x86_64-linux-gnu{-m32,}. Ok for trunk? gcc/ChangeLog: * simplify-rtx.c (simplify_context::simplify_binary_operation_1): Relax condition of simplifying (vec_concat:M (vec_select op0 index0)(vec_select op1 index1)) to allow different modes between op0 and M, but have same inner mode. gcc/testsuite/ChangeLog: * gcc.target/i386/vect-rebuild.c: * gcc.target/i386/avx512f-vect-rebuild.c: New test. --- gcc/simplify-rtx.c | 3 ++- .../gcc.target/i386/avx512f-vect-rebuild.c | 21 +++++++++++++++++++ gcc/testsuite/gcc.target/i386/vect-rebuild.c | 2 +- 3 files changed, 24 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-vect-rebuild.c diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c index ebad5cb5a79..16286befd79 100644 --- a/gcc/simplify-rtx.c +++ b/gcc/simplify-rtx.c @@ -4587,7 +4587,8 @@ simplify_context::simplify_binary_operation_1 (rtx_code code, if (GET_CODE (trueop0) == VEC_SELECT && GET_CODE (trueop1) == VEC_SELECT && rtx_equal_p (XEXP (trueop0, 0), XEXP (trueop1, 0)) - && GET_MODE (XEXP (trueop0, 0)) == mode) + && GET_MODE_INNER (GET_MODE (XEXP (trueop0, 0))) + == GET_MODE_INNER(mode)) { rtx par0 = XEXP (trueop0, 1); rtx par1 = XEXP (trueop1, 1); diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vect-rebuild.c b/gcc/testsuite/gcc.target/i386/avx512f-vect-rebuild.c new file mode 100644 index 00000000000..aef6855aa46 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vect-rebuild.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mavx512vl -mavx512dq -fno-tree-forwprop" } */ + +typedef double v2df __attribute__ ((__vector_size__ (16))); +typedef double v4df __attribute__ ((__vector_size__ (32))); + +v2df h (v4df x) +{ + v2df xx = { x[2], x[3] }; + return xx; +} + +v4df f2 (v4df x) +{ + v4df xx = { x[0], x[1], x[2], x[3] }; + return xx; +} + +/* { dg-final { scan-assembler-not "unpck" } } */ +/* { dg-final { scan-assembler-not "valign" } } */ +/* { dg-final { scan-assembler-times "\tv?extract(?:f128|f64x2)\[ \t\]" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/vect-rebuild.c b/gcc/testsuite/gcc.target/i386/vect-rebuild.c index 570967f6b5c..8e85b98bf1d 100644 --- a/gcc/testsuite/gcc.target/i386/vect-rebuild.c +++ b/gcc/testsuite/gcc.target/i386/vect-rebuild.c @@ -30,4 +30,4 @@ v2df h (v4df x) /* { dg-final { scan-assembler-not "unpck" } } */ /* { dg-final { scan-assembler-times "\tv?permilpd\[ \t\]" 1 } } */ -/* { dg-final { scan-assembler-times "\tv?extractf128\[ \t\]" 1 } } */ +/* { dg-final { scan-assembler-times "\tv?extract(?:f128|f64x2)\[ \t\]" 1 } } */ -- 2.27.0