From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by sourceware.org (Postfix) with ESMTPS id 75D0F3858405 for ; Fri, 10 Sep 2021 12:58:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 75D0F3858405 X-IronPort-AV: E=McAfee;i="6200,9189,10102"; a="219208747" X-IronPort-AV: E=Sophos;i="5.85,282,1624345200"; d="scan'208";a="219208747" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2021 05:58:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,282,1624345200"; d="scan'208";a="432236491" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga003.jf.intel.com with ESMTP; 10 Sep 2021 05:58:24 -0700 Received: from shliclel219.sh.intel.com (shliclel219.sh.intel.com [10.239.236.219]) by scymds01.sc.intel.com with ESMTP id 18ACwIBu025632; Fri, 10 Sep 2021 05:58:23 -0700 From: liuhongt To: gcc-patches@gcc.gnu.org Cc: meissner@linux.ibm.com, segher@kernel.crashing.org, richard.guenther@gmail.com, jimw@sifive.com, schwab@linux-m68k.org, andrew@sifive.com, asolokha@gmx.com Subject: [PATCH 1/2] Revert "Get rid of all float-int special cases in validate_subreg." Date: Fri, 10 Sep 2021 20:58:17 +0800 Message-Id: <20210910125818.334531-2-hongtao.liu@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210910125818.334531-1-hongtao.liu@intel.com> References: <20210910125818.334531-1-hongtao.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 10 Sep 2021 12:58:27 -0000 This reverts commit d2874d905647a1d146dafa60199d440e837adc4d. PR target/102254 PR target/102154 PR target/102211 --- gcc/emit-rtl.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/gcc/emit-rtl.c b/gcc/emit-rtl.c index 77ea8948ee8..ff3b4449b37 100644 --- a/gcc/emit-rtl.c +++ b/gcc/emit-rtl.c @@ -922,6 +922,46 @@ validate_subreg (machine_mode omode, machine_mode imode, poly_uint64 regsize = REGMODE_NATURAL_SIZE (imode); + /* ??? This should not be here. Temporarily continue to allow word_mode + subregs of anything. The most common offender is (subreg:SI (reg:DF)). + Generally, backends are doing something sketchy but it'll take time to + fix them all. */ + if (omode == word_mode) + ; + /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_field + is the culprit here, and not the backends. */ + else if (known_ge (osize, regsize) && known_ge (isize, osize)) + ; + /* Allow component subregs of complex and vector. Though given the below + extraction rules, it's not always clear what that means. */ + else if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode)) + && GET_MODE_INNER (imode) == omode) + ; + /* ??? x86 sse code makes heavy use of *paradoxical* vector subregs, + i.e. (subreg:V4SF (reg:SF) 0) or (subreg:V4SF (reg:V2SF) 0). This + surely isn't the cleanest way to represent this. It's questionable + if this ought to be represented at all -- why can't this all be hidden + in post-reload splitters that make arbitrarily mode changes to the + registers themselves. */ + else if (VECTOR_MODE_P (omode) + && GET_MODE_INNER (omode) == GET_MODE_INNER (imode)) + ; + /* Subregs involving floating point modes are not allowed to + change size. Therefore (subreg:DI (reg:DF) 0) is fine, but + (subreg:SI (reg:DF) 0) isn't. */ + else if (FLOAT_MODE_P (imode) || FLOAT_MODE_P (omode)) + { + if (! (known_eq (isize, osize) + /* LRA can use subreg to store a floating point value in + an integer mode. Although the floating point and the + integer modes need the same number of hard registers, + the size of floating point mode can be less than the + integer mode. LRA also uses subregs for a register + should be used in different mode in on insn. */ + || lra_in_progress)) + return false; + } + /* Paradoxical subregs must have offset zero. */ if (maybe_gt (osize, isize)) return known_eq (offset, 0U); -- 2.27.0