From: Richard Earnshaw <rearnsha@arm.com>
To: gcc-patches@gcc.gnu.org
Cc: Richard Earnshaw <rearnsha@arm.com>
Subject: [PATCH v3 2/3] arm: expand handling of movmisalign for DImode [PR102125]
Date: Fri, 10 Sep 2021 15:48:40 +0100 [thread overview]
Message-ID: <20210910144841.3139174-3-rearnsha@arm.com> (raw)
In-Reply-To: <20210910144841.3139174-1-rearnsha@arm.com>
[-- Attachment #1: Type: text/plain, Size: 465 bytes --]
DImode is currently handled only for machines with vector modes
enabled, but this is unduly restrictive and is generally better done
in core registers.
gcc/ChangeLog:
PR target/102125
* config/arm/arm.md (movmisaligndi): New define_expand.
* config/arm/vec-common.md (movmisalign<mode>): Iterate over VDQ mode.
---
gcc/config/arm/arm.md | 16 ++++++++++++++++
gcc/config/arm/vec-common.md | 4 ++--
2 files changed, 18 insertions(+), 2 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v3-0002-arm-expand-handling-of-movmisalign-for-DImode-PR1.patch --]
[-- Type: text/x-patch; name="v3-0002-arm-expand-handling-of-movmisalign-for-DImode-PR1.patch", Size: 1556 bytes --]
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 5d3f21b91c4..4adc976b8b6 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -12617,6 +12617,22 @@ (define_expand "copysigndf3"
}"
)
+;; movmisalign for DImode
+(define_expand "movmisaligndi"
+ [(match_operand:DI 0 "general_operand")
+ (match_operand:DI 1 "general_operand")]
+ "unaligned_access"
+{
+ rtx lo_op0 = gen_lowpart (SImode, operands[0]);
+ rtx lo_op1 = gen_lowpart (SImode, operands[1]);
+ rtx hi_op0 = gen_highpart_mode (SImode, DImode, operands[0]);
+ rtx hi_op1 = gen_highpart_mode (SImode, DImode, operands[1]);
+
+ emit_insn (gen_movmisalignsi (lo_op0, lo_op1));
+ emit_insn (gen_movmisalignsi (hi_op0, hi_op1));
+ DONE;
+})
+
;; movmisalign patterns for HImode and SImode.
(define_expand "movmisalign<mode>"
[(match_operand:HSI 0 "general_operand")
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index 68de4f0f943..e71d9b3811f 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -281,8 +281,8 @@ (define_expand "cml<fcmac1><conj_op><mode>4"
})
(define_expand "movmisalign<mode>"
- [(set (match_operand:VDQX 0 "neon_perm_struct_or_reg_operand")
- (unspec:VDQX [(match_operand:VDQX 1 "neon_perm_struct_or_reg_operand")]
+ [(set (match_operand:VDQ 0 "neon_perm_struct_or_reg_operand")
+ (unspec:VDQ [(match_operand:VDQ 1 "neon_perm_struct_or_reg_operand")]
UNSPEC_MISALIGNED_ACCESS))]
"ARM_HAVE_<MODE>_LDST && !BYTES_BIG_ENDIAN
&& unaligned_access && !TARGET_REALLY_IWMMXT"
next prev parent reply other threads:[~2021-09-10 14:48 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-10 14:48 [PATCH v3 0/3] lower more cases of memcpy [PR102125] Richard Earnshaw
2021-09-10 14:48 ` [PATCH v3 1/3] rtl: directly handle MEM in gen_highpart [PR102125] Richard Earnshaw
2021-09-13 9:38 ` Richard Biener
2021-09-13 9:38 ` Richard Sandiford
2021-09-13 9:51 ` Richard Earnshaw
2021-09-13 9:54 ` Richard Sandiford
2021-09-10 14:48 ` Richard Earnshaw [this message]
2021-09-10 14:48 ` [PATCH v3 3/3] gimple: allow more folding of memcpy [PR102125] Richard Earnshaw
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