From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by sourceware.org (Postfix) with ESMTP id B15EB3858414; Wed, 15 Sep 2021 14:15:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B15EB3858414 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=kernel.crashing.org Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id 18FEEw8o007771; Wed, 15 Sep 2021 09:14:59 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id 18FEEwT2007770; Wed, 15 Sep 2021 09:14:58 -0500 X-Authentication-Warning: gate.crashing.org: segher set sender to segher@kernel.crashing.org using -f Date: Wed, 15 Sep 2021 09:14:58 -0500 From: Segher Boessenkool To: Xionghu Luo Cc: gcc-patches@gcc.gnu.org, dje.gcc@gmail.com, wschmidt@linux.ibm.com, guojiufu@linux.ibm.com, linkw@gcc.gnu.org Subject: Re: [PATCH] rs6000: Fix wrong code generation for vec_sel [PR94613] Message-ID: <20210915141458.GL1583@gate.crashing.org> References: <20210430063258.2774866-1-luoxhu@linux.ibm.com> <20210513104931.GG10366@gate.crashing.org> <973f14d9-c626-89b4-753f-e5c613eef6f2@linux.ibm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <973f14d9-c626-89b4-753f-e5c613eef6f2@linux.ibm.com> User-Agent: Mutt/1.4.2.3i X-Spam-Status: No, score=-3.4 required=5.0 tests=BAYES_00, JMQ_SPF_NEUTRAL, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=no autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Sep 2021 14:16:01 -0000 Hi! Please do not send patches as attachments to replies. Each patch (or patch series) starts its own thread. New versions of patches (or patch series) are new threads. > From: Xionghu Luo > Date: Tue, 27 Apr 2021 01:07:25 -0500 > Subject: [PATCH 1/2] rs6000: Fix wrong code generation for vec_sel [PR94613] > * config/rs6000/rs6000-call.c (altivec_expand_vec_sel_builtin): > New. That fits on one line. Changelogs are 80 chars wide. > * config/rs6000/rs6000.c (rs6000_emit_vector_cond_expr): Use > bit-wise selection instead of per element. So "bit-wise" fits on the previous line, too. > + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) > + && rtx_equal_p (operands[2], operands[3])" The "&&" should align with "VECTOR.." (Many times in this). > +(define_insn "altivec_vsel4" > + [(set (match_operand:VM 0 "altivec_register_operand" "=v") > + (ior:VM > + (and:VM > + (match_operand:VM 1 "altivec_register_operand" "v") > + (match_operand:VM 2 "altivec_register_operand" "v")) > + (and:VM > + (not:VM (match_operand:VM 3 "altivec_register_operand" "v")) > + (match_operand:VM 4 "altivec_register_operand" "v"))))] > + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) > + && rtx_equal_p (operands[2], operands[3])" > + "vsel %0,%4,%1,%3" > [(set_attr "type" "vecmove")]) I still don't see how rtx_equal_p is correct here. Either it should be a match_dup or the constraints can do that. > + (ior:VEC_L > + (and:VEC_L (not:VEC_L (match_operand:VEC_L 3 "vlogical_operand")) > + (match_operand:VEC_L 1 "vlogical_operand")) We indent RTL by two chars, not one. An advantage of that is that wrong indent like in this last line is more obvious (the "(match.." should align with the "(not"). > + (and:VEC_L (match_dup 3) > + (match_operand:VEC_L 2 "vlogical_operand"))))] The two "(match.." should align here. > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr94613.c > @@ -0,0 +1,38 @@ > +/* { dg-do run } */ > +/* { dg-require-effective-target vmx_hw } */ > +/* { dg-options "-O3 -maltivec" } */ Why -O3? Please just -O2 (if that works). > From 74cf1fd298e4923c106deaba3192423d48049559 Mon Sep 17 00:00:00 2001 > From: Xionghu Luo > Date: Fri, 14 May 2021 01:21:06 -0500 > Subject: [PATCH 2/2] rs6000: Fold xxsel to vsel since they have same semantics Nevwer send two patches in one mail. Make a series please. > --- a/gcc/config/rs6000/altivec.md > +++ b/gcc/config/rs6000/altivec.md > @@ -668,59 +668,67 @@ (define_insn "*altivec_gev4sf" > [(set_attr "type" "veccmp")]) > > (define_insn "altivec_vsel" > - [(set (match_operand:VM 0 "altivec_register_operand" "=v") > + [(set (match_operand:VM 0 "altivec_register_operand" "=wa,v") > (ior:VM > (and:VM > - (not:VM (match_operand:VM 3 "altivec_register_operand" "v")) > - (match_operand:VM 1 "altivec_register_operand" "v")) > + (not:VM (match_operand:VM 3 "altivec_register_operand" "wa,v")) > + (match_operand:VM 1 "altivec_register_operand" "wa,v")) > (and:VM > - (match_operand:VM 2 "altivec_register_operand" "v") > - (match_operand:VM 4 "altivec_register_operand" "v"))))] > + (match_operand:VM 2 "altivec_register_operand" "wa,v") > + (match_operand:VM 4 "altivec_register_operand" "wa,v"))))] > "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) > && rtx_equal_p (operands[2], operands[3])" > - "vsel %0,%1,%4,%3" > + "@ > + xxsel %x0,%x1,%x4,%x3 > + vsel %0,%1,%4,%3" The mnemonics should align with the @. This ordering makes us prefer xxsel over vsel. Do we want that? We probably do, but it is a change I think? Do we want to add an "isa" attribute? Most patterns still don't, but we probably should wherever we can. "altivec_register_operand" is wrong. Just "gpc_reg_operand" I think? Segher