From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out30-45.freemail.mail.aliyun.com (out30-45.freemail.mail.aliyun.com [115.124.30.45]) by sourceware.org (Postfix) with ESMTPS id 6EDEA3858432 for ; Mon, 27 Sep 2021 11:37:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6EDEA3858432 X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R471e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=e01e04394; MF=gengqi@linux.alibaba.com; NM=1; PH=DS; RN=3; SR=0; TI=SMTPD_---0Upn7UVC_1632742668; Received: from ITEB-L-PF1LDBR8.hz.ali.com(mailfrom:gengqi@linux.alibaba.com fp:SMTPD_---0Upn7UVC_1632742668) by smtp.aliyun-inc.com(127.0.0.1); Mon, 27 Sep 2021 19:37:51 +0800 From: Geng Qi To: gcc-patches@gcc.gnu.org, cooper.qu@linux.alibaba.com Cc: Geng Qi Subject: [PATCH] RISC-V: Pattern name fix mulm3_highpart -> smulm3_highpart. Date: Mon, 27 Sep 2021 19:37:45 +0800 Message-Id: <20210927113745.171-1-gengqi@linux.alibaba.com> X-Mailer: git-send-email 2.22.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-20.9 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Sep 2021 11:37:56 -0000 gcc/ChangeLog: * config/riscv/riscv.md (muldi3_highpart): Rename to muldi3_highpart. (mulditi3): Emit muldi3_highpart. (mulsi3_highpart): Rename to mulsi3_highpart. (mulsidi3): Emit mulsi3_highpart. --- gcc/config/riscv/riscv.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index f88877fd596..3115a508bdf 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -899,14 +899,14 @@ emit_insn (gen_muldi3 (low, operands[1], operands[2])); rtx high = gen_reg_rtx (DImode); - emit_insn (gen_muldi3_highpart (high, operands[1], operands[2])); + emit_insn (gen_muldi3_highpart (high, operands[1], operands[2])); emit_move_insn (gen_lowpart (DImode, operands[0]), low); emit_move_insn (gen_highpart (DImode, operands[0]), high); DONE; }) -(define_insn "muldi3_highpart" +(define_insn "muldi3_highpart" [(set (match_operand:DI 0 "register_operand" "=r") (truncate:DI (lshiftrt:TI @@ -961,13 +961,13 @@ { rtx temp = gen_reg_rtx (SImode); emit_insn (gen_mulsi3 (temp, operands[1], operands[2])); - emit_insn (gen_mulsi3_highpart (riscv_subword (operands[0], true), + emit_insn (gen_mulsi3_highpart (riscv_subword (operands[0], true), operands[1], operands[2])); emit_insn (gen_movsi (riscv_subword (operands[0], false), temp)); DONE; }) -(define_insn "mulsi3_highpart" +(define_insn "mulsi3_highpart" [(set (match_operand:SI 0 "register_operand" "=r") (truncate:SI (lshiftrt:DI -- 2.22.0.windows.1