* [PATCH] RISC-V: Pattern name fix mulm3_highpart -> smulm3_highpart.
@ 2021-09-27 11:37 Geng Qi
2021-09-28 23:44 ` Jim Wilson
2021-09-28 23:48 ` [PATCH] RISC-V: Pattern name fix mul*3_highpart -> smul*3_highpart Jim Wilson
0 siblings, 2 replies; 3+ messages in thread
From: Geng Qi @ 2021-09-27 11:37 UTC (permalink / raw)
To: gcc-patches, cooper.qu; +Cc: Geng Qi
gcc/ChangeLog:
* config/riscv/riscv.md
(<u>muldi3_highpart): Rename to <su>muldi3_highpart.
(<u>mulditi3): Emit <su>muldi3_highpart.
(<u>mulsi3_highpart): Rename to <su>mulsi3_highpart.
(<u>mulsidi3): Emit <su>mulsi3_highpart.
---
gcc/config/riscv/riscv.md | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index f88877fd596..3115a508bdf 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -899,14 +899,14 @@
emit_insn (gen_muldi3 (low, operands[1], operands[2]));
rtx high = gen_reg_rtx (DImode);
- emit_insn (gen_<u>muldi3_highpart (high, operands[1], operands[2]));
+ emit_insn (gen_<su>muldi3_highpart (high, operands[1], operands[2]));
emit_move_insn (gen_lowpart (DImode, operands[0]), low);
emit_move_insn (gen_highpart (DImode, operands[0]), high);
DONE;
})
-(define_insn "<u>muldi3_highpart"
+(define_insn "<su>muldi3_highpart"
[(set (match_operand:DI 0 "register_operand" "=r")
(truncate:DI
(lshiftrt:TI
@@ -961,13 +961,13 @@
{
rtx temp = gen_reg_rtx (SImode);
emit_insn (gen_mulsi3 (temp, operands[1], operands[2]));
- emit_insn (gen_<u>mulsi3_highpart (riscv_subword (operands[0], true),
+ emit_insn (gen_<su>mulsi3_highpart (riscv_subword (operands[0], true),
operands[1], operands[2]));
emit_insn (gen_movsi (riscv_subword (operands[0], false), temp));
DONE;
})
-(define_insn "<u>mulsi3_highpart"
+(define_insn "<su>mulsi3_highpart"
[(set (match_operand:SI 0 "register_operand" "=r")
(truncate:SI
(lshiftrt:DI
--
2.22.0.windows.1
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] RISC-V: Pattern name fix mulm3_highpart -> smulm3_highpart.
2021-09-27 11:37 [PATCH] RISC-V: Pattern name fix mulm3_highpart -> smulm3_highpart Geng Qi
@ 2021-09-28 23:44 ` Jim Wilson
2021-09-28 23:48 ` [PATCH] RISC-V: Pattern name fix mul*3_highpart -> smul*3_highpart Jim Wilson
1 sibling, 0 replies; 3+ messages in thread
From: Jim Wilson @ 2021-09-28 23:44 UTC (permalink / raw)
To: Geng Qi; +Cc: GCC Patches, cooper
On Mon, Sep 27, 2021 at 4:38 AM Geng Qi via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> gcc/ChangeLog:
> * config/riscv/riscv.md
> (<u>muldi3_highpart): Rename to <su>muldi3_highpart.
> (<u>mulditi3): Emit <su>muldi3_highpart.
> (<u>mulsi3_highpart): Rename to <su>mulsi3_highpart.
> (<u>mulsidi3): Emit <su>mulsi3_highpart.
>
This doesn't build on top of tree sources. It is missing the
mulv<mode>3_highpart change I mentioned in the riscv-gcc review. Also, I
prefer that the order of the changelog entries match the order of hunks in
the patch, it is easier to review that way. Otherwise, the patch is OK and
I committed it with minor changes. Since I changed it, I need to send the
patch I did actually commit.
Jim
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH] RISC-V: Pattern name fix mul*3_highpart -> smul*3_highpart.
2021-09-27 11:37 [PATCH] RISC-V: Pattern name fix mulm3_highpart -> smulm3_highpart Geng Qi
2021-09-28 23:44 ` Jim Wilson
@ 2021-09-28 23:48 ` Jim Wilson
1 sibling, 0 replies; 3+ messages in thread
From: Jim Wilson @ 2021-09-28 23:48 UTC (permalink / raw)
To: gcc-patches; +Cc: Geng Qi
From: Geng Qi <gengqi@linux.alibaba.com>
No known code changes, just fixes an inconsistency that was noticed.
Committed.
Jim
gcc/
* config/riscv/riscv.md (mulv<mode>4): Call gen_smul<mode>3_highpart.
(<u>mulditi3): Call <su>muldi3_highpart.
(<u>muldi3_highpart): Rename to <su>muldi3_highpart.
(<u>mulsidi3): Call <su>mulsi3_highpart.
(<u>mulsi3_highpart): Rename to <su>mulsi3_highpart.
---
gcc/config/riscv/riscv.md | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index f88877fd596..98364f00f6d 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -802,7 +802,7 @@ (define_expand "mulv<mode>4"
rtx hp = gen_reg_rtx (<MODE>mode);
rtx lp = gen_reg_rtx (<MODE>mode);
- emit_insn (gen_mul<mode>3_highpart (hp, operands[1], operands[2]));
+ emit_insn (gen_smul<mode>3_highpart (hp, operands[1], operands[2]));
emit_insn (gen_mul<mode>3 (operands[0], operands[1], operands[2]));
emit_insn (gen_ashr<mode>3 (lp, operands[0],
GEN_INT (BITS_PER_WORD - 1)));
@@ -899,14 +899,14 @@ (define_expand "<u>mulditi3"
emit_insn (gen_muldi3 (low, operands[1], operands[2]));
rtx high = gen_reg_rtx (DImode);
- emit_insn (gen_<u>muldi3_highpart (high, operands[1], operands[2]));
+ emit_insn (gen_<su>muldi3_highpart (high, operands[1], operands[2]));
emit_move_insn (gen_lowpart (DImode, operands[0]), low);
emit_move_insn (gen_highpart (DImode, operands[0]), high);
DONE;
})
-(define_insn "<u>muldi3_highpart"
+(define_insn "<su>muldi3_highpart"
[(set (match_operand:DI 0 "register_operand" "=r")
(truncate:DI
(lshiftrt:TI
@@ -961,13 +961,13 @@ (define_expand "<u>mulsidi3"
{
rtx temp = gen_reg_rtx (SImode);
emit_insn (gen_mulsi3 (temp, operands[1], operands[2]));
- emit_insn (gen_<u>mulsi3_highpart (riscv_subword (operands[0], true),
+ emit_insn (gen_<su>mulsi3_highpart (riscv_subword (operands[0], true),
operands[1], operands[2]));
emit_insn (gen_movsi (riscv_subword (operands[0], false), temp));
DONE;
})
-(define_insn "<u>mulsi3_highpart"
+(define_insn "<su>mulsi3_highpart"
[(set (match_operand:SI 0 "register_operand" "=r")
(truncate:SI
(lshiftrt:DI
--
2.25.1
^ permalink raw reply [flat|nested] 3+ messages in thread
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2021-09-27 11:37 [PATCH] RISC-V: Pattern name fix mulm3_highpart -> smulm3_highpart Geng Qi
2021-09-28 23:44 ` Jim Wilson
2021-09-28 23:48 ` [PATCH] RISC-V: Pattern name fix mul*3_highpart -> smul*3_highpart Jim Wilson
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