* [committed] RISC-V: Fix wrong predicator for zero_extendsidi2_internal pattern
@ 2021-10-28 6:55 Kito Cheng
0 siblings, 0 replies; only message in thread
From: Kito Cheng @ 2021-10-28 6:55 UTC (permalink / raw)
To: gcc-patches, kito.cheng, jimw; +Cc: Kito Cheng
We're wrongly guard zero_extendsidi2_internal pattern both ZBA and ZBB,
only ZBA provide zero_extendsidi2 instruction.
gcc/ChangeLog
* config/riscv/riscv.md (zero_extendsidi2_internal): Allow ZBB
use this pattern.
---
gcc/config/riscv/riscv.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index dd4c24292f2..225e5b259c1 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1311,7 +1311,7 @@ (define_insn_and_split "*zero_extendsidi2_internal"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI
(match_operand:SI 1 "nonimmediate_operand" " r,m")))]
- "TARGET_64BIT && !(TARGET_ZBA || TARGET_ZBB)"
+ "TARGET_64BIT && !TARGET_ZBA"
"@
#
lwu\t%0,%1"
--
2.33.0
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2021-10-28 6:55 [committed] RISC-V: Fix wrong predicator for zero_extendsidi2_internal pattern Kito Cheng
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