[PATCH 3/3] RISC-V: Imply info and regs limit for zfinx extension

[jiawei <jiawei@iscas.ac.cn>]

Co-Authored-By: sinan <sinan@isrc.iscas.ac.cn>
---
 gcc/config/riscv/arch-canonicalize |  1 +
 gcc/config/riscv/constraints.md    |  3 ++-
 gcc/config/riscv/riscv.c           | 15 +++++++++++++--
 3 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize
index ea95a0693f3..3bb195416b4 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -36,6 +36,7 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
 #
 IMPLIED_EXT = {
   "d" : ["f"],
+  "zdinx" : ["zfinx"],
 }
 
 def arch_canonicalize(arch):
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index c87d5b796a5..a99b8ce277e 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -20,8 +20,9 @@
 ;; <http://www.gnu.org/licenses/>.
 
 ;; Register constraints
+;; Zfinx support need refuse FPR and use GPR
 
-(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
+(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : ((TARGET_ZFINX || TARGET_ZDINX) ? GR_REGS : NO_REGS)"
   "A floating-point register (if available).")
 
 (define_register_constraint "j" "SIBCALL_REGS"
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 6aef3d3a6cf..505435c3cee 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -4013,7 +4013,7 @@ riscv_compute_frame_info (void)
 
       /* Find out which FPRs we need to save.  This loop must iterate over
 	 the same space as its companion in riscv_for_each_saved_reg.  */
-      if (TARGET_HARD_FLOAT)
+      if (TARGET_HARD_FLOAT && !TARGET_ZFINX)
 	for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
 	  if (riscv_save_reg_p (regno))
 	    frame->fmask |= 1 << (regno - FP_REG_FIRST), num_f_saved++;
@@ -4790,6 +4790,13 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
 	!= call_used_or_fixed_reg_p (regno + i))
       return false;
 
+  /* Only use even registers in RV32 ZFINX */
+  if (!TARGET_64BIT && TARGET_ZDINX){
+    if (GET_MODE_CLASS (mode) == MODE_FLOAT &&
+	GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DFmode))
+      return !(regno & 1);
+  }
+
   return true;
 }
 
@@ -4981,7 +4988,7 @@ riscv_option_override (void)
     error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension");
 
   /* Likewise floating-point division and square root.  */
-  if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0)
+  if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & MASK_FDIV) == 0)
     target_flags |= MASK_FDIV;
 
   /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune
@@ -5027,6 +5034,10 @@ riscv_option_override (void)
   if (TARGET_RVE && riscv_abi != ABI_ILP32E)
     error ("rv32e requires ilp32e ABI");
 
+  // Zfinx require abi ilp32,ilp32e or lp64.
+  if (TARGET_ZFINX && riscv_abi != ABI_ILP32 && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E)
+  error ("z*inx requires ABI ilp32, ilp32e or lp64");
+
   /* We do not yet support ILP32 on RV64.  */
   if (BITS_PER_WORD != POINTER_SIZE)
     error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);
-- 
2.25.1