[PATCH 00/21] RISC-V: add gcc support for Scalar Cryptography v1.0.0-rc5

[PATCH 00/21] RISC-V: add gcc support for Scalar Cryptography v1.0.0-rc5

[siyu]

From: SiYu Wu <siyu@isrc.iscas.ac.cn>

This patch add gcc backend support for RISC-V Scalar Cryptography 
Extension (k-ext), including machine description, builtins defines and 
testcases for each k-ext's subset.

A note about Zbkx: The Zbkx should be implemented in bitmanip's Zbp, but 
since zbp is not included in the bitmanip spec v1.0, and crypto's v1.0 
release will earlier than bitmanip's next release, so for now we 
implementing it here.

SiYu Wu (19):
  [crypto]: add machine description for Zknd and Zkne
  [crypto]: add builtins for Zknd and Zkne
  [crypto]: add testcases for Zknd and Zkne
  [crypto]: add machine description for Zknh
  [crypto]: add builtins for Zknh
  [crypto]: add testcases for Zknh
  [crypto]: add machine description for Zksed
  [crypto]: add builtins for Zksed
  [crypto]: add testcases for Zksed
  [crypto]: add machine description for Zksh
  [crypto]: add builtins for Zksh
  [crypto]: add testcases for Zksh
  [crypto]: add option defines for Zkr and Zkt
  [crypto]: add option defines for Zbkb, Zbkc and Zbkx
  [crypto]: add implied defines of Zk, Zkn and Zks
  change z* subset assert to allow "zk"
  [crypto]: add machine description for Zbkx
  [crypto]: add builtins for Zbkx
  [crypto]: add testcases for Zbkx

jiawei (1):
  Fix attribute bugs due to zicsr/zifencei

linsinan1995 (1):
  Fix riscv_expand_block_move

 gcc/common/config/riscv/riscv-common.c        |  39 ++-
 gcc/config/riscv/arch-canonicalize            |  18 +-
 gcc/config/riscv/crypto.md                    | 319 ++++++++++++++++++
 gcc/config/riscv/riscv-builtins-crypto.def    |  76 +++++
 gcc/config/riscv/riscv-builtins.c             |  25 ++
 gcc/config/riscv/riscv-ftypes.def             |   6 +
 gcc/config/riscv/riscv-opts.h                 |  21 ++
 gcc/config/riscv/riscv.c                      |   2 +-
 gcc/config/riscv/riscv.md                     |   4 +-
 gcc/config/riscv/riscv.opt                    |   3 +
 gcc/testsuite/gcc.target/riscv/Zbkx.c         |  17 +
 gcc/testsuite/gcc.target/riscv/Zknd-aes-01.c  |  15 +
 gcc/testsuite/gcc.target/riscv/Zknd-aes-02.c  |  21 ++
 gcc/testsuite/gcc.target/riscv/Zkne-aes-01.c  |  15 +
 gcc/testsuite/gcc.target/riscv/Zkne-aes-02.c  |  27 ++
 gcc/testsuite/gcc.target/riscv/Zknh-sha256.c  |  27 ++
 .../gcc.target/riscv/Zknh-sha512-01.c         |  40 +++
 .../gcc.target/riscv/Zknh-sha512-02.c         |  28 ++
 gcc/testsuite/gcc.target/riscv/Zksed-sm4.c    |  17 +
 gcc/testsuite/gcc.target/riscv/Zksh-sm3.c     |  15 +
 20 files changed, 730 insertions(+), 5 deletions(-)
 create mode 100644 gcc/config/riscv/crypto.md
 create mode 100644 gcc/config/riscv/riscv-builtins-crypto.def
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zbkx.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zknd-aes-01.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zknd-aes-02.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zkne-aes-01.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zkne-aes-02.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zknh-sha256.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zknh-sha512-01.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zknh-sha512-02.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zksed-sm4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zksh-sm3.c

-- 
2.25.1

[PATCH 01/21] Fix riscv_expand_block_move

[siyu]

From: linsinan1995 <47880367+linsinan1995@users.noreply.github.com>

---
 gcc/config/riscv/riscv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 6aef3d3a6cf..0529b6d60cd 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -3491,7 +3491,7 @@ riscv_block_move_loop (rtx dest, rtx src, unsigned HOST_WIDE_INT length,
 bool
 riscv_expand_block_move (rtx dest, rtx src, rtx length)
 {
-  if (CONST_INT_P (length))
+  if (CONST_INT_P (length) && INTVAL (length) >= 0)
     {
       unsigned HOST_WIDE_INT hwi_length = UINTVAL (length);
       unsigned HOST_WIDE_INT factor, align;
-- 
2.25.1

[PATCH 02/21] Fix attribute bugs due to zicsr/zifencei

[siyu]

From: jiawei <jiawei@iscas.ac.cn>

---
 gcc/config/riscv/arch-canonicalize | 2 ++
 gcc/config/riscv/riscv.md          | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize
index c7df3c8a313..e2feb7e85cd 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -36,6 +36,8 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
 #
 IMPLIED_EXT = {
   "d" : ["f"],
+  "f" : ["zicsr"],
+  "f" : ["zifencei"],
 }
 
 def arch_canonicalize(arch):
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 225e5b259c1..1a786f31258 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1812,7 +1812,7 @@ (define_expand "clear_cache"
 
 (define_insn "fence"
   [(unspec_volatile [(const_int 0)] UNSPECV_FENCE)]
-  ""
+  "TARGET_ZIFENCEI"
   "%|fence%-")
 
 (define_insn "fence_i"
-- 
2.25.1

[PATCH 03/21] [crypto]: add machine description for Zknd and Zkne

[siyu]

From: SiYu Wu <siyu@isrc.iscas.ac.cn>

---
 gcc/common/config/riscv/riscv-common.c |   6 ++
 gcc/config/riscv/crypto.md             | 129 +++++++++++++++++++++++++
 gcc/config/riscv/riscv-opts.h          |   6 ++
 gcc/config/riscv/riscv.md              |   2 +
 gcc/config/riscv/riscv.opt             |   3 +
 5 files changed, 146 insertions(+)
 create mode 100644 gcc/config/riscv/crypto.md

diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
index 37b6ea80086..1e81847ee5c 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -106,6 +106,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
   {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zkne",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zknd",  ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -916,6 +919,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"zbc",    &gcc_options::x_riscv_zb_subext, MASK_ZBC},
   {"zbs",    &gcc_options::x_riscv_zb_subext, MASK_ZBS},
 
+  {"zknd",   &gcc_options::x_riscv_zk_subext, MASK_ZKND},
+  {"zkne",   &gcc_options::x_riscv_zk_subext, MASK_ZKNE},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
new file mode 100644
index 00000000000..170be7ff56c
--- /dev/null
+++ b/gcc/config/riscv/crypto.md
@@ -0,0 +1,129 @@
+;; Machine description for K extension.
+;; Copyright (C) 2021 Free Software Foundation, Inc.
+;; Contributed by SiYu Wu (siyu@isrc.iscas.ac.cn).
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+
+(define_c_enum "unspec" [
+  ;; Crypto extension unspecs.
+  UNSPEC_AES_DS
+  UNSPEC_AES_DSM
+  UNSPEC_AES_ES
+  UNSPEC_AES_ESM
+  UNSPEC_AES_IM
+  UNSPEC_AES_KS1
+  UNSPEC_AES_KS2
+])
+
+
+;; Zkne&Zknd - AES (RV32)
+
+(define_insn "riscv_aes32dsi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")
+                   (match_operand:SI 3 "immediate_operand" "")]
+                   UNSPEC_AES_DS))]
+  "TARGET_ZKND && !TARGET_64BIT"
+  "aes32dsi\t%0,%1,%2,%3")
+
+(define_insn "riscv_aes32dsmi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")
+                   (match_operand:SI 3 "immediate_operand" "")]
+                   UNSPEC_AES_DSM))]
+  "TARGET_ZKND && !TARGET_64BIT"
+  "aes32dsmi\t%0,%1,%2,%3")
+
+(define_insn "riscv_aes32esi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "")
+                   (match_operand:SI 3 "immediate_operand" "")]
+                   UNSPEC_AES_ES))]
+  "TARGET_ZKNE && !TARGET_64BIT"
+  "aes32esi\t%0,%1,%2,%3")
+
+(define_insn "riscv_aes32esmi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")
+                   (match_operand:SI 3 "immediate_operand" "")]
+                   UNSPEC_AES_ESM))]
+  "TARGET_ZKNE && !TARGET_64BIT"
+  "aes32esmi\t%0,%1,%2,%3")
+
+
+;; Zkne&Zknd - AES (RV64)
+
+(define_insn "riscv_aes64ds"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+                   (match_operand:DI 2 "register_operand" "r")]
+                   UNSPEC_AES_DS))]
+  "TARGET_ZKND && TARGET_64BIT"
+  "aes64ds\t%0,%1,%2")
+
+(define_insn "riscv_aes64dsm"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+                   (match_operand:DI 2 "register_operand" "r")]
+                   UNSPEC_AES_DSM))]
+  "TARGET_ZKND && TARGET_64BIT"
+  "aes64dsm\t%0,%1,%2")
+
+(define_insn "riscv_aes64es"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+                   (match_operand:DI 2 "register_operand" "r")]
+                   UNSPEC_AES_ES))]
+  "TARGET_ZKNE && TARGET_64BIT"
+  "aes64es\t%0,%1,%2")
+
+(define_insn "riscv_aes64esm"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+                   (match_operand:DI 2 "register_operand" "r")]
+                   UNSPEC_AES_ESM))]
+  "TARGET_ZKNE && TARGET_64BIT"
+  "aes64esm\t%0,%1,%2")
+
+(define_insn "riscv_aes64im"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+                   UNSPEC_AES_IM))]
+  "TARGET_ZKND && TARGET_64BIT"
+  "aes64im\t%0,%1")
+
+(define_insn "riscv_aes64ks1i"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+                   (match_operand:DI 2 "immediate_operand" "")]
+                   UNSPEC_AES_KS1))]
+  "TARGET_ZKNE && TARGET_64BIT"
+  "aes64ks1i\t%0,%1,%2")
+
+(define_insn "riscv_aes64ks2"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+                   (match_operand:DI 2 "register_operand" "r")]
+                   UNSPEC_AES_KS2))]
+  "TARGET_ZKNE && TARGET_64BIT"
+  "aes64ks2\t%0,%1,%2")
+
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 2efc4b80f1f..b0226335c4f 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -83,4 +83,10 @@ enum stack_protector_guard {
 #define TARGET_ZBC    ((riscv_zb_subext & MASK_ZBC) != 0)
 #define TARGET_ZBS    ((riscv_zb_subext & MASK_ZBS) != 0)
 
+#define MASK_ZKNE     (1 << 5)
+#define MASK_ZKND     (1 << 6)
+
+#define TARGET_ZKNE   ((riscv_zk_subext & MASK_ZKNE) != 0)
+#define TARGET_ZKND   ((riscv_zk_subext & MASK_ZKND) != 0)
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 1a786f31258..f95505d07da 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2765,6 +2765,8 @@ (define_insn "stack_tie<mode>"
   [(set_attr "length" "0")]
 )
 
+(include "crypto.md")
+
 ;; This fixes a failure with gcc.c-torture/execute/pr64242.c at -O2 for a
 ;; 32-bit target when using -mtune=sifive-7-series.  The first sched pass
 ;; runs before register elimination, and we have a non-obvious dependency
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 15bf89e17c2..617000975bf 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -198,6 +198,9 @@ int riscv_zi_subext
 TargetVariable
 int riscv_zb_subext
 
+TargetVariable
+int riscv_zk_subext
+
 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):
-- 
2.25.1

[PATCH 04/21] [crypto]: add builtins for Zknd and Zkne

[siyu]

From: SiYu Wu <siyu@isrc.iscas.ac.cn>

---
 gcc/config/riscv/riscv-builtins-crypto.def | 34 ++++++++++++++++++++++
 gcc/config/riscv/riscv-builtins.c          | 15 ++++++++++
 gcc/config/riscv/riscv-ftypes.def          |  3 ++
 3 files changed, 52 insertions(+)
 create mode 100644 gcc/config/riscv/riscv-builtins-crypto.def

diff --git a/gcc/config/riscv/riscv-builtins-crypto.def b/gcc/config/riscv/riscv-builtins-crypto.def
new file mode 100644
index 00000000000..13a2efe2e2b
--- /dev/null
+++ b/gcc/config/riscv/riscv-builtins-crypto.def
@@ -0,0 +1,34 @@
+/* Builtin definitions for K extension
+   Copyright (C) 2021 Free Software Foundation, Inc.
+   Contributed by SiYu Wu (siyu@isrc.iscas.ac.cn).
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+// Zkne&Zknd - AES (RV32)
+DIRECT_BUILTIN (aes32dsi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zknd32),
+DIRECT_BUILTIN (aes32dsmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zknd32),
+DIRECT_BUILTIN (aes32esi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32),
+DIRECT_BUILTIN (aes32esmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32),
+
+// Zkne&Zknd - AES (RV64)
+DIRECT_BUILTIN (aes64ds, RISCV_DI_FTYPE_DI_DI, crypto_zknd64),
+DIRECT_BUILTIN (aes64dsm, RISCV_DI_FTYPE_DI_DI, crypto_zknd64),
+DIRECT_BUILTIN (aes64es, RISCV_DI_FTYPE_DI_DI, crypto_zkne64),
+DIRECT_BUILTIN (aes64esm, RISCV_DI_FTYPE_DI_DI, crypto_zkne64),
+DIRECT_BUILTIN (aes64im, RISCV_DI_FTYPE_DI, crypto_zknd64),
+DIRECT_BUILTIN (aes64ks1i, RISCV_DI_FTYPE_DI_SI, crypto_zkne64),
+DIRECT_BUILTIN (aes64ks2, RISCV_DI_FTYPE_DI_DI, crypto_zkne64),
diff --git a/gcc/config/riscv/riscv-builtins.c b/gcc/config/riscv/riscv-builtins.c
index 97b1480a15e..937a80ac483 100644
--- a/gcc/config/riscv/riscv-builtins.c
+++ b/gcc/config/riscv/riscv-builtins.c
@@ -40,6 +40,8 @@ along with GCC; see the file COPYING3.  If not see
 /* Macros to create an enumeration identifier for a function prototype.  */
 #define RISCV_FTYPE_NAME0(A) RISCV_##A##_FTYPE
 #define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B
+#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C
+#define RISCV_FTYPE_NAME3(A, B, C, D) RISCV_##A##_FTYPE_##B##_##C##_##D
 
 /* Classifies the prototype of a built-in function.  */
 enum riscv_function_type {
@@ -87,6 +89,11 @@ struct riscv_builtin_description {
 
 AVAIL (hard_float, TARGET_HARD_FLOAT)
 
+AVAIL (crypto_zknd32, TARGET_ZKND && !TARGET_64BIT)
+AVAIL (crypto_zknd64, TARGET_ZKND && TARGET_64BIT)
+AVAIL (crypto_zkne32, TARGET_ZKNE && !TARGET_64BIT)
+AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT)
+
 /* Construct a riscv_builtin_description from the given arguments.
 
    INSN is the name of the associated instruction pattern, without the
@@ -119,6 +126,8 @@ AVAIL (hard_float, TARGET_HARD_FLOAT)
 /* Argument types.  */
 #define RISCV_ATYPE_VOID void_type_node
 #define RISCV_ATYPE_USI unsigned_intSI_type_node
+#define RISCV_ATYPE_SI intSI_type_node
+#define RISCV_ATYPE_DI intDI_type_node
 
 /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
    their associated RISCV_ATYPEs.  */
@@ -126,8 +135,14 @@ AVAIL (hard_float, TARGET_HARD_FLOAT)
   RISCV_ATYPE_##A
 #define RISCV_FTYPE_ATYPES1(A, B) \
   RISCV_ATYPE_##A, RISCV_ATYPE_##B
+#define RISCV_FTYPE_ATYPES2(A, B, C) \
+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C
+#define RISCV_FTYPE_ATYPES3(A, B, C, D) \
+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D
 
 static const struct riscv_builtin_description riscv_builtins[] = {
+  #include "riscv-builtins-crypto.def"
+
   DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
   DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float)
 };
diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
index b19b731bdf2..e5bc5ac28c9 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -28,3 +28,6 @@ along with GCC; see the file COPYING3.  If not see
 
 DEF_RISCV_FTYPE (0, (USI))
 DEF_RISCV_FTYPE (1, (VOID, USI))
+DEF_RISCV_FTYPE (2, (DI, DI, DI))
+DEF_RISCV_FTYPE (2, (DI, DI, SI))
+DEF_RISCV_FTYPE (3, (SI, SI, SI, SI))
-- 
2.25.1

[PATCH 05/21] [crypto]: add testcases for Zknd and Zkne

[siyu]

From: SiYu Wu <siyu@isrc.iscas.ac.cn>

Co-authored-by: Shihua Liao <shihua@iscas.ac.cn>
---
 gcc/testsuite/gcc.target/riscv/Zknd-aes-01.c | 15 +++++++++++
 gcc/testsuite/gcc.target/riscv/Zknd-aes-02.c | 21 +++++++++++++++
 gcc/testsuite/gcc.target/riscv/Zkne-aes-01.c | 15 +++++++++++
 gcc/testsuite/gcc.target/riscv/Zkne-aes-02.c | 27 ++++++++++++++++++++
 4 files changed, 78 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zknd-aes-01.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zknd-aes-02.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zkne-aes-01.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zkne-aes-02.c

diff --git a/gcc/testsuite/gcc.target/riscv/Zknd-aes-01.c b/gcc/testsuite/gcc.target/riscv/Zknd-aes-01.c
new file mode 100644
index 00000000000..87d0b490476
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/Zknd-aes-01.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zknd -mabi=ilp32 -O2" } */
+
+int foo1(int rs1, int rs2)
+{
+    return __builtin_riscv_aes32dsi(rs1, rs2, 1);
+}
+
+int foo2(int rs1, int rs2)
+{
+    return __builtin_riscv_aes32dsmi(rs1, rs2, 0);
+}
+
+/* { dg-final { scan-assembler-times "aes32dsi" 1 } } */
+/* { dg-final { scan-assembler-times "aes32dsmi" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/Zknd-aes-02.c b/gcc/testsuite/gcc.target/riscv/Zknd-aes-02.c
new file mode 100644
index 00000000000..3abe8342f9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/Zknd-aes-02.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zknd -mabi=lp64 -O2" } */
+
+long foo1(long rs1, long rs2)
+{
+    return __builtin_riscv_aes64ds(rs1, rs2);
+}
+
+long foo2(long rs1, long rs2)
+{
+    return __builtin_riscv_aes64dsm(rs1, rs2);
+}
+
+long foo3(long rs1)
+{
+    return __builtin_riscv_aes64im(rs1);
+}
+
+/* { dg-final { scan-assembler-times "aes64ds" 2 } } */
+/* { dg-final { scan-assembler-times "aes64dsm" 1 } } */
+/* { dg-final { scan-assembler-times "aes64im" 1 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/Zkne-aes-01.c b/gcc/testsuite/gcc.target/riscv/Zkne-aes-01.c
new file mode 100644
index 00000000000..06848166f07
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/Zkne-aes-01.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zkne -mabi=ilp32 -O2" } */
+
+int foo1(int rs1, int rs2)
+{
+    return __builtin_riscv_aes32esi(rs1, rs2, 1);
+}
+
+int foo2(int rs1, int rs2)
+{
+    return __builtin_riscv_aes32esmi(rs1, rs2, 1);
+}
+
+/* { dg-final { scan-assembler-times "aes32esi" 1 } } */
+/* { dg-final { scan-assembler-times "aes32esmi" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/Zkne-aes-02.c b/gcc/testsuite/gcc.target/riscv/Zkne-aes-02.c
new file mode 100644
index 00000000000..8c8bf43b680
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/Zkne-aes-02.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zkne -mabi=lp64 -O2" } */
+
+long foo1(long rs1, long rs2)
+{
+    return __builtin_riscv_aes64es(rs1, rs2);
+}
+
+long foo2(long rs1, long rs2)
+{
+    return __builtin_riscv_aes64esm(rs1, rs2);
+}
+
+long foo3(long rs1)
+{
+    return __builtin_riscv_aes64ks1i(rs1, 1);
+}
+
+long foo4(long rs1, long rs2)
+{
+    return __builtin_riscv_aes64ks2(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "aes64es" 2 } } */
+/* { dg-final { scan-assembler-times "aes64esm" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks1i" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks2" 1 } } */
\ No newline at end of file
-- 
2.25.1

[PATCH 06/21] [crypto]: add machine description for Zknh

[siyu]

From: SiYu Wu <siyu@isrc.iscas.ac.cn>

---
 gcc/common/config/riscv/riscv-common.c |   2 +
 gcc/config/riscv/crypto.md             | 123 +++++++++++++++++++++++++
 gcc/config/riscv/riscv-opts.h          |   2 +
 3 files changed, 127 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
index 1e81847ee5c..c0432c93dd3 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -108,6 +108,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
 
   {"zkne",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zknd",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zknh",  ISA_SPEC_CLASS_NONE, 1, 0},
 
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
@@ -921,6 +922,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
 
   {"zknd",   &gcc_options::x_riscv_zk_subext, MASK_ZKND},
   {"zkne",   &gcc_options::x_riscv_zk_subext, MASK_ZKNE},
+  {"zknh",   &gcc_options::x_riscv_zk_subext, MASK_ZKNH},
 
   {NULL, NULL, 0}
 };
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 170be7ff56c..243a77ef528 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -28,6 +28,16 @@ (define_c_enum "unspec" [
   UNSPEC_AES_IM
   UNSPEC_AES_KS1
   UNSPEC_AES_KS2
+  UNSPEC_SHA_256_SIG0
+  UNSPEC_SHA_256_SIG1
+  UNSPEC_SHA_256_SUM0
+  UNSPEC_SHA_256_SUM1
+  UNSPEC_SHA_512_SIG0
+  UNSPEC_SHA_512_SIG0_2
+  UNSPEC_SHA_512_SIG1
+  UNSPEC_SHA_512_SIG1_2
+  UNSPEC_SHA_512_SUM0
+  UNSPEC_SHA_512_SUM1
 ])
 
 
@@ -127,3 +137,116 @@ (define_insn "riscv_aes64ks2"
   "TARGET_ZKNE && TARGET_64BIT"
   "aes64ks2\t%0,%1,%2")
 
+
+;; Zknh - SHA256
+
+(define_insn "riscv_sha256sig0_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SHA_256_SIG0))]
+  "TARGET_ZKNH"
+  "sha256sig0\t%0,%1")
+
+(define_insn "riscv_sha256sig1_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SHA_256_SIG1))]
+  "TARGET_ZKNH"
+  "sha256sig1\t%0,%1")
+
+(define_insn "riscv_sha256sum0_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SHA_256_SUM0))]
+  "TARGET_ZKNH"
+  "sha256sum0\t%0,%1")
+
+(define_insn "riscv_sha256sum1_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SHA_256_SUM1))]
+  "TARGET_ZKNH"
+  "sha256sum1\t%0,%1")
+
+
+;; Zknh - SHA512 (RV32)
+
+(define_insn "riscv_sha512sig0h"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG0))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig0h\t%0,%1,%2")
+
+(define_insn "riscv_sha512sig0l"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG0_2))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig0l\t%0,%1,%2")
+
+(define_insn "riscv_sha512sig1h"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG1))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig1h\t%0,%1,%2")
+
+(define_insn "riscv_sha512sig1l"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG1_2))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig1l\t%0,%1,%2")
+
+(define_insn "riscv_sha512sum0r"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SUM0))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sum0r\t%0,%1,%2")
+
+(define_insn "riscv_sha512sum1r"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SUM1))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sum1r\t%0,%1,%2")
+
+
+;; Zknh - SHA512 (RV64)
+
+(define_insn "riscv_sha512sig0"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG0))]
+  "TARGET_ZKNH && TARGET_64BIT"
+  "sha512sig0\t%0,%1")
+
+(define_insn "riscv_sha512sig1"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG1))]
+  "TARGET_ZKNH && TARGET_64BIT"
+  "sha512sig1\t%0,%1")
+
+(define_insn "riscv_sha512sum0"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+                   UNSPEC_SHA_512_SUM0))]
+  "TARGET_ZKNH && TARGET_64BIT"
+  "sha512sum0\t%0,%1")
+
+(define_insn "riscv_sha512sum1"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+                   UNSPEC_SHA_512_SUM1))]
+  "TARGET_ZKNH && TARGET_64BIT"
+  "sha512sum1\t%0,%1")
+
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index b0226335c4f..9d8e560c4ba 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -85,8 +85,10 @@ enum stack_protector_guard {
 
 #define MASK_ZKNE     (1 << 5)
 #define MASK_ZKND     (1 << 6)
+#define MASK_ZKNH     (1 << 7)
 
 #define TARGET_ZKNE   ((riscv_zk_subext & MASK_ZKNE) != 0)
 #define TARGET_ZKND   ((riscv_zk_subext & MASK_ZKND) != 0)
+#define TARGET_ZKNH   ((riscv_zk_subext & MASK_ZKNH) != 0)
 
 #endif /* ! GCC_RISCV_OPTS_H */
-- 
2.25.1

[PATCH 07/21] [crypto]: add builtins for Zknh

[siyu]

From: SiYu Wu <siyu@isrc.iscas.ac.cn>

---
 gcc/config/riscv/riscv-builtins-crypto.def | 24 ++++++++++++++++++++++
 gcc/config/riscv/riscv-builtins.c          |  2 ++
 gcc/config/riscv/riscv-ftypes.def          |  3 +++
 3 files changed, 29 insertions(+)

diff --git a/gcc/config/riscv/riscv-builtins-crypto.def b/gcc/config/riscv/riscv-builtins-crypto.def
index 13a2efe2e2b..ca008929927 100644
--- a/gcc/config/riscv/riscv-builtins-crypto.def
+++ b/gcc/config/riscv/riscv-builtins-crypto.def
@@ -32,3 +32,27 @@ DIRECT_BUILTIN (aes64esm, RISCV_DI_FTYPE_DI_DI, crypto_zkne64),
 DIRECT_BUILTIN (aes64im, RISCV_DI_FTYPE_DI, crypto_zknd64),
 DIRECT_BUILTIN (aes64ks1i, RISCV_DI_FTYPE_DI_SI, crypto_zkne64),
 DIRECT_BUILTIN (aes64ks2, RISCV_DI_FTYPE_DI_DI, crypto_zkne64),
+
+// Zknh - SHA256
+RISCV_BUILTIN (sha256sig0_si, "sha256sig0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sig0_di, "sha256sig0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64),
+RISCV_BUILTIN (sha256sig1_si, "sha256sig1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sig1_di, "sha256sig1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64),
+RISCV_BUILTIN (sha256sum0_si, "sha256sum0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sum0_di, "sha256sum0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64),
+RISCV_BUILTIN (sha256sum1_si, "sha256sum1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sum1_di, "sha256sum1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64),
+
+// Zknh - SHA512 (RV32)
+DIRECT_BUILTIN (sha512sig0h, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sig0l, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sig1h, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sig1l, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sum0r, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sum1r, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+
+// Zknh - SHA512 (RV64)
+DIRECT_BUILTIN (sha512sig0, RISCV_DI_FTYPE_DI, crypto_zknh64),
+DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI, crypto_zknh64),
+DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI, crypto_zknh64),
+DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI, crypto_zknh64),
diff --git a/gcc/config/riscv/riscv-builtins.c b/gcc/config/riscv/riscv-builtins.c
index 937a80ac483..597f8ed60cb 100644
--- a/gcc/config/riscv/riscv-builtins.c
+++ b/gcc/config/riscv/riscv-builtins.c
@@ -93,6 +93,8 @@ AVAIL (crypto_zknd32, TARGET_ZKND && !TARGET_64BIT)
 AVAIL (crypto_zknd64, TARGET_ZKND && TARGET_64BIT)
 AVAIL (crypto_zkne32, TARGET_ZKNE && !TARGET_64BIT)
 AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT)
+AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT)
+AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT)
 
 /* Construct a riscv_builtin_description from the given arguments.
 
diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
index e5bc5ac28c9..87b814135d5 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -28,6 +28,9 @@ along with GCC; see the file COPYING3.  If not see
 
 DEF_RISCV_FTYPE (0, (USI))
 DEF_RISCV_FTYPE (1, (VOID, USI))
+DEF_RISCV_FTYPE (1, (SI, SI))
+DEF_RISCV_FTYPE (1, (DI, DI))
+DEF_RISCV_FTYPE (2, (SI, SI, SI))
 DEF_RISCV_FTYPE (2, (DI, DI, DI))
 DEF_RISCV_FTYPE (2, (DI, DI, SI))
 DEF_RISCV_FTYPE (3, (SI, SI, SI, SI))
-- 
2.25.1

[PATCH 08/21] [crypto]: add testcases for Zknh

[siyu]

From: SiYu Wu <siyu@isrc.iscas.ac.cn>

Co-authored-by: Shihua Liao <shihua@iscas.ac.cn>
---
 gcc/testsuite/gcc.target/riscv/Zknh-sha256.c  | 27 +++++++++++++
 .../gcc.target/riscv/Zknh-sha512-01.c         | 40 +++++++++++++++++++
 .../gcc.target/riscv/Zknh-sha512-02.c         | 28 +++++++++++++
 3 files changed, 95 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zknh-sha256.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zknh-sha512-01.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zknh-sha512-02.c

diff --git a/gcc/testsuite/gcc.target/riscv/Zknh-sha256.c b/gcc/testsuite/gcc.target/riscv/Zknh-sha256.c
new file mode 100644
index 00000000000..1c1cb7be5d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/Zknh-sha256.c
@@ -0,0 +1,27 @@
+/* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-options "-march=rv64gc_zknh -mabi=lp64 -O2" } */
+
+long foo1(long rs1)
+{
+    return __builtin_riscv_sha256sig0(rs1);
+}
+
+long foo2(long rs1)
+{
+    return __builtin_riscv_sha256sig1(rs1);
+}
+
+long foo3(long rs1)
+{
+    return __builtin_riscv_sha256sum0(rs1);
+}
+
+long foo4(long rs1)
+{
+    return __builtin_riscv_sha256sum1(rs1);
+}
+
+/* { dg-final { scan-assembler-times "sha256sig0" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sig1" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sum0" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sum1" 1 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/Zknh-sha512-01.c b/gcc/testsuite/gcc.target/riscv/Zknh-sha512-01.c
new file mode 100644
index 00000000000..ef1f6dafe60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/Zknh-sha512-01.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zknh -mabi=ilp32 -O2" } */
+
+int foo1(int rs1, int rs2)
+{
+    return __builtin_riscv_sha512sig0h(rs1, rs2);
+}
+
+int foo2(int rs1, int rs2)
+{
+    return __builtin_riscv_sha512sig0l(rs1, rs2);
+}
+
+int foo3(int rs1, int rs2)
+{
+    return __builtin_riscv_sha512sig1h(rs1, rs2);
+}
+
+int foo4(int rs1, int rs2)
+{
+    return __builtin_riscv_sha512sig1l(rs1, rs2);
+}
+
+int foo5(int rs1, int rs2)
+{
+    return __builtin_riscv_sha512sum0r(rs1, rs2);
+}
+
+int foo6(int rs1, int rs2)
+{
+    return __builtin_riscv_sha512sum1r(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "sha512sig0h" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig0l" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1h" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1l" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum0r" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum1r" 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/Zknh-sha512-02.c b/gcc/testsuite/gcc.target/riscv/Zknh-sha512-02.c
new file mode 100644
index 00000000000..f25cbcfb75b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/Zknh-sha512-02.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zknh -mabi=lp64 -O2" } */
+
+long foo1(long rs1)
+{
+    return __builtin_riscv_sha512sig0(rs1);
+}
+
+long foo2(long rs1)
+{
+    return __builtin_riscv_sha512sig1(rs1);
+}
+
+
+long foo3(long rs1)
+{
+    return __builtin_riscv_sha512sum0(rs1);
+}
+
+long foo4(long rs1)
+{
+    return __builtin_riscv_sha512sum1(rs1);
+}
+
+/* { dg-final { scan-assembler-times "sha512sig0" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum0" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum1" 1 } } */
\ No newline at end of file
-- 
2.25.1

[PATCH 09/21] [crypto]: add machine description for Zksed

[siyu]

From: SiYu Wu <siyu@isrc.iscas.ac.cn>

---
 gcc/common/config/riscv/riscv-common.c |  2 ++
 gcc/config/riscv/crypto.md             | 21 +++++++++++++++++++++
 gcc/config/riscv/riscv-opts.h          |  2 ++
 3 files changed, 25 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
index c0432c93dd3..d4d61bd765d 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -109,6 +109,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
   {"zkne",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zknd",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zknh",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zksed", ISA_SPEC_CLASS_NONE, 1, 0},
 
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
@@ -923,6 +924,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"zknd",   &gcc_options::x_riscv_zk_subext, MASK_ZKND},
   {"zkne",   &gcc_options::x_riscv_zk_subext, MASK_ZKNE},
   {"zknh",   &gcc_options::x_riscv_zk_subext, MASK_ZKNH},
+  {"zksed",  &gcc_options::x_riscv_zk_subext, MASK_ZKSED},
 
   {NULL, NULL, 0}
 };
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 243a77ef528..ac0107f43c2 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -38,6 +38,8 @@ (define_c_enum "unspec" [
   UNSPEC_SHA_512_SIG1_2
   UNSPEC_SHA_512_SUM0
   UNSPEC_SHA_512_SUM1
+  UNSPEC_SM4_ED
+  UNSPEC_SM4_KS
 ])
 
 
@@ -250,3 +252,22 @@ (define_insn "riscv_sha512sum1"
   "TARGET_ZKNH && TARGET_64BIT"
   "sha512sum1\t%0,%1")
 
+
+;; Zksed - SM4
+
+(define_insn "riscv_sm4ed_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:SI 2 "immediate_operand" "")]
+                  UNSPEC_SM4_ED))]
+  "TARGET_ZKSED"
+  "sm4ed\t%0,%1,%2")
+
+(define_insn "riscv_sm4ks_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:SI 2 "immediate_operand" "")]
+                  UNSPEC_SM4_KS))]
+  "TARGET_ZKSED"
+  "sm4ks\t%0,%1,%2")
+
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 9d8e560c4ba..6ad89db42f5 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -86,9 +86,11 @@ enum stack_protector_guard {
 #define MASK_ZKNE     (1 << 5)
 #define MASK_ZKND     (1 << 6)
 #define MASK_ZKNH     (1 << 7)
+#define MASK_ZKSED    (1 << 9)
 
 #define TARGET_ZKNE   ((riscv_zk_subext & MASK_ZKNE) != 0)
 #define TARGET_ZKND   ((riscv_zk_subext & MASK_ZKND) != 0)
 #define TARGET_ZKNH   ((riscv_zk_subext & MASK_ZKNH) != 0)
+#define TARGET_ZKSED  ((riscv_zk_subext & MASK_ZKSED) != 0)
 
 #endif /* ! GCC_RISCV_OPTS_H */
-- 
2.25.1

[PATCH 10/21] [crypto]: add builtins for Zksed

[siyu]

From: SiYu Wu <siyu@isrc.iscas.ac.cn>

---
 gcc/config/riscv/riscv-builtins-crypto.def | 6 ++++++
 gcc/config/riscv/riscv-builtins.c          | 3 +++
 2 files changed, 9 insertions(+)

diff --git a/gcc/config/riscv/riscv-builtins-crypto.def b/gcc/config/riscv/riscv-builtins-crypto.def
index ca008929927..47bfff80f2e 100644
--- a/gcc/config/riscv/riscv-builtins-crypto.def
+++ b/gcc/config/riscv/riscv-builtins-crypto.def
@@ -56,3 +56,9 @@ DIRECT_BUILTIN (sha512sig0, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI, crypto_zknh64),
+
+// Zksed - SM4
+RISCV_BUILTIN (sm4ed_si, "sm4ed", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zksed32),
+RISCV_BUILTIN (sm4ed_di, "sm4ed", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_SI, crypto_zksed64),
+RISCV_BUILTIN (sm4ks_si, "sm4ks", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zksed32),
+RISCV_BUILTIN (sm4ks_di, "sm4ks", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_SI, crypto_zksed64),
diff --git a/gcc/config/riscv/riscv-builtins.c b/gcc/config/riscv/riscv-builtins.c
index 597f8ed60cb..1eed8d3fcb3 100644
--- a/gcc/config/riscv/riscv-builtins.c
+++ b/gcc/config/riscv/riscv-builtins.c
@@ -96,6 +96,9 @@ AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT)
 AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT)
 AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT)
 
+AVAIL (crypto_zksed32, TARGET_ZKSED && !TARGET_64BIT)
+AVAIL (crypto_zksed64, TARGET_ZKSED && TARGET_64BIT)
+
 /* Construct a riscv_builtin_description from the given arguments.
 
    INSN is the name of the associated instruction pattern, without the
-- 
2.25.1

[PATCH 11/21] [crypto]: add testcases for Zksed

[siyu]

From: SiYu Wu <siyu@isrc.iscas.ac.cn>

Co-authored-by: Shihua Liao <shihua@iscas.ac.cn>
---
 gcc/testsuite/gcc.target/riscv/Zksed-sm4.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zksed-sm4.c

diff --git a/gcc/testsuite/gcc.target/riscv/Zksed-sm4.c b/gcc/testsuite/gcc.target/riscv/Zksed-sm4.c
new file mode 100644
index 00000000000..f7bb3e8dc0b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/Zksed-sm4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zksed -mabi=lp64 -O2" } */
+
+long foo1(long rs1)
+{
+    return __builtin_riscv_sm4ed(rs1, 1);
+}
+
+long foo2(long rs1)
+{
+    return __builtin_riscv_sm4ks(rs1, 2);
+}
+
+
+
+/* { dg-final { scan-assembler-times "sm4ed" 1 } } */
+/* { dg-final { scan-assembler-times "sm4ks" 1 } } */
\ No newline at end of file
-- 
2.25.1

[PATCH 12/21] [crypto]: add machine description for Zksh

[siyu]

From: SiYu Wu <siyu@isrc.iscas.ac.cn>

---
 gcc/common/config/riscv/riscv-common.c |  2 ++
 gcc/config/riscv/crypto.md             | 19 +++++++++++++++++++
 gcc/config/riscv/riscv-opts.h          |  2 ++
 3 files changed, 23 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
index d4d61bd765d..8f4f4472690 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -110,6 +110,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
   {"zknd",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zknh",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zksed", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zksh",  ISA_SPEC_CLASS_NONE, 1, 0},
 
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
@@ -925,6 +926,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"zkne",   &gcc_options::x_riscv_zk_subext, MASK_ZKNE},
   {"zknh",   &gcc_options::x_riscv_zk_subext, MASK_ZKNH},
   {"zksed",  &gcc_options::x_riscv_zk_subext, MASK_ZKSED},
+  {"zksh",   &gcc_options::x_riscv_zk_subext, MASK_ZKSH},
 
   {NULL, NULL, 0}
 };
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index ac0107f43c2..79ca2ec2696 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -38,6 +38,8 @@ (define_c_enum "unspec" [
   UNSPEC_SHA_512_SIG1_2
   UNSPEC_SHA_512_SUM0
   UNSPEC_SHA_512_SUM1
+  UNSPEC_SM3_P0
+  UNSPEC_SM3_P1
   UNSPEC_SM4_ED
   UNSPEC_SM4_KS
 ])
@@ -253,6 +255,23 @@ (define_insn "riscv_sha512sum1"
   "sha512sum1\t%0,%1")
 
 
+;; Zksh - SM3
+
+(define_insn "riscv_sm3p0_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SM3_P0))]
+  "TARGET_ZKSH"
+  "sm3p0\t%0,%1")
+
+(define_insn "riscv_sm3p1_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SM3_P1))]
+  "TARGET_ZKSH"
+  "sm3p1\t%0,%1")
+
+
 ;; Zksed - SM4
 
 (define_insn "riscv_sm4ed_<mode>"
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 6ad89db42f5..dafcf1f591f 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -87,10 +87,12 @@ enum stack_protector_guard {
 #define MASK_ZKND     (1 << 6)
 #define MASK_ZKNH     (1 << 7)
 #define MASK_ZKSED    (1 << 9)
+#define MASK_ZKSH     (1 << 10)
 
 #define TARGET_ZKNE   ((riscv_zk_subext & MASK_ZKNE) != 0)
 #define TARGET_ZKND   ((riscv_zk_subext & MASK_ZKND) != 0)
 #define TARGET_ZKNH   ((riscv_zk_subext & MASK_ZKNH) != 0)
 #define TARGET_ZKSED  ((riscv_zk_subext & MASK_ZKSED) != 0)
+#define TARGET_ZKSH   ((riscv_zk_subext & MASK_ZKSH) != 0)
 
 #endif /* ! GCC_RISCV_OPTS_H */
-- 
2.25.1

[PATCH 13/21] [crypto]: add builtins for Zksh

[siyu]

From: SiYu Wu <siyu@isrc.iscas.ac.cn>

---
 gcc/config/riscv/riscv-builtins-crypto.def | 6 ++++++
 gcc/config/riscv/riscv-builtins.c          | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/gcc/config/riscv/riscv-builtins-crypto.def b/gcc/config/riscv/riscv-builtins-crypto.def
index 47bfff80f2e..abef52057a0 100644
--- a/gcc/config/riscv/riscv-builtins-crypto.def
+++ b/gcc/config/riscv/riscv-builtins-crypto.def
@@ -57,6 +57,12 @@ DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI, crypto_zknh64),
 
+// Zksh - SM3
+RISCV_BUILTIN (sm3p0_si, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zksh32),
+RISCV_BUILTIN (sm3p0_di, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zksh64),
+RISCV_BUILTIN (sm3p1_si, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zksh32),
+RISCV_BUILTIN (sm3p1_di, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zksh64),
+
 // Zksed - SM4
 RISCV_BUILTIN (sm4ed_si, "sm4ed", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zksed32),
 RISCV_BUILTIN (sm4ed_di, "sm4ed", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_SI, crypto_zksed64),
diff --git a/gcc/config/riscv/riscv-builtins.c b/gcc/config/riscv/riscv-builtins.c
index 1eed8d3fcb3..86701bb8ada 100644
--- a/gcc/config/riscv/riscv-builtins.c
+++ b/gcc/config/riscv/riscv-builtins.c
@@ -96,6 +96,8 @@ AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT)
 AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT)
 AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT)
 
+AVAIL (crypto_zksh32, TARGET_ZKSH && !TARGET_64BIT)
+AVAIL (crypto_zksh64, TARGET_ZKSH && TARGET_64BIT)
 AVAIL (crypto_zksed32, TARGET_ZKSED && !TARGET_64BIT)
 AVAIL (crypto_zksed64, TARGET_ZKSED && TARGET_64BIT)
 
-- 
2.25.1

[PATCH 14/21] [crypto]: add testcases for Zksh

[siyu]

From: SiYu Wu <siyu@isrc.iscas.ac.cn>

Co-authored-by: Shihua Liao <shihua@iscas.ac.cn>
---
 gcc/testsuite/gcc.target/riscv/Zksh-sm3.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/Zksh-sm3.c

diff --git a/gcc/testsuite/gcc.target/riscv/Zksh-sm3.c b/gcc/testsuite/gcc.target/riscv/Zksh-sm3.c
new file mode 100644
index 00000000000..88ef5a55816
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/Zksh-sm3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zksh -mabi=lp64 -O2" } */
+
+long foo1(long rs1)
+{
+    return __builtin_riscv_sm3p0(rs1);
+}
+
+long foo2(long rs1)
+{
+    return __builtin_riscv_sm3p1(rs1);
+}
+
+/* { dg-final { scan-assembler-times "sm3p0" 1 } } */
+/* { dg-final { scan-assembler-times "sm3p1" 1 } } */
\ No newline at end of file
-- 
2.25.1

[PATCH 15/21] [crypto]: add option defines for Zkr and Zkt

[siyu]

From: SiYu Wu <siyu@isrc.iscas.ac.cn>

---
 gcc/common/config/riscv/riscv-common.c | 3 +++
 gcc/config/riscv/riscv-opts.h          | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
index 8f4f4472690..b2b85180ffe 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -109,8 +109,10 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
   {"zkne",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zknd",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zknh",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zkr",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zksed", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zksh",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zkt",   ISA_SPEC_CLASS_NONE, 1, 0},
 
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
@@ -927,6 +929,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"zknh",   &gcc_options::x_riscv_zk_subext, MASK_ZKNH},
   {"zksed",  &gcc_options::x_riscv_zk_subext, MASK_ZKSED},
   {"zksh",   &gcc_options::x_riscv_zk_subext, MASK_ZKSH},
+  {"zkt",    &gcc_options::x_riscv_zk_subext, MASK_ZKT},
 
   {NULL, NULL, 0}
 };
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index dafcf1f591f..df254d1015e 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -86,13 +86,16 @@ enum stack_protector_guard {
 #define MASK_ZKNE     (1 << 5)
 #define MASK_ZKND     (1 << 6)
 #define MASK_ZKNH     (1 << 7)
+#define MASK_ZKR      (1 << 8)
 #define MASK_ZKSED    (1 << 9)
 #define MASK_ZKSH     (1 << 10)
+#define MASK_ZKT      (1 << 11)
 
 #define TARGET_ZKNE   ((riscv_zk_subext & MASK_ZKNE) != 0)
 #define TARGET_ZKND   ((riscv_zk_subext & MASK_ZKND) != 0)
 #define TARGET_ZKNH   ((riscv_zk_subext & MASK_ZKNH) != 0)
 #define TARGET_ZKSED  ((riscv_zk_subext & MASK_ZKSED) != 0)
 #define TARGET_ZKSH   ((riscv_zk_subext & MASK_ZKSH) != 0)
+#define TARGET_ZKT    ((riscv_zk_subext & MASK_ZKT) != 0)
 
 #endif /* ! GCC_RISCV_OPTS_H */
-- 
2.25.1

[PATCH 16/21] [crypto]: add option defines for Zbkb, Zbkc and Zbkx

[siyu]

From: SiYu Wu <siyu@isrc.iscas.ac.cn>

---
 gcc/common/config/riscv/riscv-common.c | 6 ++++++
 gcc/config/riscv/riscv-opts.h          | 6 ++++++
 2 files changed, 12 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
index b2b85180ffe..18c09591c42 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -106,6 +106,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
   {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zbkb",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zbkc",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zbkx",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zkne",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zknd",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zknh",  ISA_SPEC_CLASS_NONE, 1, 0},
@@ -924,6 +927,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"zbc",    &gcc_options::x_riscv_zb_subext, MASK_ZBC},
   {"zbs",    &gcc_options::x_riscv_zb_subext, MASK_ZBS},
 
+  {"zbkb",   &gcc_options::x_riscv_zk_subext, MASK_ZBKB},
+  {"zbkc",   &gcc_options::x_riscv_zk_subext, MASK_ZBKC},
+  {"zbkx",   &gcc_options::x_riscv_zk_subext, MASK_ZBKX},
   {"zknd",   &gcc_options::x_riscv_zk_subext, MASK_ZKND},
   {"zkne",   &gcc_options::x_riscv_zk_subext, MASK_ZKNE},
   {"zknh",   &gcc_options::x_riscv_zk_subext, MASK_ZKNH},
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index df254d1015e..dde426a7348 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -83,6 +83,9 @@ enum stack_protector_guard {
 #define TARGET_ZBC    ((riscv_zb_subext & MASK_ZBC) != 0)
 #define TARGET_ZBS    ((riscv_zb_subext & MASK_ZBS) != 0)
 
+#define MASK_ZBKB     (1 << 2)
+#define MASK_ZBKC     (1 << 3)
+#define MASK_ZBKX     (1 << 4)
 #define MASK_ZKNE     (1 << 5)
 #define MASK_ZKND     (1 << 6)
 #define MASK_ZKNH     (1 << 7)
@@ -91,6 +94,9 @@ enum stack_protector_guard {
 #define MASK_ZKSH     (1 << 10)
 #define MASK_ZKT      (1 << 11)
 
+#define TARGET_ZBKB   ((riscv_zk_subext & MASK_ZBKB) != 0)
+#define TARGET_ZBKC   ((riscv_zk_subext & MASK_ZBKC) != 0)
+#define TARGET_ZBKX   ((riscv_zk_subext & MASK_ZBKX) != 0)
 #define TARGET_ZKNE   ((riscv_zk_subext & MASK_ZKNE) != 0)
 #define TARGET_ZKND   ((riscv_zk_subext & MASK_ZKND) != 0)
 #define TARGET_ZKNH   ((riscv_zk_subext & MASK_ZKNH) != 0)
-- 
2.25.1

[PATCH 17/21] [crypto]: add implied defines of Zk, Zkn and Zks

[siyu]

From: SiYu Wu <siyu@isrc.iscas.ac.cn>

---
 gcc/common/config/riscv/riscv-common.c | 16 +++++++++++++++-
 gcc/config/riscv/arch-canonicalize     | 16 +++++++++++++++-
 2 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
index 18c09591c42..4ed2a1f662a 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -50,6 +50,20 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"d", "f"},
   {"f", "zicsr"},
   {"d", "zicsr"},
+  {"zk", "zkn"},
+  {"zk", "zkr"},
+  {"zk", "zkt"},
+  {"zkn", "zbkb"},
+  {"zkn", "zbkc"},
+  {"zkn", "zbkx"},
+  {"zkn", "zkne"},
+  {"zkn", "zknd"},
+  {"zkn", "zknh"},
+  {"zks", "zbkb"},
+  {"zks", "zbkc"},
+  {"zks", "zbkx"},
+  {"zks", "zksed"},
+  {"zks", "zksh"},
   {NULL, NULL}
 };
 
@@ -503,7 +517,7 @@ riscv_subset_list::lookup (const char *subset, int major_version,
 static const char *
 riscv_supported_std_ext (void)
 {
-  return "mafdqlcbjtpvn";
+  return "mafdqlcbjktpvn";
 }
 
 /* Parsing subset version.
diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize
index e2feb7e85cd..284a0dc0073 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -28,7 +28,7 @@ import itertools
 from functools import reduce
 
 
-CANONICAL_ORDER = "imafdgqlcbjtpvn"
+CANONICAL_ORDER = "imafdgqlcbjktpvn"
 LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
 
 #
@@ -38,6 +38,20 @@ IMPLIED_EXT = {
   "d" : ["f"],
   "f" : ["zicsr"],
   "f" : ["zifencei"],
+  "zk" : ["zkn"],
+  "zk" : ["zkr"],
+  "zk" : ["zkt"],
+  "zkn" : ["zbkb"],
+  "zkn" : ["zbkc"],
+  "zkn" : ["zbkx"],
+  "zkn" : ["zkne"],
+  "zkn" : ["zknd"],
+  "zkn" : ["zknh"],
+  "zks" : ["zbkb"],
+  "zks" : ["zbkc"],
+  "zks" : ["zbkx"],
+  "zks" : ["zksed"],
+  "zks" : ["zksh"],
 }
 
 def arch_canonicalize(arch):
-- 
2.25.1

[PATCH 18/21] change z* subset assert to allow "zk"

[siyu]

From: SiYu Wu <siyu@isrc.iscas.ac.cn>

---
 gcc/common/config/riscv/riscv-common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
index 4ed2a1f662a..e801fa149a2 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -227,7 +227,7 @@ multi_letter_subset_rank (const std::string &subset)
       high_order = 1;
       break;
     case 'z':
-      gcc_assert (subset.length () > 2);
+      gcc_assert (subset.length () > 1);
       high_order = 2;
       break;
     case 'x':
-- 
2.25.1

[PATCH 19/21] [crypto]: add machine description for Zbkx

[siyu]

From: SiYu Wu <siyu@isrc.iscas.ac.cn>

NOTE: The Zbkx should be implemented in bitmanip's Zbp, but since zbp is not
included in the bitmanip spec v1.0, and crypto's v1.0 release will earlier
than bitmanip's next release, so for now we implementing it here.
---
 gcc/config/riscv/crypto.md | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 79ca2ec2696..8753f2f585c 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -42,6 +42,10 @@ (define_c_enum "unspec" [
   UNSPEC_SM3_P1
   UNSPEC_SM4_ED
   UNSPEC_SM4_KS
+
+  ;; Zbkx unspecs, see below
+  UNSPEC_XPERM8
+  UNSPEC_XPERM4
 ])
 
 
@@ -290,3 +294,26 @@ (define_insn "riscv_sm4ks_<mode>"
   "TARGET_ZKSED"
   "sm4ks\t%0,%1,%2")
 
+;; Zbkx
+
+;; The Zbkx should be implemented in bitmanip's Zbp, but since zbp is not
+;; included in the bitmanip spec v1.0, and crypto's v1.0 release will earlier
+;; than bitmanip's next release, so for now we implementing it here.
+;;                                                                   2021/10/24
+
+(define_insn "riscv_xperm8_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")]
+                  UNSPEC_XPERM8))]
+  "TARGET_ZBKX"
+  "xperm8\t%0,%1,%2")
+
+(define_insn "riscv_xperm4_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")]
+                  UNSPEC_XPERM4))]
+  "TARGET_ZBKX"
+  "xperm4\t%0,%1,%2")
+
-- 
2.25.1

[PATCH 20/21] [crypto]: add builtins for Zbkx

[siyu]

From: SiYu Wu <siyu@isrc.iscas.ac.cn>

---
 gcc/config/riscv/riscv-builtins-crypto.def | 6 ++++++
 gcc/config/riscv/riscv-builtins.c          | 3 +++
 2 files changed, 9 insertions(+)

diff --git a/gcc/config/riscv/riscv-builtins-crypto.def b/gcc/config/riscv/riscv-builtins-crypto.def
index abef52057a0..e8c36789fe5 100644
--- a/gcc/config/riscv/riscv-builtins-crypto.def
+++ b/gcc/config/riscv/riscv-builtins-crypto.def
@@ -68,3 +68,9 @@ RISCV_BUILTIN (sm4ed_si, "sm4ed", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, cr
 RISCV_BUILTIN (sm4ed_di, "sm4ed", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_SI, crypto_zksed64),
 RISCV_BUILTIN (sm4ks_si, "sm4ks", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zksed32),
 RISCV_BUILTIN (sm4ks_di, "sm4ks", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_SI, crypto_zksed64),
+
+// Zbkx
+RISCV_BUILTIN (xperm4_si, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32),
+RISCV_BUILTIN (xperm4_di, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64),
+RISCV_BUILTIN (xperm8_si, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32),
+RISCV_BUILTIN (xperm8_di, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64),
diff --git a/gcc/config/riscv/riscv-builtins.c b/gcc/config/riscv/riscv-builtins.c
index 86701bb8ada..3a487abbc80 100644
--- a/gcc/config/riscv/riscv-builtins.c
+++ b/gcc/config/riscv/riscv-builtins.c
@@ -101,6 +101,9 @@ AVAIL (crypto_zksh64, TARGET_ZKSH && TARGET_64BIT)
 AVAIL (crypto_zksed32, TARGET_ZKSED && !TARGET_64BIT)
 AVAIL (crypto_zksed64, TARGET_ZKSED && TARGET_64BIT)
 
+AVAIL (crypto_zbkx32, TARGET_ZBKX && !TARGET_64BIT)
+AVAIL (crypto_zbkx64, TARGET_ZBKX && TARGET_64BIT)
+
 /* Construct a riscv_builtin_description from the given arguments.
 
    INSN is the name of the associated instruction pattern, without the
-- 
2.25.1

Re: [PATCH 02/21] Fix attribute bugs due to zicsr/zifencei

[Kito Cheng]

> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 225e5b259c1..1a786f31258 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -1812,7 +1812,7 @@ (define_expand "clear_cache"
>
>  (define_insn "fence"
>    [(unspec_volatile [(const_int 0)] UNSPECV_FENCE)]
> -  ""
> +  "TARGET_ZIFENCEI"
   "%|fence%-")

fence instruction is included in baseline ISA.
https://github.com/riscv/riscv-isa-manual/blob/master/src/rv32.tex#L1206

Re: [PATCH 01/21] Fix riscv_expand_block_move

[Kito Cheng]

IIRC this issue should be resolved?

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99314

On Sun, Oct 31, 2021 at 5:34 PM <siyu@isrc.iscas.ac.cn> wrote:
>
> From: linsinan1995 <47880367+linsinan1995@users.noreply.github.com>
>
> ---
>  gcc/config/riscv/riscv.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
> index 6aef3d3a6cf..0529b6d60cd 100644
> --- a/gcc/config/riscv/riscv.c
> +++ b/gcc/config/riscv/riscv.c
> @@ -3491,7 +3491,7 @@ riscv_block_move_loop (rtx dest, rtx src, unsigned HOST_WIDE_INT length,
>  bool
>  riscv_expand_block_move (rtx dest, rtx src, rtx length)
>  {
> -  if (CONST_INT_P (length))
> +  if (CONST_INT_P (length) && INTVAL (length) >= 0)
>      {
>        unsigned HOST_WIDE_INT hwi_length = UINTVAL (length);
>        unsigned HOST_WIDE_INT factor, align;
> --
> 2.25.1
>

Re: [PATCH 00/21] RISC-V: add gcc support for Scalar Cryptography v1.0.0-rc5

[Kito Cheng]

Hi Si-Yu:

Thanks for your patch!

Here is a general comment for this patch-set, GCC require ChagneLog in
commit log, and seems like that is included in your commit log, you
can refer other commit log to see how changelog wrote.

Scalar cryptography extension seems not define builtin and intrinsic
within the spec, I would prefer add those builtin to
riscv-c-api-doc[1] before adding to GCC for make sure LLVM and GCC
toolchain has consistent interface, so I would like to merge arch
string related stuffs only first.

So could you send a V2 patchset without builtins and md changes?


[1] https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md

Thanks!






On Sun, Oct 31, 2021 at 5:34 PM <siyu@isrc.iscas.ac.cn> wrote:
>
> From: SiYu Wu <siyu@isrc.iscas.ac.cn>
>
> This patch add gcc backend support for RISC-V Scalar Cryptography
> Extension (k-ext), including machine description, builtins defines and
> testcases for each k-ext's subset.
>
> A note about Zbkx: The Zbkx should be implemented in bitmanip's Zbp, but
> since zbp is not included in the bitmanip spec v1.0, and crypto's v1.0
> release will earlier than bitmanip's next release, so for now we
> implementing it here.
>
> SiYu Wu (19):
>   [crypto]: add machine description for Zknd and Zkne
>   [crypto]: add builtins for Zknd and Zkne
>   [crypto]: add testcases for Zknd and Zkne
>   [crypto]: add machine description for Zknh
>   [crypto]: add builtins for Zknh
>   [crypto]: add testcases for Zknh
>   [crypto]: add machine description for Zksed
>   [crypto]: add builtins for Zksed
>   [crypto]: add testcases for Zksed
>   [crypto]: add machine description for Zksh
>   [crypto]: add builtins for Zksh
>   [crypto]: add testcases for Zksh
>   [crypto]: add option defines for Zkr and Zkt
>   [crypto]: add option defines for Zbkb, Zbkc and Zbkx
>   [crypto]: add implied defines of Zk, Zkn and Zks
>   change z* subset assert to allow "zk"
>   [crypto]: add machine description for Zbkx
>   [crypto]: add builtins for Zbkx
>   [crypto]: add testcases for Zbkx
>
> jiawei (1):
>   Fix attribute bugs due to zicsr/zifencei
>
> linsinan1995 (1):
>   Fix riscv_expand_block_move
>
>  gcc/common/config/riscv/riscv-common.c        |  39 ++-
>  gcc/config/riscv/arch-canonicalize            |  18 +-
>  gcc/config/riscv/crypto.md                    | 319 ++++++++++++++++++
>  gcc/config/riscv/riscv-builtins-crypto.def    |  76 +++++
>  gcc/config/riscv/riscv-builtins.c             |  25 ++
>  gcc/config/riscv/riscv-ftypes.def             |   6 +
>  gcc/config/riscv/riscv-opts.h                 |  21 ++
>  gcc/config/riscv/riscv.c                      |   2 +-
>  gcc/config/riscv/riscv.md                     |   4 +-
>  gcc/config/riscv/riscv.opt                    |   3 +
>  gcc/testsuite/gcc.target/riscv/Zbkx.c         |  17 +
>  gcc/testsuite/gcc.target/riscv/Zknd-aes-01.c  |  15 +
>  gcc/testsuite/gcc.target/riscv/Zknd-aes-02.c  |  21 ++
>  gcc/testsuite/gcc.target/riscv/Zkne-aes-01.c  |  15 +
>  gcc/testsuite/gcc.target/riscv/Zkne-aes-02.c  |  27 ++
>  gcc/testsuite/gcc.target/riscv/Zknh-sha256.c  |  27 ++
>  .../gcc.target/riscv/Zknh-sha512-01.c         |  40 +++
>  .../gcc.target/riscv/Zknh-sha512-02.c         |  28 ++
>  gcc/testsuite/gcc.target/riscv/Zksed-sm4.c    |  17 +
>  gcc/testsuite/gcc.target/riscv/Zksh-sm3.c     |  15 +
>  20 files changed, 730 insertions(+), 5 deletions(-)
>  create mode 100644 gcc/config/riscv/crypto.md
>  create mode 100644 gcc/config/riscv/riscv-builtins-crypto.def
>  create mode 100644 gcc/testsuite/gcc.target/riscv/Zbkx.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/Zknd-aes-01.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/Zknd-aes-02.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/Zkne-aes-01.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/Zkne-aes-02.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/Zknh-sha256.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/Zknh-sha512-01.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/Zknh-sha512-02.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/Zksed-sm4.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/Zksh-sm3.c
>
> --
> 2.25.1
>

Re: [PATCH 14/21] [crypto]: add testcases for Zksh

[Christoph Muellner]

On Sun, Oct 31, 2021 at 10:34 AM <siyu@isrc.iscas.ac.cn> wrote:
>
> From: SiYu Wu <siyu@isrc.iscas.ac.cn>

You forgot the commit message.
Please have a read at the GCC Coding Conventions for the requirements:
https://gcc.gnu.org/codingconventions.html
Note that GCC commit messages require ChangeLog entries (a template
can be generated with ./contrib/mklog.py).

>
> Co-authored-by: Shihua Liao <shihua@iscas.ac.cn>
> ---
>  gcc/testsuite/gcc.target/riscv/Zksh-sm3.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/Zksh-sm3.c
>
> diff --git a/gcc/testsuite/gcc.target/riscv/Zksh-sm3.c b/gcc/testsuite/gcc.target/riscv/Zksh-sm3.c
> new file mode 100644
> index 00000000000..88ef5a55816
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/Zksh-sm3.c
> @@ -0,0 +1,15 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_zksh -mabi=lp64 -O2" } */
> +
> +long foo1(long rs1)
> +{
> +    return __builtin_riscv_sm3p0(rs1);
> +}
> +
> +long foo2(long rs1)
> +{
> +    return __builtin_riscv_sm3p1(rs1);
> +}
> +
> +/* { dg-final { scan-assembler-times "sm3p0" 1 } } */
> +/* { dg-final { scan-assembler-times "sm3p1" 1 } } */
> \ No newline at end of file
> --
> 2.25.1
>