From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 492383858429 for ; Mon, 8 Nov 2021 17:42:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 492383858429 Received: from pps.filterd (m0187473.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 1A8GVM0S030174; Mon, 8 Nov 2021 17:42:33 GMT Received: from ppma04wdc.us.ibm.com (1a.90.2fa9.ip4.static.sl-reverse.com [169.47.144.26]) by mx0a-001b2d01.pphosted.com with ESMTP id 3c66rq760f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Nov 2021 17:42:33 +0000 Received: from pps.filterd (ppma04wdc.us.ibm.com [127.0.0.1]) by ppma04wdc.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 1A8HX13e012236; Mon, 8 Nov 2021 17:42:32 GMT Received: from b03cxnp08026.gho.boulder.ibm.com (b03cxnp08026.gho.boulder.ibm.com [9.17.130.18]) by ppma04wdc.us.ibm.com with ESMTP id 3c5hba1bjt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Nov 2021 17:42:32 +0000 Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1A8HgU6m40174038 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 8 Nov 2021 17:42:30 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 921EB6A064; Mon, 8 Nov 2021 17:42:30 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B064D6A04D; Mon, 8 Nov 2021 17:42:29 +0000 (GMT) Received: from li-24c3614c-2adc-11b2-a85c-85f334518bdb.ibm.com (unknown [9.160.169.99]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTPS; Mon, 8 Nov 2021 17:42:29 +0000 (GMT) Date: Mon, 8 Nov 2021 11:42:27 -0600 From: "Paul A. Clarke" To: segher@kernel.crashing.org, wschmidt@linux.ibm.com, gcc-patches@gcc.gnu.org Subject: [PING PATCH] rs6000: Add Power10 optimization for _mm_blendv* Message-ID: <20211108174227.GD12060@li-24c3614c-2adc-11b2-a85c-85f334518bdb.ibm.com> References: <20211021014207.342435-1-pc@us.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211021014207.342435-1-pc@us.ibm.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: vLjm3-n8E9UBbyjQxK-c9Yq3jgSyG_Wb X-Proofpoint-GUID: vLjm3-n8E9UBbyjQxK-c9Yq3jgSyG_Wb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-08_05,2021-11-08_02,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 bulkscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 spamscore=0 phishscore=0 priorityscore=1501 adultscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2111080105 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 08 Nov 2021 17:42:35 -0000 Gentle ping... On Wed, Oct 20, 2021 at 08:42:07PM -0500, Paul A. Clarke via Gcc-patches wrote: > Power10 ISA added `xxblendv*` instructions which are realized in the > `vec_blendv` instrinsic. > > Use `vec_blendv` for `_mm_blendv_epi8`, `_mm_blendv_ps`, and > `_mm_blendv_pd` compatibility intrinsics, when `_ARCH_PWR10`. > > Also, copy a test from i386 for testing `_mm_blendv_ps`. > This should have come with commit ed04cf6d73e233c74c4e55c27f1cbd89ae4710e8, > but was inadvertently omitted. > > 2021-10-20 Paul A. Clarke > > gcc > * config/rs6000/smmintrin.h (_mm_blendv_epi8): Use vec_blendv > when _ARCH_PWR10. > (_mm_blendv_ps): Likewise. > (_mm_blendv_pd): Likewise. > > gcc/testsuite > * gcc.target/powerpc/sse4_1-blendvps.c: Copy from gcc.target/i386, > adjust dg directives to suit. > --- > Tested on Power10 powerpc64le-linux (compiled with and without > `-mcpu=power10`). > > OK for trunk? > > gcc/config/rs6000/smmintrin.h | 12 ++++ > .../gcc.target/powerpc/sse4_1-blendvps.c | 65 +++++++++++++++++++ > 2 files changed, 77 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-blendvps.c > > diff --git a/gcc/config/rs6000/smmintrin.h b/gcc/config/rs6000/smmintrin.h > index b732fbca7b09..5d87fd7b6f61 100644 > --- a/gcc/config/rs6000/smmintrin.h > +++ b/gcc/config/rs6000/smmintrin.h > @@ -113,9 +113,13 @@ _mm_blend_epi16 (__m128i __A, __m128i __B, const int __imm8) > extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) > _mm_blendv_epi8 (__m128i __A, __m128i __B, __m128i __mask) > { > +#ifdef _ARCH_PWR10 > + return (__m128i) vec_blendv ((__v16qu) __A, (__v16qu) __B, (__v16qu) __mask); > +#else > const __v16qu __seven = vec_splats ((unsigned char) 0x07); > __v16qu __lmask = vec_sra ((__v16qu) __mask, __seven); > return (__m128i) vec_sel ((__v16qu) __A, (__v16qu) __B, __lmask); > +#endif > } > > __inline __m128 > @@ -149,9 +153,13 @@ __inline __m128 > __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) > _mm_blendv_ps (__m128 __A, __m128 __B, __m128 __mask) > { > +#ifdef _ARCH_PWR10 > + return (__m128) vec_blendv ((__v4sf) __A, (__v4sf) __B, (__v4su) __mask); > +#else > const __v4si __zero = {0}; > const __vector __bool int __boolmask = vec_cmplt ((__v4si) __mask, __zero); > return (__m128) vec_sel ((__v4su) __A, (__v4su) __B, (__v4su) __boolmask); > +#endif > } > > __inline __m128d > @@ -174,9 +182,13 @@ __inline __m128d > __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) > _mm_blendv_pd (__m128d __A, __m128d __B, __m128d __mask) > { > +#ifdef _ARCH_PWR10 > + return (__m128d) vec_blendv ((__v2df) __A, (__v2df) __B, (__v2du) __mask); > +#else > const __v2di __zero = {0}; > const __vector __bool long long __boolmask = vec_cmplt ((__v2di) __mask, __zero); > return (__m128d) vec_sel ((__v2du) __A, (__v2du) __B, (__v2du) __boolmask); > +#endif > } > #endif > > diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-blendvps.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-blendvps.c > new file mode 100644 > index 000000000000..8fcb55383047 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-blendvps.c > @@ -0,0 +1,65 @@ > +/* { dg-do run } */ > +/* { dg-require-effective-target p8vector_hw } */ > +/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ > + > +#include "sse4_1-check.h" > + > +#include > +#include > + > +#define NUM 20 > + > +static void > +init_blendvps (float *src1, float *src2, float *mask) > +{ > + int i, msk, sign = 1; > + > + msk = -1; > + for (i = 0; i < NUM * 4; i++) > + { > + if((i % 4) == 0) > + msk++; > + src1[i] = i* (i + 1) * sign; > + src2[i] = (i + 20) * sign; > + mask[i] = (i + 120) * i; > + if( (msk & (1 << (i % 4)))) > + mask[i] = -mask[i]; > + sign = -sign; > + } > +} > + > +static int > +check_blendvps (__m128 *dst, float *src1, float *src2, > + float *mask) > +{ > + float tmp[4]; > + int j; > + > + memcpy (&tmp[0], src1, sizeof (tmp)); > + for (j = 0; j < 4; j++) > + if (mask [j] < 0.0) > + tmp[j] = src2[j]; > + > + return memcmp (dst, &tmp[0], sizeof (tmp)); > +} > + > +static void > +sse4_1_test (void) > +{ > + union > + { > + __m128 x[NUM]; > + float f[NUM * 4]; > + } dst, src1, src2, mask; > + int i; > + > + init_blendvps (src1.f, src2.f, mask.f); > + > + for (i = 0; i < NUM; i++) > + { > + dst.x[i] = _mm_blendv_ps (src1.x[i], src2.x[i], mask.x[i]); > + if (check_blendvps (&dst.x[i], &src1.f[i * 4], &src2.f[i * 4], > + &mask.f[i * 4])) > + abort (); > + } > +} > -- > 2.27.0 >