From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by sourceware.org (Postfix) with ESMTPS id 732583858C3A for ; Tue, 9 Nov 2021 15:59:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 732583858C3A Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-179-o87AIpG_M0yB5GedaGvCkQ-1; Tue, 09 Nov 2021 10:59:31 -0500 X-MC-Unique: o87AIpG_M0yB5GedaGvCkQ-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id C3AE1875047; Tue, 9 Nov 2021 15:59:21 +0000 (UTC) Received: from tucnak.zalov.cz (unknown [10.39.192.54]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 33ADC67846; Tue, 9 Nov 2021 15:59:18 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.16.1/8.16.1) with ESMTPS id 1A9FxFsa1606658 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Tue, 9 Nov 2021 16:59:16 +0100 Received: (from jakub@localhost) by tucnak.zalov.cz (8.16.1/8.16.1/Submit) id 1A9FxEpi1606657; Tue, 9 Nov 2021 16:59:14 +0100 Date: Tue, 9 Nov 2021 16:59:14 +0100 From: Jakub Jelinek To: Hafiz Abid Qadeer , Jason Merrill Cc: gcc-patches@gcc.gnu.org, ams@codesourcery.com Subject: Re: [PATCH] dwarf: Multi-register CFI address support. Message-ID: <20211109155914.GW2710@tucnak> Reply-To: Jakub Jelinek References: <20210613132738.615611-1-abidh@codesourcery.com> MIME-Version: 1.0 In-Reply-To: <20210613132738.615611-1-abidh@codesourcery.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-Spam-Status: No, score=-5.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 09 Nov 2021 15:59:39 -0000 On Sun, Jun 13, 2021 at 02:27:38PM +0100, Hafiz Abid Qadeer wrote: > *** with this patch (edited for brevity)*** > > 00000000 00000024 ffffffff CIE > > DW_CFA_def_cfa_expression: DW_OP_bregx SGPR49+0, DW_OP_const1u 0x20, DW_OP_shl, DW_OP_bregx SGPR48+0, DW_OP_plus > DW_CFA_expression: reg16 DW_OP_bregx SGPR51+0, DW_OP_const1u 0x20, DW_OP_shl, DW_OP_bregx SGPR50+0, DW_OP_plus > > 00000028 0000003c 00000000 FDE cie=00000000 pc=00000000...000001ac > DW_CFA_advance_loc4: 96 > DW_CFA_offset: reg46 0 > DW_CFA_offset: reg47 4 > DW_CFA_offset: reg50 8 > DW_CFA_offset: reg51 12 > DW_CFA_offset: reg16 8 > DW_CFA_advance_loc4: 4 > DW_CFA_def_cfa_expression: DW_OP_bregx SGPR47+0, DW_OP_const1u 0x20, DW_OP_shl, DW_OP_bregx SGPR46+0, DW_OP_plus, DW_OP_lit16, DW_OP_minus I guess as a temporary solution until DWARF6 comes with something more compact for cases like that it can be fine, but is there a DWARF issue filed for it? Is AMDGCN a DWARF2_ADDR_SIZE == 8 target? > +/* This represents a register, in DWARF_FRAME_REGNUM space, for use in CFA > + definitions and expressions. > + Most architectures only need a single register number, but some (amdgcn) > + have pointers that span multiple registers. DWARF permits arbitrary > + register sets but existing use-cases only require contiguous register > + sets, as represented here. */ > +struct GTY(()) cfa_reg { > + unsigned int reg; > + unsigned int span; > + poly_uint16_pod span_width; /* A.K.A. register mode size. */ If this is only used for span > 1, wouldn't it be better to make it unsigned int reg; unsigned short span; unsigned short span_width; and keep span_width 0 for the span == 1 cases and only set span_width to ....to_constant () if span > 1 is needed? If at least for now the only target that needs this is AMDGCN and the only target that has NUM_POLY_INT_COEFFS != 1 is aarch64 (maybe eventually riscv?), then I don't see why we should represent it in poly_uint16... Of course we can change it later if a target which needs both NUM_POLY_INT_COEFFS > 1 and span > 1 registers with non-constant span_width, we can change it, but doing it just in case seems unnecessary complication... Jakub