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From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, wilson@tuliptree.org,
	Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: [PATCH v1 2/8] RISC-V: costs: handle BSWAP
Date: Thu, 11 Nov 2021 15:10:14 +0100	[thread overview]
Message-ID: <20211111141020.2738001-3-philipp.tomsich@vrull.eu> (raw)
In-Reply-To: <20211111141020.2738001-1-philipp.tomsich@vrull.eu>

The BSWAP operation is not handled in rtx_costs. Add it.

gcc/ChangeLog:

        * config/riscv/riscv.c (rtx_costs): Add BSWAP.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---

 gcc/config/riscv/riscv.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index c77b0322869..8480cf09294 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -2131,6 +2131,14 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
       *total = riscv_extend_cost (XEXP (x, 0), GET_CODE (x) == ZERO_EXTEND);
       return false;
 
+    case BSWAP:
+      if (TARGET_ZBB)
+	{
+	  *total = COSTS_N_INSNS (1);
+	  return true;
+	}
+      return false;
+
     case FLOAT:
     case UNSIGNED_FLOAT:
     case FIX:
-- 
2.32.0


  parent reply	other threads:[~2021-11-11 14:10 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-11 14:10 [PATCH v1 0/8] Improvements to bitmanip-1.0 (Zb[abcs]) support Philipp Tomsich
2021-11-11 14:10 ` [PATCH v1 1/8] bswap: synthesize HImode bswap from SImode or DImode Philipp Tomsich
2021-11-17 14:51   ` Kito Cheng
2021-11-19 10:20   ` Richard Biener
2021-11-19 10:21     ` Richard Biener
2021-11-11 14:10 ` Philipp Tomsich [this message]
2021-11-17 14:52   ` [PATCH v1 2/8] RISC-V: costs: handle BSWAP Kito Cheng
2021-11-11 14:10 ` [PATCH v1 3/8] RISC-V: costs: support shift-and-add in strength-reduction Philipp Tomsich
2021-11-11 14:10 ` [PATCH v1 4/8] RISC-V: bitmanip: fix constant-loading for (1ULL << 31) in DImode Philipp Tomsich
2021-11-11 14:10 ` [PATCH v1 5/8] RISC-V: bitmanip: improvements to rotate instructions Philipp Tomsich
2021-11-11 14:10 ` [PATCH v1 6/8] RISC-V: bitmanip: add splitter to use bexti for "(a & (1 << BIT_NO)) ? 0 : -1" Philipp Tomsich
2021-11-18  9:45   ` Kito Cheng
2021-11-11 14:10 ` [PATCH v1 7/8] RISC-V: bitmanip: add orc.b as an unspec Philipp Tomsich
2021-11-11 14:10 ` [PATCH v1 8/8] RISC-V: bitmanip: relax minmax to operate on GPR Philipp Tomsich
2021-11-11 16:00   ` Kito Cheng
2021-11-11 16:18     ` Philipp Tomsich
2021-11-11 16:27       ` Kito Cheng
2021-11-11 16:42         ` Kito Cheng
2021-11-11 18:33           ` Philipp Tomsich

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