From: "H.J. Lu" <hjl.tools@gmail.com>
To: gcc-patches@gcc.gnu.org
Subject: [PATCH] libsanitizer: Use SSE to save and restore XMM registers
Date: Tue, 30 Nov 2021 06:20:09 -0800 [thread overview]
Message-ID: <20211130142009.832466-1-hjl.tools@gmail.com> (raw)
Use SSE, instead of AVX, to save and restore XMM registers to support
processors without AVX. The affected codes are unused in upstream since
https://github.com/llvm/llvm-project/commit/66d4ce7e26a5
and will be removed in
https://reviews.llvm.org/D112604
This fixed
FAIL: g++.dg/tsan/pthread_cond_clockwait.C -O0 execution test
FAIL: g++.dg/tsan/pthread_cond_clockwait.C -O2 execution test
on machines without AVX.
PR sanitizer/103466
* tsan/tsan_rtl_amd64.S (__tsan_trace_switch_thunk): Replace
vmovdqu with movdqu.
(__tsan_report_race_thunk): Likewise.
---
libsanitizer/tsan/tsan_rtl_amd64.S | 128 ++++++++++++++---------------
1 file changed, 64 insertions(+), 64 deletions(-)
diff --git a/libsanitizer/tsan/tsan_rtl_amd64.S b/libsanitizer/tsan/tsan_rtl_amd64.S
index 632b19d1815..c15b01e49e5 100644
--- a/libsanitizer/tsan/tsan_rtl_amd64.S
+++ b/libsanitizer/tsan/tsan_rtl_amd64.S
@@ -45,22 +45,22 @@ ASM_SYMBOL(__tsan_trace_switch_thunk):
# All XMM registers are caller-saved.
sub $0x100, %rsp
CFI_ADJUST_CFA_OFFSET(0x100)
- vmovdqu %xmm0, 0x0(%rsp)
- vmovdqu %xmm1, 0x10(%rsp)
- vmovdqu %xmm2, 0x20(%rsp)
- vmovdqu %xmm3, 0x30(%rsp)
- vmovdqu %xmm4, 0x40(%rsp)
- vmovdqu %xmm5, 0x50(%rsp)
- vmovdqu %xmm6, 0x60(%rsp)
- vmovdqu %xmm7, 0x70(%rsp)
- vmovdqu %xmm8, 0x80(%rsp)
- vmovdqu %xmm9, 0x90(%rsp)
- vmovdqu %xmm10, 0xa0(%rsp)
- vmovdqu %xmm11, 0xb0(%rsp)
- vmovdqu %xmm12, 0xc0(%rsp)
- vmovdqu %xmm13, 0xd0(%rsp)
- vmovdqu %xmm14, 0xe0(%rsp)
- vmovdqu %xmm15, 0xf0(%rsp)
+ movdqu %xmm0, 0x0(%rsp)
+ movdqu %xmm1, 0x10(%rsp)
+ movdqu %xmm2, 0x20(%rsp)
+ movdqu %xmm3, 0x30(%rsp)
+ movdqu %xmm4, 0x40(%rsp)
+ movdqu %xmm5, 0x50(%rsp)
+ movdqu %xmm6, 0x60(%rsp)
+ movdqu %xmm7, 0x70(%rsp)
+ movdqu %xmm8, 0x80(%rsp)
+ movdqu %xmm9, 0x90(%rsp)
+ movdqu %xmm10, 0xa0(%rsp)
+ movdqu %xmm11, 0xb0(%rsp)
+ movdqu %xmm12, 0xc0(%rsp)
+ movdqu %xmm13, 0xd0(%rsp)
+ movdqu %xmm14, 0xe0(%rsp)
+ movdqu %xmm15, 0xf0(%rsp)
# Align stack frame.
push %rbx # non-scratch
CFI_ADJUST_CFA_OFFSET(8)
@@ -78,22 +78,22 @@ ASM_SYMBOL(__tsan_trace_switch_thunk):
pop %rbx
CFI_ADJUST_CFA_OFFSET(-8)
# Restore scratch registers.
- vmovdqu 0x0(%rsp), %xmm0
- vmovdqu 0x10(%rsp), %xmm1
- vmovdqu 0x20(%rsp), %xmm2
- vmovdqu 0x30(%rsp), %xmm3
- vmovdqu 0x40(%rsp), %xmm4
- vmovdqu 0x50(%rsp), %xmm5
- vmovdqu 0x60(%rsp), %xmm6
- vmovdqu 0x70(%rsp), %xmm7
- vmovdqu 0x80(%rsp), %xmm8
- vmovdqu 0x90(%rsp), %xmm9
- vmovdqu 0xa0(%rsp), %xmm10
- vmovdqu 0xb0(%rsp), %xmm11
- vmovdqu 0xc0(%rsp), %xmm12
- vmovdqu 0xd0(%rsp), %xmm13
- vmovdqu 0xe0(%rsp), %xmm14
- vmovdqu 0xf0(%rsp), %xmm15
+ movdqu 0x0(%rsp), %xmm0
+ movdqu 0x10(%rsp), %xmm1
+ movdqu 0x20(%rsp), %xmm2
+ movdqu 0x30(%rsp), %xmm3
+ movdqu 0x40(%rsp), %xmm4
+ movdqu 0x50(%rsp), %xmm5
+ movdqu 0x60(%rsp), %xmm6
+ movdqu 0x70(%rsp), %xmm7
+ movdqu 0x80(%rsp), %xmm8
+ movdqu 0x90(%rsp), %xmm9
+ movdqu 0xa0(%rsp), %xmm10
+ movdqu 0xb0(%rsp), %xmm11
+ movdqu 0xc0(%rsp), %xmm12
+ movdqu 0xd0(%rsp), %xmm13
+ movdqu 0xe0(%rsp), %xmm14
+ movdqu 0xf0(%rsp), %xmm15
add $0x100, %rsp
CFI_ADJUST_CFA_OFFSET(-0x100)
pop %r11
@@ -163,22 +163,22 @@ ASM_SYMBOL(__tsan_report_race_thunk):
# All XMM registers are caller-saved.
sub $0x100, %rsp
CFI_ADJUST_CFA_OFFSET(0x100)
- vmovdqu %xmm0, 0x0(%rsp)
- vmovdqu %xmm1, 0x10(%rsp)
- vmovdqu %xmm2, 0x20(%rsp)
- vmovdqu %xmm3, 0x30(%rsp)
- vmovdqu %xmm4, 0x40(%rsp)
- vmovdqu %xmm5, 0x50(%rsp)
- vmovdqu %xmm6, 0x60(%rsp)
- vmovdqu %xmm7, 0x70(%rsp)
- vmovdqu %xmm8, 0x80(%rsp)
- vmovdqu %xmm9, 0x90(%rsp)
- vmovdqu %xmm10, 0xa0(%rsp)
- vmovdqu %xmm11, 0xb0(%rsp)
- vmovdqu %xmm12, 0xc0(%rsp)
- vmovdqu %xmm13, 0xd0(%rsp)
- vmovdqu %xmm14, 0xe0(%rsp)
- vmovdqu %xmm15, 0xf0(%rsp)
+ movdqu %xmm0, 0x0(%rsp)
+ movdqu %xmm1, 0x10(%rsp)
+ movdqu %xmm2, 0x20(%rsp)
+ movdqu %xmm3, 0x30(%rsp)
+ movdqu %xmm4, 0x40(%rsp)
+ movdqu %xmm5, 0x50(%rsp)
+ movdqu %xmm6, 0x60(%rsp)
+ movdqu %xmm7, 0x70(%rsp)
+ movdqu %xmm8, 0x80(%rsp)
+ movdqu %xmm9, 0x90(%rsp)
+ movdqu %xmm10, 0xa0(%rsp)
+ movdqu %xmm11, 0xb0(%rsp)
+ movdqu %xmm12, 0xc0(%rsp)
+ movdqu %xmm13, 0xd0(%rsp)
+ movdqu %xmm14, 0xe0(%rsp)
+ movdqu %xmm15, 0xf0(%rsp)
# Align stack frame.
push %rbx # non-scratch
CFI_ADJUST_CFA_OFFSET(8)
@@ -196,22 +196,22 @@ ASM_SYMBOL(__tsan_report_race_thunk):
pop %rbx
CFI_ADJUST_CFA_OFFSET(-8)
# Restore scratch registers.
- vmovdqu 0x0(%rsp), %xmm0
- vmovdqu 0x10(%rsp), %xmm1
- vmovdqu 0x20(%rsp), %xmm2
- vmovdqu 0x30(%rsp), %xmm3
- vmovdqu 0x40(%rsp), %xmm4
- vmovdqu 0x50(%rsp), %xmm5
- vmovdqu 0x60(%rsp), %xmm6
- vmovdqu 0x70(%rsp), %xmm7
- vmovdqu 0x80(%rsp), %xmm8
- vmovdqu 0x90(%rsp), %xmm9
- vmovdqu 0xa0(%rsp), %xmm10
- vmovdqu 0xb0(%rsp), %xmm11
- vmovdqu 0xc0(%rsp), %xmm12
- vmovdqu 0xd0(%rsp), %xmm13
- vmovdqu 0xe0(%rsp), %xmm14
- vmovdqu 0xf0(%rsp), %xmm15
+ movdqu 0x0(%rsp), %xmm0
+ movdqu 0x10(%rsp), %xmm1
+ movdqu 0x20(%rsp), %xmm2
+ movdqu 0x30(%rsp), %xmm3
+ movdqu 0x40(%rsp), %xmm4
+ movdqu 0x50(%rsp), %xmm5
+ movdqu 0x60(%rsp), %xmm6
+ movdqu 0x70(%rsp), %xmm7
+ movdqu 0x80(%rsp), %xmm8
+ movdqu 0x90(%rsp), %xmm9
+ movdqu 0xa0(%rsp), %xmm10
+ movdqu 0xb0(%rsp), %xmm11
+ movdqu 0xc0(%rsp), %xmm12
+ movdqu 0xd0(%rsp), %xmm13
+ movdqu 0xe0(%rsp), %xmm14
+ movdqu 0xf0(%rsp), %xmm15
add $0x100, %rsp
CFI_ADJUST_CFA_OFFSET(-0x100)
pop %r11
--
2.33.1
next reply other threads:[~2021-11-30 14:20 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-30 14:20 H.J. Lu [this message]
2021-12-06 15:59 ` Jakub Jelinek
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