From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by sourceware.org (Postfix) with ESMTPS id 0922B3858D28 for ; Wed, 15 Dec 2021 01:25:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0922B3858D28 X-IronPort-AV: E=McAfee;i="6200,9189,10197"; a="226400610" X-IronPort-AV: E=Sophos;i="5.88,207,1635231600"; d="scan'208";a="226400610" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2021 17:25:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,207,1635231600"; d="scan'208";a="545394280" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga001.jf.intel.com with ESMTP; 14 Dec 2021 17:25:45 -0800 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.236.50]) by scymds01.sc.intel.com with ESMTP id 1BF1PiTc011303; Tue, 14 Dec 2021 17:25:44 -0800 From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com Subject: [PATCH] [i386][avx512]Add combine splitter to transform vpternlogd/vpcmpeqd/vpxor/vblendvps to vblendvps for ~op0 Date: Wed, 15 Dec 2021 09:25:43 +0800 Message-Id: <20211215012543.18689-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Dec 2021 01:25:50 -0000 Hi all, This patch fix the regression previously reported on the combine splitter under '-m32 -march=cascadelake' options. Regtested on x86_64-pc-linux-gnu. BRs, Haochen gcc/ChangeLog: PR target/100738 * config/i386/sse.md (*avx_cmp3_lt, *avx_cmp3_ltint): Remove MEM_P restriction and add force_reg for operands[2]. (*avx_cmp3_ltint_not): Add new define_insn_and_split. gcc/testsuite/ChangeLog: PR target/100738 * g++.target/i386/avx512vl-pr100738-1.C: New test. --- gcc/config/i386/sse.md | 44 +++++++++++++++++-- .../g++.target/i386/avx512vl-pr100738-1.C | 8 ++++ 2 files changed, 48 insertions(+), 4 deletions(-) create mode 100755 gcc/testsuite/g++.target/i386/avx512vl-pr100738-1.C diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 5421fb51684..8ec9fb075d0 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -3528,8 +3528,7 @@ UNSPEC_PCMP)))] "TARGET_AVX512VL && ix86_pre_reload_split () /* LT or GE 0 */ - && ((INTVAL (operands[5]) == 1 && !MEM_P (operands[2])) - || (INTVAL (operands[5]) == 5 && !MEM_P (operands[1])))" + && ((INTVAL (operands[5]) == 1) || (INTVAL (operands[5]) == 5))" "#" "&& 1" [(set (match_dup 0) @@ -3543,6 +3542,7 @@ { if (INTVAL (operands[5]) == 5) std::swap (operands[1], operands[2]); + operands[2] = force_reg (mode, operands[2]); }) (define_insn_and_split "*avx_cmp3_ltint" @@ -3557,8 +3557,7 @@ UNSPEC_PCMP)))] "TARGET_AVX512VL && ix86_pre_reload_split () /* LT or GE 0 */ - && ((INTVAL (operands[5]) == 1 && !MEM_P (operands[2])) - || (INTVAL (operands[5]) == 5 && !MEM_P (operands[1])))" + && ((INTVAL (operands[5]) == 1) || (INTVAL (operands[5]) == 5))" "#" "&& 1" [(set (match_dup 0) @@ -3575,7 +3574,44 @@ std::swap (operands[1], operands[2]); operands[0] = gen_lowpart (mode, operands[0]); operands[1] = gen_lowpart (mode, operands[1]); + operands[2] = force_reg (mode, + gen_lowpart (mode, operands[2])); +}) + +(define_insn_and_split "*avx_cmp3_ltint_not" + [(set (match_operand:VI48_AVX 0 "register_operand") + (vec_merge:VI48_AVX + (match_operand:VI48_AVX 1 "vector_operand") + (match_operand:VI48_AVX 2 "vector_operand") + (unspec: + [(subreg:VI48_AVX + (not: + (match_operand: 3 "vector_operand")) 0) + (match_operand:VI48_AVX 4 "const0_operand") + (match_operand:SI 5 "const_0_to_7_operand")] + UNSPEC_PCMP)))] + "TARGET_AVX512VL && ix86_pre_reload_split () + /* not LT or GE 0 */ + && ((INTVAL (operands[5]) == 1) || (INTVAL (operands[5]) == 5))" + "#" + "&& 1" + [(set (match_dup 0) + (unspec: + [(match_dup 1) + (match_dup 2) + (subreg: + (lt:VI48_AVX + (match_dup 3) + (match_dup 4)) 0)] + UNSPEC_BLENDV))] +{ + if (INTVAL (operands[5]) == 5) + std::swap (operands[1], operands[2]); + operands[0] = gen_lowpart (mode, operands[0]); + operands[1] = force_reg (mode, + gen_lowpart (mode, operands[1])); operands[2] = gen_lowpart (mode, operands[2]); + operands[3] = lowpart_subreg (mode, operands[3], mode); }) (define_insn "avx_vmcmp3" diff --git a/gcc/testsuite/g++.target/i386/avx512vl-pr100738-1.C b/gcc/testsuite/g++.target/i386/avx512vl-pr100738-1.C new file mode 100755 index 00000000000..ac4d62b94d1 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/avx512vl-pr100738-1.C @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-Ofast -march=cascadelake" } */ +/* { dg-final {scan-assembler-times "vblendvps\[ \\t\]" 2 } } */ +/* { dg-final {scan-assembler-not "vpcmpeqd\[ \\t\]" } } */ +/* { dg-final {scan-assembler-not "vpxor\[ \\t\]" } } */ +/* { dg-final {scan-assembler-not "vpternlogd\[ \\t\]" } } */ + +#include "pr100738-1.C" -- 2.18.1